S-19190 Series www.sii-ic.com FOR AUTOMOTIVE 105°C OPERATION VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION © SII Semiconductor Corporation, 2015-2016 Rev.1.1_00 The S-19190 Series is a voltage monitoring IC with a cell balancing function and includes a high-accuracy voltage detection circuit and a delay circuit. The S-19190 Series is suitable for cell balancing and overcharge protection of batteries and capacitors. Caution This product can be used in vehicle equipment and in-vehicle equipment. Before using the product in the purpose, contact to SII Semiconductor Corporation is indispensable. Features • High-accuracy voltage detection circuit Cell balancing detection voltage: 2.0 V to 4.6 V (5 mV step) • • • • • • • • Accuracy ±12 mV (2.0 V ≤ V BU < 2.4 V) Accuracy ±0.5% (2.4 V ≤ V BU ≤ 4.6 V) *1 Accuracy ±24 mV (2.0 V ≤ V BL < 2.4 V) Cell balancing release voltage: 2.0 V to 4.6 V Accuracy ±1.0% (2.4 V ≤ V BL ≤ 4.6 V) Overcharge detection voltage: 2.0 V to 4.6 V (5 mV step) Accuracy ±12 mV (2.0 V ≤ V CU < 2.4 V) Accuracy ±0.5% (2.4 V ≤ V CU ≤ 4.6 V) *2 Accuracy ±24 mV (2.0 V ≤ V CL < 2.4 V) Overcharge release voltage: 2.0 V to 4.6 V Accuracy ±1.0% (2.4 V ≤ V CL ≤ 4.6 V) Built-in Nch transistor with ON resistance of 5 Ω typ. between the CB pin and the VSS pin Current consumption: 2.0 μA max. (Ta = +25°C) Delay times are generated only by an internal circuit (External capacitors are unnecessary). CO pin output form and output logic are selectable: CMOS output Active "H", active "L" Nch open-drain output Active "H", active "L" _____ Switchable to power-saving mode by using the CE pin Operation temperature range: Ta = −40°C to +105°C Lead-free (Sn 100%), halogen-free AEC-Q100 in process *3 *1. *2. *3. Cell balancing release voltage = Cell balancing detection voltage − Cell balancing hysteresis voltage (Cell balancing hysteresis voltage can be selected as 0 V or from a range of 0.1 V to 0.7 V in 50 mV step.) Overcharge release voltage = Overcharge detection voltage − Overcharge hysteresis voltage (Overcharge hysteresis voltage can be selected as 0 V or from a range of 0.1 V to 0.7 V in 50 mV step.) Contact our sales office for details. Applications • Rechargeable battery module • Capacitor module Package • SOT-23-6 1 FOR AUTOMOTIVE 105°C OPERATION VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.1_00 S-19190 Series Block Diagram VDD CB + Control circuit − CO Delay circuit + − DP 1 MΩ Power-saving mode _____ CE switching circuit 1 MΩ VSS *1. All diodes shown in the figure are parasitic diodes. Figure 1 2 FOR AUTOMOTIVE 105°C OPERATION VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.1_00 S-19190 Series AEC-Q100 in Process Contact our sales office for details of AEC-Q100 reliability specification. Product Name Structure 1. Product name S-19190 xx H - M6T1 U Environmental code U: Lead-free (Sn 100%), halogen-free Package abbreviation and IC packing specifications M6T1: SOT-23-6, Tape *1 Operation temperature H: Ta = −40°C to +105°C Serial code Sequentially set from AA to ZZ *1. Refer to the tape drawing. 2. Package Table 1 Package Drawing Codes Package Name SOT-23-6 Dimension Tape Reel MP006-A-P-SD MP006-A-C-SD MP006-A-R-SD 3 FOR AUTOMOTIVE 105°C OPERATION VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.1_00 S-19190 Series 3. Product name list Table 2 Product Name Cell Balancing Detection Voltage [V BU ] Cell Balancing Release Voltage [V BL ] Overcharge Detection Voltage [V CU ] Overcharge Release Voltage [V CL ] CO Pin Output Form S-19190AOH-M6T1U 2.000 V 2.000 V 3.000 V 3.000 V CMOS output Remark CO Pin Output Logic Combination of Delay Time Active "H" (1) 1. Contact our sales office for the products with detection voltage values other than those specified above. 2. Set V CU > V BU . 3. Refer to Table 3 for details about combinations of delay times. Table 3 Combination of Delay Time Cell Balancing Detection Delay Time [t BU ] Cell Balancing Release Delay Time [t BL ] Overcharge Detection Delay Time [t CU ] Overcharge Release Delay Time [t CL ] (1) 128 ms 1.0 ms 128 ms 1.0 ms Remark The delay times can be changed within the ranges listed above. For details, please contact our sales office. Table 4 Delay Time Cell balancing detection *1 delay time Cell balancing release delay time Overcharge detection delay *1 time Overcharge release delay time *1. Set t CU ≥ t BU . *2. The value is the delay time 4 Symbol Selection Range Remark t BU 64 ms 128 ms *2 256 ms t BL 0.5 ms 1.0 ms *2 2.0 ms t CU 64 ms 128 ms *2 256 ms t CL 0.5 ms 1.0 ms *2 2.0 ms of the standard products. Select a value from the left. Select a value from the left. Select a value from the left. Select a value from the left. FOR AUTOMOTIVE 105°C OPERATION VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.1_00 S-19190 Series Pin Configuration 1. SOT-23-6 Table 5 Top view 6 5 4 Pin No. 1 2 3 1 2 3 4 Symbol CO VSS DP _____ CE Figure 2 5 VDD 6 CB Description Output pin for overcharge signal Input pin for negative power supply Test mode switching pin "H": Test mode (used to shorten the delay time) "L": Normal operation mode Power-saving mode switching pin "H": Power-saving mode "L": Normal operation mode Input pin for positive power supply Output pin for cell balancing signal (Nch open-drain output) 5 FOR AUTOMOTIVE 105°C OPERATION VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.1_00 S-19190 Series Absolute Maximum Ratings Table 6 Item Symbol Applied Pin Input voltage between VDD pin and V DS VDD VSS pin _____ CE , DP Input pin voltage VIN Output pin voltage VOUT CO, CB Operation ambient temperature T opr − Storage temperature T stg − Caution The absolute maximum ratings are rated values physical damage. These values must therefore not (Ta = +25°C unless otherwise specified) Absolute Maximum Rating Unit V SS − 0.3 to V SS + 6.0 V V V SS − 0.3 to V DD + 0.3 ≤ V SS + 6.0 V SS − 0.3 to V DD + 0.3 ≤ V SS + 6.0 V −40 to +105 °C −55 to +125 °C exceeding which the product could suffer be exceeded under any conditions. Thermal Resistance Value Table 7 Item Condition Board 1 Junction-to-ambient thermal resistance *1 θ ja SOT-23-6 Board 2 *1. Test environment: compliance with JEDEC STANDARD JESD51-2A Remark 6 Symbol Min. − − Typ. 159 124 Refer to " Thermal Characteristics" for details of power dissipation and test board. Max. − − Unit °C/W °C/W FOR AUTOMOTIVE 105°C OPERATION VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.1_00 S-19190 Series Electrical Characteristics For details about the test circuits and testing method, refer to " Test Circuit". Caution Unless otherwise specified in Table 8 and Table 9, set V2 = V3 = 0 V, and SWn (n = 1 to 4) = OFF. 1. Ta = +25°C Table 8 (1 / 2) Item Detection voltage Symbol Condition (Ta = +25°C unless otherwise specified) Min. Typ. Max. Unit 2.0 V ≤ V BU < 2.4 V Cell balancing detection voltage V BU Cell balancing release voltage V BL Overcharge detection voltage V CU Overcharge release voltage V CL SW1 = ON 2.4 V ≤ V BU ≤ 4.6 V 2.0 V ≤ V BL < 2.4 V SW1 = ON 2.4 V ≤ V BL ≤ 4.6 V 2.0 V ≤ V CU < 2.4 V 2.4 V ≤ V CU ≤ 4.6 V 2.0 V ≤ V CL < 2.4 V 2.4 V ≤ V CL ≤ 4.6 V Input voltage Operation voltage between V DS VDD pin and VSS pin V BU − 0.012 V BU × 0.995 V BL − 0.024 V BL × 0.99 V CU − 0.012 V CU × 0.995 V CL − 0.024 V CL × 0.99 V BU V BU V BL V BL V CU V CU V CL V CL V BU + 0.012 V BU × 1.005 V BL + 0.024 V BL × 1.01 V CU + 0.012 V CU × 1.005 V CL + 0.024 V CL × 1.01 V V V V V V V V Voltages output from CO pin and CB pin are fixed 1.5 − 5.0 V VCEH − − − V DD × 0.9 V CE pin voltage "L" VCEL − V DD × 0.1 − − V DP pin voltage "H" VDPH − − − V DD × 0.9 V DP pin voltage "L" VDPL − V DD × 0.1 − − V _____ CE pin voltage "H" _____ Input current Current consumption during operation Current consumption during power-saving _____ _____ I OPE I VDD when V1 = V BL − 0.1 V − 1.2 2.0 μA I PSV I VDD when V1 = V2 = V BL − 0.1 V − − 0.1 μA 7 FOR AUTOMOTIVE 105°C OPERATION VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.1_00 S-19190 Series Table 8 (2 / 2) Item Delay time Cell balancing detection delay time Cell balancing release delay time Overcharge detection delay time Overcharge release delay time Output current CB pin output current Symbol (Ta = +25°C unless otherwise specified) Min. Typ. Max. Unit t BU − t BU × 0.8 t BU t BU × 1.2 ms t BL − t BL × 0.8 t BL t BL × 1.2 ms t CU × 0.8 t CU t CU × 1.2 ms t CL × 0.8 t CL t CL × 1.2 ms − mA 0.1 μA − mA − mA − mA − mA − mA 0.1 μA − mA 0.1 μA t CU t CL CB pin sink current ICBS CB pin leakage current I CBL CO pin output current (output form: CO pin sink current I COL CO pin source current ICOH CO pin output current (output form: CO pin sink current I COL CO pin source current ICOH CO pin output current (output form: CO pin sink current I COL CO pin leakage current I COHL CO pin output current (output form: 8 Condition CO pin sink current I COL CO pin leakage current I COHL − − V1 = V BU + 0.1 V, SW2 = ON, 30 − V4 = 0.5 V V1 = V BL − 0.1 V, SW2 = ON, − − V4 = 6.0 V CMOS output, output logic: active "H") V1 = V CL − 0.1 V, SW4 = ON, 5.0 − V5 = 0.5 V V1 = V CU + 0.1 V, SW4 = ON, 1.0 − V5 = V1 − 0.5 V CMOS output, output logic: active "L") V1 = V CU + 0.1 V, SW4 = ON, 5.0 − V5 = 0.5 V V1 = V CL − 0.1 V, SW4 = ON, 1.0 − V5 = V1 − 0.5 V Nch open-drain output, output logic: active "H") V1 = V CL − 0.1 V, SW4 = ON, 5.0 − V5 = 0.5 V V1 = V CU + 0.1 V, SW4 = ON, − − V5 = 6.0 V Nch open-drain output, output logic: active "L") V1 = V CU + 0.1 V, SW4 = ON, 5.0 − V5 = 0.5 V V1 = V CL − 0.1 V, SW4 = ON, − − V5 = 6.0 V FOR AUTOMOTIVE 105°C OPERATION VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.1_00 S-19190 Series 2. Ta = −40°C to +105°C Item Detection voltage Symbol Table 9 (1 / 2) (Ta = −40°C to +105°C unless otherwise specified) Condition Min. Typ. Max. Unit 2.0 V ≤ V BU < 2.4 V Cell balancing detection voltage V BU Cell balancing release voltage V BL Overcharge detection voltage V CU Overcharge release voltage V CL SW1 = ON 2.4 V ≤ V BU ≤ 4.6 V 2.0 V ≤ V BL < 2.4 V SW1 = ON 2.4 V ≤ V BL ≤ 4.6 V 2.0 V ≤ V CU < 2.4 V 2.4 V ≤ V CU ≤ 4.6 V 2.0 V ≤ V CL < 2.4 V 2.4 V ≤ V CL ≤ 4.6 V Input voltage Operation voltage between V DS VDD pin and VSS pin V BU − 0.040 V BU × 0.984 V BL − 0.080 V BL × 0.968 V CU − 0.040 V CU × 0.984 V CL − 0.080 V CL × 0.968 V BU V BU V BL V BL V CU V CU V CL V CL V BU + 0.040 V BU × 1.016 V BL + 0.080 V BL × 1.032 V CU + 0.040 V CU × 1.016 V CL + 0.080 V CL × 1.032 V V V V V V V V Voltages output from CO pin and CB pin are fixed 1.5 − 5.0 V VCEH − − − V DD × 0.9 V CE pin voltage "L" VCEL − V DD × 0.1 − − V DP pin voltage "H" VDPH − − − V DD × 0.9 V DP pin voltage "L" VDPL − V DD × 0.1 − − V _____ CE pin voltage "H" _____ Input current Current consumption during operation Current consumption during power-saving _____ _____ I OPE I VDD when V1 = V BL − 0.1 V − 1.2 2.1 μA I PSV I VDD when V1 = V2 = V BL − 0.1 V − − 0.15 μA 9 FOR AUTOMOTIVE 105°C OPERATION VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.1_00 S-19190 Series Item Delay time Cell balancing detection delay time Cell balancing release delay time Overcharge detection delay time Overcharge release delay time Output current CB pin output current Symbol t BU − t BU × 0.5 t BU t BU × 1.5 ms t BL − t BL × 0.5 t BL t BL × 1.5 ms t CU × 0.5 t CU t CU × 1.5 ms t CL × 0.5 t CL t CL × 1.5 ms − mA 0.15 μA − mA − mA − mA − mA − mA 0.15 μA − mA 0.15 μA t CU t CL CB pin sink current ICBS CB pin leakage current I CBL CO pin output current (output form: CO pin sink current I COL CO pin source current ICOH CO pin output current (output form: CO pin sink current I COL CO pin source current ICOH CO pin output current (output form: CO pin sink current I COL CO pin leakage current I COHL CO pin output current (output form: 10 Table 9 (2 / 2) (Ta = −40°C to +105°C unless otherwise specified) Condition Min. Typ. Max. Unit CO pin sink current I COL CO pin leakage current I COHL − − V1 = V BU + 0.1 V, SW2 = ON, 30 − V4 = 0.5 V V1 = V BL − 0.1 V, SW2 = ON, − − V4 = 6.0 V CMOS output, output logic: active "H") V1 = V CL − 0.1 V, SW4 = ON, 5.0 − V5 = 0.5 V V1 = V CU + 0.1 V, SW4 = ON, 1.0 − V5 = V1 − 0.5 V CMOS output, output logic: active "L") V1 = V CU + 0.1 V, SW4 = ON, 5.0 − V5 = 0.5 V V1 = V CL − 0.1 V, SW4 = ON, 1.0 − V5 = V1 − 0.5 V Nch open-drain output, output logic: active "H") V1 = V CL − 0.1 V, SW4 = ON, 5.0 − V5 = 0.5 V V1 = V CU + 0.1 V, SW4 = ON, − − V5 = 6.0 V Nch open-drain output, output logic: active "L") V1 = V CU + 0.1 V, SW4 = ON, 5.0 − V5 = 0.5 V V1 = V CL − 0.1 V, SW4 = ON, − − V5 = 6.0 V FOR AUTOMOTIVE 105°C OPERATION VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.1_00 S-19190 Series Test Circuit RCB = 100 kΩ RCO = 100 kΩ SW1 SW3 SW2 SW4 IVDD A VDD CO S-19190 V1 Series CB DP _____ VSS CE V2 V3 V4 V5 ICB A ICO A Figure 3 Caution Unless otherwise specified in Table 8, set V2 = V3 = 0 V, and SWn (n = 1 to 4) = OFF. _____ 1. CE pin voltage "H" _____ CE pin voltage "H" (V C E H ) is defined as the voltage at which I VDD is changed from I OPE to I PSV when V2 is increased from 0 V after setting V1 = V BL − 0.1 V. _____ _____ 2. CE pin voltage "L" _____ CE pin voltage "L" (V C E L ) is defined as the voltage at which I VDD is changed from I PSV to I OPE when V2 is decreased from V BL − 0.1 V after setting V1 = V2 = V BL − 0.1 V. _____ 3. DP pin voltage "H" *1 DP pin voltage "H" (V DPH ) is defined as the voltage at which the test mode is switched when V3 is increased from 0 V after setting V1 = V BL − 0.1 V. 4. DP pin voltage "L" *1 DP pin voltage "L" (V DPL ) is defined as the voltage at which the normal operation mode is switched when V3 is decreased from V BL − 0.1 V after setting V1 = V3 = V BL − 0.1 V. 5. Cell balancing detection delay time Cell balancing detection delay time (t BU ) is defined as the time from when SW1 is set to ON and V1 is set to V BU − 0.1 V to when the CB pin output is inverted after setting V1 to V BU + 0.1 V. 6. Cell balancing release delay time Cell balancing release delay time (t BL ) is defined as the time from when SW1 is set to ON and V1 is set to VBL + 0.1 V to when the CB pin output is inverted after setting V1 to V BL − 0.1 V. 7. Overcharge detection delay time Overcharge detection delay time (t CU ) is defined as the time from when SW1 is set to ON and V1 is set to V CU − 0.1 V to when the CO pin output is inverted after setting V1 to V CU + 0.1 V. 8. Overcharge release delay time Overcharge release delay time (t CL ) is defined as the time from when SW1 is set to ON and V1 is set to V CL + 0.1 V to when the CO pin output is inverted after setting V1 to V CL − 0.1 V. *1. For details about switching to the test mode by using the DP pin, refer to "5. DP pin" in " Operation". 11 FOR AUTOMOTIVE 105°C OPERATION VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.1_00 S-19190 Series Standard Circuit VDD RVDD CO CVDD S-19190 CB RCB DP Series _____ VSS CE Figure 4 Table 10 Constants for External Components Symbol Part R VDD Resistor C VDD Capacitor R CB Resistor Purpose ESD protection, for power fluctuation control For power fluctuation control For setting the cell balancing current value Min. Typ. Max. Remark 150 Ω 330 Ω 1.0 kΩ Resistance should be as small as possible to avoid worsening the overcharge detection *1 accuracy due to current consumption. 0.068 μF 0.1 μF 1.0 μF Connect a capacitor of 0.068 μF or more *1 between VDD pin and VSS pin. − − − Set the required cell balancing current value depending on "2. Cell balancing status" in " Operation". *2 *1. When connecting a resistor less than 150 Ω to R VDD or a capacitor less than 0.068 μF to C VDD , the S-19190 Series may malfunction when power is largely fluctuated. *2. Set the cell balancing current value so that R CB does not exceed the power dissipation. Cautions 1. The above constants may be changed without notice. 2. The example of connection shown above and the constant do not guarantee proper operation. Perform thorough evaluation using the actual application to set the constant. 12 FOR AUTOMOTIVE 105°C OPERATION VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.1_00 S-19190 Series Operation Remark Refer to " Standard Circuit ". 1. Normal status In the S-19190 Series, if the voltage between the VDD pin and the VSS pin (V DS ) has not reached the cell balancing detection voltage (V BU ), the CB pin output is in the high-impedance status. The CO pin output status varies according to the output form and output logic selected, as shown in Table 11. This is the normal status. Table 11 CO Pin Output Form and Output Logic CB Pin Output CO Pin Output CMOS output, active "H" "H" "L" CMOS output, active "L" "H" "H" Nch open-drain output, active "H" "H" "L" Nch open-drain output, active "L" "H" "H" 2. Cell balancing status In the S-19190 Series, if V DS is V BU or higher and this status continues for the cell balancing detection delay time (t BU ) or longer, the CB pin output becomes "L". This is the cell balancing status. The cell balancing status is released when V DS drops to the cell balancing release voltage (V BL ) or lower and this status continues for the cell balancing release delay time (tBL ) or longer. The S-19190 Series includes an Nch transistor with ON resistance of 5 Ω typ. (R CBON ) between the CB pin and the VSS pin, thus causing the cell balancing current (I CB ) to flow in cell balancing status, and the cell balancing operation to start. By connecting a resistor (R CB ) to the CB pin, I CB in cell balancing status can be calculated by using the following equation. I CB = V BU / (R CBON + R CB ) S-19190 Series VDD CB RCB ICB Control circuit VSS RCBON = 5 Ω typ. Figure 5 13 FOR AUTOMOTIVE 105°C OPERATION VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.1_00 S-19190 Series 3. Overcharge status In the S-19190 Series, if VDS is the overcharge detection voltage (V CU ) or higher and this status continues for the overcharge detection delay time (t CU ) or longer, the CO pin output is inverted. The CO pin output status varies according to the output form and output logic selected, as shown in Table 12. This is the overcharge status. In the overcharge status, the CB pin output becomes "L". Table 12 CO Pin Output Form and Output Logic CB Pin Output CO Pin Output CMOS output, active "H" "L" "H" CMOS output, active "L" "L" "L" Nch open-drain output, active "H" "L" "H" Nch open-drain output, active "L" "L" "L" The overcharge status is released when VDS drops to the overcharge release voltage (V CL ) or lower and this status continues for the overcharge release delay time (t CL ) or longer. _____ 4. CE pin _____ The S-19190 Series has the CE pin (Power-saving mode switching pin). The S-19190 Series is set to _____ power-saving mode by inputting a voltage of V C E H or higher to the CE pin. _____ _____ Table 13 CE Pin Open (V C E = V SS ) Status Normal operation mode "H" (V C E ≥ V C E H ) Power-saving mode "L" (V C E ≤ V C E L ) Normal operation mode _____ _____ _____ _____ _____ In power-saving mode, the current consumption is decreased to current consumption during power-saving (I PSV ). The CB pin or the CO pin output in power-saving mode is the same as that in the normal status. _____ The_____ CE pin is pulled down to V SS by the internal resistor. When in a mode other than power-saving mode, leave the CE pin open or short it with V SS . 14 FOR AUTOMOTIVE 105°C OPERATION VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.1_00 S-19190 Series 5. DP pin The S-19190 Series has the DP pin (Test mode switching pin). The S-19190 Series is set to test mode (used to shorten the delay time) by inputting a voltage of V DPH or higher to the DP pin. Table 14 DP Pin Open (V DP = V SS ) "H" (V DP ≥ V DPH ) "L" (V DP ≤ V DPL ) Status Normal operation mode Test mode Normal operation mode In test mode, the cell balancing detection delay time (t BU ) and overcharge detection delay time (t CU ) are shortened to 1/64 of the delay time in the normal operation mode. The DP pin is pulled down to VSS by the internal resistor. When in a mode other than test mode, leave the DP pin open or short it with V SS . 15 FOR AUTOMOTIVE 105°C OPERATION VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.1_00 S-19190 Series Timing Chart VCU VCL (VCU − VHC) Battery voltage VBU VBL (VBU − VHB) VCB *1 CB pin voltage VSS VDD CO pin voltage (Active "H") VSS VDD CO pin voltage (Active "L") VSS Charger connection Cell balancing detection delay time (tBU) tBU Cell balancing release delay time (tBL) Status *2 (1) (2) (1) *1. The CB pin is pulled up by the external resistor. *2. (1): Normal status (2): Cell balancing status (3): Overcharge status Remark The charger is assumed to charge with a constant current. Figure 6 16 Overcharge detection delay time (tCU) Overcharge release delay time (tCL) (2) (3) (2) tBL (1) FOR AUTOMOTIVE 105°C OPERATION VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.1_00 S-19190 Series Precautions • The application conditions for the input voltage, output voltage, and load current should not exceed the power dissipation. • Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit. • SII Semiconductor Corporation claims no responsibility for any and all disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party. 17 FOR AUTOMOTIVE 105°C OPERATION VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.1_00 S-19190 Series Characteristics (Typical Data) 1. Current consumption 1. 2 I PSV vs. Ta 1. 1 I OPE vs. Ta V DD = V BL − 0.1 V 2.50 2.00 0.08 IPSV [A] IOPE [A] V DD = V BL − 0.1 V 0.10 1.50 1.00 0.50 0.06 0.04 0.02 0.00 40 25 0 25 50 Ta [C] 75 105 4.0 5.0 0.00 40 25 0 25 50 Ta [C] 75 105 1. 3 I OPE vs. V DD IOPE [A] 4.00 3.00 2.00 1.00 0.00 0.0 1.0 2.0 3.0 VDD [V] 2. Cell balancing detection / release voltage, overcharge detection / release voltage and delay times 2. 2 V BL vs. Ta 2.62 2.64 2.61 2.62 VBL [V] VBU [V] 2. 1 V BU vs. Ta 2.60 2.59 2.58 40 25 2.58 0 25 50 Ta [C] 75 2.77 2.79 2.76 2.77 2.75 2.74 2.73 40 25 0 25 50 Ta [C] 75 105 0 25 50 Ta [C] 75 105 2. 4 V CL vs. Ta VCL [V] VCU [V] 2.56 40 25 105 2. 3 V CU vs. Ta 18 2.60 2.75 2.73 0 25 50 Ta [C] 75 105 2.71 40 25 FOR AUTOMOTIVE 105°C OPERATION VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.1_00 S-19190 Series 2. 5 t BU vs. Ta 2. 6 t BL vs. Ta 1.2 1.1 140 tBL [ms] tBU [ms] 160 120 0.9 100 40 25 0 25 50 Ta [C] 75 0.8 40 25 105 2. 7 t CU vs. Ta 0 25 50 Ta [C] 75 105 0 25 50 Ta [C] 75 105 2. 8 t CL vs. Ta 160 1.2 1.1 140 tCL [ms] tCU [ms] 1.0 120 1.0 0.9 100 40 25 0 25 50 Ta [C] 75 0.8 40 25 105 3. Output current 3. 1 I CBH vs. V CB 3. 2 I CBL vs. V CB Ta = +25°C, V DD = V BL − 0.1 V Ta = +25°C, V DD = V BU + 0.1 V 0.10 400 ICBL [mA] ICBH [A] 0.08 0.06 0.04 0.02 0.00 300 200 100 0 0.0 1.0 2.0 3.0 VCB [V] 4.0 5.0 3. 3 I COH vs. V CO 0.0 2.0 3.0 VCB [V] 4.0 5.0 3. 4 I COL vs. V CO Ta = +25°C, V DD = V CU + 0.1 V Ta = +25°C, V DD = V CL − 0.1 V 8.0 40.0 6.0 30.0 ICOL [mA] ICOH [mA] 1.0 4.0 2.0 0.0 20.0 10.0 0.0 0.0 0.5 1.0 1.5 2.0 VCO [V] 2.5 3.0 0.0 0.5 1.0 1.5 2.0 VCO [V] 2.5 3.0 19 FOR AUTOMOTIVE 105°C OPERATION VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.1_00 S-19190 Series Thermal Characteristics 1. SOT-23-6 Tj = 125C max. Power dissipation (PD) [W] 1.0 Board 2 0.81 W 0.8 0.6 Board 1 0.63 W 0.4 0.2 0 0 50 100 150 Ambient temperature (Ta) [C] Figure 7 Power Dissipation of Package (When Mounted on Board) 1. 1 Board 1 *1 76.2 mm 114.3 mm Table 15 Item Thermal resistance value (θ ja ) Size Material Number of copper foil layer 1 2 Copper foil layer 3 4 Thermal via Specification 159°C/W 114.3 mm × 76.2 mm × t1.6 mm FR-4 2 Land pattern and wiring for testing: t0.070 mm − − 74.2 mm × 74.2 mm × t0.070 mm − Figure 8 1. 2 Board 2 *1 76.2 mm 114.3 mm Table 16 Item Thermal resistance value (θ ja ) Size Material Number of copper foil layer 1 2 Copper foil layer 3 4 Thermal via Figure 9 *1. The board is same in SOT-23-3, SOT-23-5 and SOT-23-6. 20 Specification 124°C/W 114.3 mm × 76.2 mm × t1.6 mm FR-4 4 Land pattern and wiring for testing: t0.070 mm 74.2 mm × 74.2 mm × t0.035 mm 74.2 mm × 74.2 mm × t0.035 mm 74.2 mm × 74.2 mm × t0.070 mm − 2.9±0.2 1.9±0.2 6 0.95 4 5 1 2 3 +0.1 0.15 -0.05 0.95 0.35±0.15 No. MP006-A-P-SD-2.1 TITLE SOT236-A-PKG Dimensions No. MP006-A-P-SD-2.1 ANGLE UNIT mm SII Semiconductor Corporation 4.0±0.1(10 pitches:40.0±0.2) +0.1 ø1.5 -0 +0.2 ø1.0 -0 2.0±0.05 0.25±0.1 4.0±0.1 1.4±0.2 3.2±0.2 3 2 1 4 5 6 Feed direction No. MP006-A-C-SD-3.1 TITLE SOT236-A-Carrier Tape No. MP006-A-C-SD-3.1 ANGLE UNIT mm SII Semiconductor Corporation 12.5max. 9.0±0.3 Enlarged drawing in the central part ø13±0.2 (60°) (60°) No. MP006-A-R-SD-2.1 TITLE SOT236-A-Reel No. MP006-A-R-SD-2.1 ANGLE QTY UNIT 3,000 mm SII Semiconductor Corporation Disclaimers (Handling Precautions) 1. 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