IDT74ALVCH16270 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS AND BUS-HOLD IDT74ALVCH16270 DESCRIPTION: FEATURES: This registered bus exchanger is built using advanced dual metal CMOS technology. The ALVCH16270 is used in applications in which data must be transferred from a narrow high-speed bus to a wide lower-frequency bus. This device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate clock-enable (CLKEN) inputs are low. The select (SEL) line selects 1B or 2B data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of the CLKENA input allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B-port. Data flow is controlled by the active-low output enables (OEA and OEB). The control terminals are registered to synchronize the bus-direction changes with CLK. The ALVCH16270 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The ALVCH16270 has “bus-hold” which retains the inputs’ last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • VCC = 2.5V ± 0.2V µ W typ. static) • CMOS power levels (0.4µ • Rail-to-Rail output swing for increased noise margin • Available in SSOP, TSSOP, and TVSOP packages DRIVE FEATURES: • High Output Drivers: ±24mA • Suitable for heavy loads APPLICATIONS: • 3.3V high speed systems • 3.3V and lower voltage computing systems FUNCTIONAL BLOCK DIAGRAM 29 C LK 2 CLKEN1B 27 CLKEN2B 30 CLKENA1 55 CLKENA2 C1 56 OEB 1D 28 SEL 1 OEA CE C1 1D 1D 23 1B 1 C1 A1 CE C1 0 8 1D 1 CE C1 CE C1 1D 1D 6 2B 1 CE C1 1D 1 of 12 Channels The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE AUGUST 1999 1 © 1999 Integrated Device Technology, Inc. DSC-4475/1 IDT74ALVCH16270 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol Description VTERM(2) Max Unit Terminal Voltage with Respect to GND –0.5 to +4.6 V OEA 1 56 OEB VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V CLKEN1B 2 55 CLKENA2 TSTG Storage Temperature –65 to +150 °C 2B3 3 54 2B4 IOUT DC Output Current –50 to +50 mA IIK Continuous Clamp Current, VI < 0 or VI > VCC ±50 mA IOK Continuous Clamp Current, VO < 0 –50 mA ICC ISS Continuous Current through each VCC or GND ±100 mA GND 4 53 GND 2B2 5 52 2B5 2B1 6 51 2B6 VCC 7 50 VCC A1 8 49 2B7 A2 9 48 2B8 A3 10 47 2B9 GND 11 46 GND A4 12 45 2B10 A5 13 44 2B11 A6 14 43 2B12 A7 15 42 1B12 A8 16 41 1B11 A9 17 40 1B10 GND 18 39 GND A10 19 38 1B9 A11 20 37 1B8 A12 21 36 1B7 VCC 22 35 VCC 1B1 23 34 1B6 1B2 24 33 1B5 CLK OEA OEB Ax 1Bx, 2Bx GND 25 32 GND ↑ H H Z Z 1B3 26 31 1B4 ↑ H L Z Active CLKEN2B 27 30 CLKENA1 ↑ L H Active Z SEL 28 29 CLK ↑ L L Active Active NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. CAPACITANCE (TA = +25°C, F = 1.0MHz) Symbol Parameter(1) Conditions Typ. Max. CIN Input Capacitance VIN = 0V 5 7 Unit pF COUT Output Capacitance VOUT = 0V 7 9 pF CI/O I/O Port Capacitance VIN = 0V 7 9 pF NOTE: 1. As applicable to the device type. FUNCTION TABLES(1) OUTPUT ENABLE Inputs Outputs B-TO-A STORAGE (OEA = L AND OEB = H) SSOP/ TSSOP/ TVSOP TOP VIEW Inputs A-TO-B STORAGE (OEB = L AND OEA = H) Inputs Outputs CLKENA1 CLKENA2 CLK Ax 1Bx 2Bx L H ↑ L 1B0(2) 2B0(2) L H ↑ H 1B0(2) 2B0(2) L L L L ↑ ↑ L H L(3) H (3) L H H L ↑ L 1B0(4) L H L ↑ H 1B0(4) H H H X or ↑ X 1B0(2) 2B0(2) Outputs CLKENB1 CLKENB2 CLK SEL 1Bx 2Bx Ax H X X H X X A0(2) X H X L X X A0(2) L X ↑ H L X L L X ↑ H H X H X L ↑ L X L L X L ↑ L X H H NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance ↑ = LOW-to-HIGH transition 2. Output level before the indicated steady-state input conditions were established. 3. Two CLK edges are needed to propagate data. 4. Data present at the output of the first register. 2 IDT74ALVCH16270 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER INDUSTRIAL TEMPERATURE RANGE PIN DESCRIPTION Pin Names I/O Description Ax(1:12) I/O Bidirectional Data Port A. Usually connected to the CPU’s Address/Data bus.(1) 1Bx(1:12) I/O Bidirectional Data Port 1B. Usually connected to the even path or even bank of memory.(1) 2Bx(1:12) I/O Bidirectional Data Port 2B. Usually connected to the odd path or odd bank of memory.(1) CLK I Clock Input CLKENA1 I Clock Enable Input for the A-1B Register. If CLKENA1 is LOW during the rising edge of CLK, data will be clocked into register A-1B (Active LOW). CLKENA2 I Clock Enable Input for the A-2B Register. If CLKENA2 is LOW during the rising edge of CLK, data will be clocked into register A-2B (Active LOW). CLKEN1B I Clock Enable Input for the 1B-A Register. If CLKEN1B is LOW during the rising edge of CLK, data will be clocked into register 1B-A (Active LOW). CLKEN2B I Clock Enable Input for the 2B-A Register. If CLKEN2B is LOW during the rising edge of CLK, data will be clocked into register 2B-A (Active LOW). SEL I 1B or 2B Port Selection. When HIGH during the rising edge of CLK, SEL enables data transfer from 1B Port to A Port. When LOW during the rising OEA I Synchronous Output Enable for A Port (Active LOW) OEB I Synchronous Output Enable for B Port (Active LOW) edge of CLK, SEL enables data transfer from 2B Port to A Port. NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V IIH Input HIGH Current VCC = 3.6V VI = VCC — — ±5 µA IIL Input LOW Current VCC = 3.6V VI = GND — — ±5 µA IOZH High Impedance Output Current VCC = 3.6V VO = VCC — — ±10 µA IOZL (3-State Output pins) VO = GND — — ±10 VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ∆ICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 0.1 — 40 mV µA Quiescent Power Supply Current Variation One input at VCC - 0.6V, other inputs at VCC or GND — — 750 µA NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. 3 IDT74ALVCH16270 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER INDUSTRIAL TEMPERATURE RANGE BUS-HOLD CHARACTERISTICS Symbol IBHH Parameter(1) Test Conditions Bus-Hold Input Sustain Current VCC = 3V VI = 2V IBHL IBHH Bus-Hold Input Sustain Current VCC = 2.3V IBHL IBHHO Bus-Hold Input Overdrive Current Min. VCC = 3.6V Typ.(2) Max. Unit µA – 75 — — VI = 0.8V 75 — — VI = 1.7V – 45 — — VI = 0.7V 45 — — — ±500 VI = 0 to 3.6V — µA µA IBHLO NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25°C ambient. OUTPUT DRIVE CHARACTERISTICS Symbol VOH VOL Test Conditions(1) Parameter Output HIGH Voltage Output LOW Voltage Min. Max. Unit VCC – 0.2 — V VCC = 2.3V to 3.6V IOH = – 0.1mA VCC = 2.3V IOH = – 6mA 2 — VCC = 2.3V IOH = – 12mA 1.7 — VCC = 2.7V 2.2 — VCC = 3V 2.4 — VCC = 3V IOH = – 24mA 2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3V IOL = 24mA — 0.55 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. OPERATING CHARACTERISTICS, TA = 25°C Symbol Parameter CPD Power Dissipation Capacitance Outputs enabled CPD Power Dissipation Capacitance Outputs disabled VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Test Conditions Typical Typical Unit CL = 0pF, f = 10Mhz 87 120 pF 80.5 118 4 IDT74ALVCH16270 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS(1) VCC = 2.5V ± 0.2V Symbol Parameter fMAX VCC = 2.7V VCC = 3.3V ± 0.3V Min. Max. Min. Max. Min. Max. Unit 150 — 150 — 150 — MHz 1.5 5.9 — 5.8 1.1 5.1 ns 1.2 5.4 — 5.4 1 4.7 ns 1.4 6.2 — 6.4 1 5.5 ns 1.5 7 — 6.8 1 6 ns 1.5 7 — 6.8 1 6 ns 1.9 7.2 — 6.5 1.1 5.8 ns 1.9 7.2 — 6.5 1.1 5.8 ns tPLH Propagation Delay tPHL CLK to xBx tPLH Propagation Delay tPHL CLK to Ax tPLH Propagation Delay tPHL SEL to Ax tPZH Output Enable Time tPZL CLK to xBx tPZH Output Enable Time tPZL CLK to Ax tPHZ Output Disable Time tPLZ CLK to xBx tPHZ Output Disable Time tPLZ CLK to Ax tSU Set-up Time, Ax data before CLK↑ 4.1 — 3.8 — 3.1 — ns tSU Set-up Time, Bx data before CLK↑ 0.9 — 1.2 — 0.9 — ns tSU Set-up Time, CLKENA1 or CLKENA2 before CLK↑ 3.5 — 3.2 — 2.7 — ns tSU Set-up Time, CLKEN1B or CLKEN2B before CLK↑ 3.4 — 3 — 2.6 — ns tSU Set-up Time, OEB or OEA before CLK↑ 4.4 — 3.9 — 3.2 — ns tH Hold Time, Ax data after CLK↑ 0 — 0 — 0.2 — ns tH Hold Time, Bx data after CLK↑ 1.4 — 1 — 1.7 — ns tH Hold Time, CLKENA1 or CLKENA2 after CLK↑ 0 — 0.1 — 0.3 — ns tH Hold Time, CLKEN1B or CLKEN2B after CLK↑ 0 — 0 — 0.6 — ns tH Hold Time, OEB or OEA after CLK↑ 0 — 0 — 0.1 — ns tW Pulse Width, CLK HIGH or LOW 3.3 — 3.3 — 3.3 — ns Output Skew(2) — — — — — 500 ps tSK(O) NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 5 IDT74ALVCH16270 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS VCC(1)= 3.3V±0.3V VCC(1)= 2.7V Symbol VCC(2)= 2.5V±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF (1, 2) tPHL V IH VT 0V ALVC Link DISABLE ENABLE CONTROL INPUT GND tPZL D.U.T. OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH 500 Ω RT t PLH CL ALVC Link Test Circuit for All Outputs V OH VT V OL Propagation Delay V OUT Pulse Generator t PHL OPPOSITE PHASE INPUT TRANSITION Open 500 Ω tPLH OUTPUT V LOAD V CC V IN V IH VT 0V SAME PHASE INPUT TRANSITION tPLZ V IH VT 0V V LOAD/2 V LOAD/2 VT V LZ V OL tPHZ VT V OH V HZ 0V 0V ALVC Link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Enable and Disable Times NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. V IH DATA VT INPUT 0V tSU tH V IH TIMING VT INPUT 0V tREM V IH ASYNCHRONOUS VT CONTROL 0V V IH SYNCHRONOUS VT CONTROL tSU 0V tH NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns. SWITCH POSITION Test Switch Open Drain Disable Low Enable Low VLOAD Disable High Enable High GND All Other Tests Open ALVC Link Set-up, Hold, and Release Times V IH INPUT VT 0V tPHL1 tPLH1 V OH OUTPUT 1 tSK (x) LOW-HIGH-LOW PULSE VT V OL tSK (x) tW V OH VT V OL OUTPUT 2 VT HIGH-LOW-HIGH PULSE VT ALVC Link tPLH2 tPHL2 Pulse Width tSK (x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Output Skew - tSK(X) ALVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 6 IDT74ALVCH16270 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION ALVC X IDT XX Bus-Hold Temp. Range XX Family XX XXX Device Type Package CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 PV PA PF Shrink Small Outline Package Thin Shrink Small Outline Package Thin Very Small Outline Package 270 12-Bit to 24-Bit Registered Bus Exchanger with 3-State Outputs 16 Double-Density, ±24mA H Bus-hold 74 –40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 7 for Tech Support: [email protected] (408) 654-6459