ICS843SDN FEMTOCLOCK™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR General Description Features The ICS843SDN is a Gigabit Ethernet Clock Generator and a member of the HiPerClocksTM HiPerClockS™ family of high performance devices from IDT. The ICS843SDN uses a 24MHz crystal to synthesize 120MHz. The ICS843SDN uses IDT’s 3rd generation low phase noise VCO technology, and can achieve <1ps rms phase jitter performance over the 12kHz – 20MHz integration range. The ICS843SDN is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. • • One differential 3.3V LVPECL output • • • • Output frequency range: 116MHz – 150MHz • • • • Full 3.3V supply mode ICS Crystal oscillator interface designed for 23.2MHz – 30MHz, 18pF parallel resonant crystal VCO range: 580MHz – 750MHz Output duty cycle range: 47% – 53% RMS phase jitter @ 120MHz, using a 24MHz crystal (12kHz – 20MHz): 0.81ps (typical) 0°C to 70°C ambient operating temperature Industrial temperature information available upon request Available in lead-free (RoHS 6) package Table 1. Frequency Table - Typical Applications Crystal Frequency (MHz) Output Frequency (MHz) 25 125 24 120 Block Diagram Pin Assignment 25MHz XTAL_IN OSC XTAL_OUT Phase Detector VCO Q nQ ÷5 ÷25 (fixed) IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR VCCA VEE XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VCC Q nQ nc ICS843SDN 8 Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View 1 ICS843SDNAG REV. A FEBRUARY 19, 2009 ICS843SDN FEMTOCLOCK™CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR Table 2. Pin Descriptions Number Name Type Description 1 VCCA Power Analog supply pin. 2 VEE Power Negative supply pin. 3, 4 XTAL_OUT XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 5 nc Unused No connect. 6, 7 nQ, Q Output Differential output pair. LVPECL interface levels. 8 VCC Power Core supply pin. Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC+ 0.5V Outputs, IO Continuos Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 129.5°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 3A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter VCC Core Supply Voltage VCCA Analog Supply Voltage IEE Power Supply Current IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR Test Conditions 2 Minimum Typical Maximum Units 3.135 3.3 3.465 V VCC – 0.10 3.3 VCC V 83 mA ICS843SDNAG REV. A FEBRUARY 19, 2009 ICS843SDN FEMTOCLOCK™CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR Table 3B. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter Test Conditions VOH Output High Current; NOTE 1 VOL Output Low Current; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Minimum Typical Maximum Units VCC – 1.4 VCC – 0.9 µA VCC – 2.0 VCC – 1.7 µA 0.6 1.0 V Maximum Units 30 MHz Equivalent Series Resistance (ESR) 40 Ω Shunt Capacitance 7 pF NOTE 1: Outputs termination with 50Ω to VCC – 2V. Table 4. Crystal Characteristics Parameter Test Conditions Minimum Mode of Oscillation Typical Fundamental Frequency; NOTE 1 23.2 NOTE 1:Input frequency is limited to a range of 23.2MHz – 30MHz due to VCO range. AC Electrical Characteristics Table 5. AC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Parameter Symbol fOUT Output Frequency tjit(Ø) RMS Phase Jitter, Random; NOTE 1 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical 116 120MHz, (Integration Range: 12kHz – 20MHz) 20% to 80% Maximum Units 150 MHz 0.81 ps 100 600 ps 47 53 % NOTE 1: Please refer to Phase Noise Plot. IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR 3 ICS843SDNAG REV. A FEBRUARY 19, 2009 ICS843SDN FEMTOCLOCK™CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR Typical Phase Noise at 120MHz Noise Power dBc Hz 120MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.81ps (typical) Offset Frequency (Hz) IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR 4 ICS843SDNAG REV. A FEBRUARY 19, 2009 ICS843SDN FEMTOCLOCK™CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR Parameter Measurement Information 2V 2V VCC Noise Power Phase Noise Plot SCOPE Qx VCCA Phase Noise Mask LVPECL nQx VEE f1 3.3V LVPECL Output Load AC Test Circuit f2 RMS Jitter = Area Under the Masked Phase Noise Plot - -1.3V ± 0.165V Offset Frequency RMS Phase Jitter nQ nQ 80% 80% Q VSW I N G ➤ ➤ Q 20% 20% tF tR ➤ ➤ Output Duty Cycle/Pulse Width/Period IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR Output Rise/Fall Time 5 ICS843SDNAG REV. A FEBRUARY 19, 2009 ICS843SDN FEMTOCLOCK™CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS843SDN provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VCCA pin. 3.3V VCC .01µF 10Ω .01µF 10µF VCCA Figure 1. Power Supply Filtering Crystal Input Interface The ICS843SDN has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_IN C1 27p X1 18pF Parallel Crystal XTAL_OUT C2 27p Figure 2. Crystal Input Interface IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR 6 ICS843SDNAG REV. A FEBRUARY 19, 2009 ICS843SDN FEMTOCLOCK™CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VCC impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. VCC R1 Ro 0.1µf 50Ω Rs XTAL_IN R2 Zo = Ro + Rs XTAL_OUT Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω 3.3V Zo = 50Ω 125Ω FOUT FIN 125Ω Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω Figure 4A. 3.3V LVPECL Output Termination IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR 84Ω Figure 4B. 3.3V LVPECL Output Termination 7 ICS843SDNAG REV. A FEBRUARY 19, 2009 ICS843SDN FEMTOCLOCK™CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR Schematic Example Figure 5A shows an example of the ICS843SDN application schematic. In this example, the device is operated at VCC = 3.3V. The 18pF parallel resonant crystal is used. The C1 = 27pF and C2 = 27pF are recommended for frequency accuracy. For a different board layout, the C1 and C2 values may be slightly adjusted for optimizing frequency accuracy. Two examples of LVPECL terminations are shown in this schematic. Additional approaches are shown in the LVPECL Termination Application Note. VCC VCC VCCA R1 10 C4 10uF VCC C5 0.01u U1 XTAL_OUT XTAL_IN 1 2 3 4 VCCA VEE XTAL_OUT XTAL_IN VCC Q nQ nc 3.3V C3 0.01u 8 7 6 5 Q nQ Zo = 50 Ohm R2 133 R3 133 + Zo = 50 Ohm - VCC=3.3V 25MHz R4 82.5 R5 82.5 F p 8 1 C2 27pF X1 C1 27pF Zo = 50 Ohm + Zo = 50 Ohm R6 50 Optional Y-Termination R7 50 R8 50 Figure 5A. ICS843SDN Schematic Example IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR 8 ICS843SDNAG REV. A FEBRUARY 19, 2009 ICS843SDN FEMTOCLOCK™CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR Schematic Example Figure 5B shows an example of ICS843SDN P.C. board layout. The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through-hole HC49 package. The footprints of other components in this example are listed in the Table 6 There should be at least one decoupling capacitor per power pin. The decoupling capacitors should be located as close as possible to the power pins. The layout assumes that the board has clean analog power ground plane. Table 6. Footprint Table Reference Size C1, C2 0402 C3 0805 C4, C5 0603 R2 0603 NOTE: Table 6 lists component sizes shown in this layout example. Figure 5B. ICS843SDN PC Board Layout Example IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR 9 ICS843SDNAG REV. A FEBRUARY 19, 2009 ICS843SDN FEMTOCLOCK™CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR Power Considerations This section provides information on power dissipation and junction temperature for the ICS843SDN. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843SDN is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 83mA = 287.60mW • Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.3V, with all outputs switching) = 287.60mW + 30mW = 317.60mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 129.5°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.318W * 129.5°C/W = 111.2°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7. Thermal Resistance θJA for 8 Lead TSSOP, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR 0 1 2.5 129.5°C/W 125.5°C/W 123.5°C/W 10 ICS843SDNAG REV. A FEBRUARY 19, 2009 ICS843SDN FEMTOCLOCK™CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCC Q1 VOUT RL 50Ω VCC - 2V Figure 6. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCC – 2V. • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V (VCC_MAX – VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V (VCC_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) = [(2V – 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) = [(2V – 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR 11 ICS843SDNAG REV. A FEBRUARY 19, 2009 ICS843SDN FEMTOCLOCK™CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR Reliability Information Table 8. θJA vs. Air Flow Table for a 8 Lead TSSOP θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 129.5°C/W 125.5°C/W 123.5°C/W Transistor Count The transistor count for ICS843SDN is: 2395 Package Outline and Package Dimensions Package Outline - G Suffix for 8 Lead TSSOP Table 9. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 α 0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR 12 ICS843SDNAG REV. A FEBRUARY 19, 2009 ICS843SDN FEMTOCLOCK™CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR Ordering Information Table 10. Ordering Information Part/Order Number 843SDNAGLF 843SDNAGLFT Marking SDNAL SDNAL Package “Lead-Free” 8 Lead TSSOP “Lead-Free” 8 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Temperature 0°C to 70°C 0°C to 70°C NOTE: Parts that are ordered with an LF suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR 13 ICS843SDNAG REV. A FEBRUARY 19, 2009 ICS843SDN FEMTOCLOCK™CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR Contact Information: www.IDT.com www.IDT.com Sales Technical Support 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT [email protected] +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA