SiC521, SiC521A www.vishay.com Vishay Siliconix 30 A VRPower® Integrated Power Stage DESCRIPTION FEATURES The SiC521 and SiC521A are integrated power stage solutions optimized for synchronous buck applications to offer high current, high efficiency, and high power density performance. Packaged in Vishay’s proprietary 4.5 mm x 3.5 mm MLP package, SiC521 and SiC521A enable voltage regulator designs to deliver up to 30 A continuous current per phase. • Thermally enhanced PowerPAK® MLP4535-22L package • Vishay’s Gen IV MOSFET technology and a low-side MOSFET with integrated Schottky diode • Delivers up to 30 A continuous current, 40 A at 10 ms peak current • 95 % peak efficiency • High frequency operation up to 1.5 MHz • Power MOSFETs optimized for 12 V input stage • 3.3 V (SiC521A) / 5 V (SiC521) PWM logic with tri-state and hold-off • Zero current detect control for light load efficiency improvement The internal power MOSFETs utilize Vishay’s state-of-the-art Gen IV TrenchFET technology that delivers industry benchmark performance to significantly reduce switching and conduction losses. The SiC521 and SiC521A incorporate an advanced MOSFET gate driver IC that features high current driving capability, adaptive dead-time control, an integrated bootstrap Schottky diode, and zero current detect to improve light load efficiency. The drivers are also compatible with a wide range of PWM controllers, support tri-state PWM, and 3.3 V (SiC521A) / 5 V (SiC521) PWM logic. • Low PWM propagation delay (< 20 ns) • Under voltage lockout for VCIN • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 APPLICATIONS • Multi-phase VRDs for CPU, GPU, and memory • Synchronous buck converters • DC/DC VR modules TYPICAL APPLICATION DIAGRAM 5V VIN V IN VDRV BOOT PHASE VCIN ZCD_EN# PWM controller PWM VSWH VOUT Gate driver PGND GL C GND Fig. 1 - SiC521 and SiC521A Typical Application Diagram S15-0170-Rev. B, 09-Feb-15 Document Number: 62989 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC521, SiC521A www.vishay.com Vishay Siliconix PGND PGND PGND VIN VIN VIN PINOUT CONFIGURATION 11 10 9 8 7 6 25 VIN VSWH 12 26 PGND VSWH 13 VSWH 14 23 CGND VSWH 15 24 GL 17 18 19 20 21 22 PGND PGND GL PGND VDRV PWM VSWH 16 5 PHASE 4 BOOT 3 CGND 2 VCIN 1 ZCD_EN# Fig. 2 - SiC521 and SiC521A Pin Configuration PIN DESCRIPTION PIN NUMBER NAME FUNCTION 1 ZCD_EN# 2 VCIN Supply voltage for internal logic circuitry 3, 23 CGND Analog ground for the driver IC 4 BOOT High-side driver bootstrap voltage 5 PHASE Return path of high-side gate driver 6 to 8, 25 VIN ZCD control. Active low Power stage input voltage. Drain of high-side MOSFET 9 to 11, 17, 18, 20, 26 PGND Power ground 12 to 16 VSWH Switch node of the power stage 19, 24 GL 21 VDRV Supply voltage for internal gate driver Low-side gate signal 22 PWM PWM control input ORDERING INFORMATION PART NUMBER SiC521CD-T1-GE3 SiC521ACD-T1-GE3 SiC521ADB and SiC521DB S15-0170-Rev. B, 09-Feb-15 PACKAGE PowerPAK® MLP4535-22L MARKING CODE SiC521 5 V PWM optimized SiC521A 3.3 V PWM optimized Reference board Document Number: 62989 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC521, SiC521A www.vishay.com Vishay Siliconix ABSOLUTE MAXIMUM RATINGS ELECTRICAL PARAMETER CONDITIONS LIMIT VIN -0.3 to +25 Control Logic Supply Voltage VCIN -0.3 to +7 Drive Supply Voltage VDRV Input Voltage Switch Node (DC voltage) -0.3 to +7 -0.3 to +25 VSWH Switch Node (AC voltage) (1) BOOT Voltage (DC voltage) -8 to +30 BOOT to PHASE (DC voltage) 38 -0.3 to +7 VBOOT- PHASE BOOT to PHASE (AC voltage) (3) -0.3 to +8 All Logic Inputs and Outputs (PWM and ZCD_EN#) -0.3 to VCIN + 0.3 fS = 300 kHz, VIN = 12 V, VOUT = 1.8 V 30 fS = 1 MHz, VIN = 12 V, VOUT = 1.8 V 25 TJ 150 Ambient Temperature TA -40 to +125 Storage Temperature Tstg -65 to +150 Human body model, JESD22-A114 3000 Charged device model, JESD22-C101 1000 Output Current, IOUT(AV) (4) Max. Operating Junction Temperature Electrostatic Discharge Protection V 32 VBOOT BOOT Voltage (AC voltage) (2) UNIT A °C V Note (1) The specification values indicated “AC” is V SWH to PGND, -8 V (< 20 ns, 10 μJ), min. and 30 V (< 50 ns), max. (2) The specification value indicates “AC voltage” is V BOOT to PGND, 36 V (< 50 ns) max. (3) The specification value indicates “AC voltage” is V BOOT to VPHASE, 8 V (< 20 ns) max. (4) Output current rated with testing evaluation board at T = 25 °C with natural convection cooling. The rating is limited by the peak evaluation A board temperature, TJ = 150 °C, and varies depending on the operating conditions and PCB layout. This rating may be changed with different application settings. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE ELECTRICAL PARAMETER Input Voltage (VIN) MINIMUM TYPICAL MAXIMUM 4.5 - 18 Drive Supply Voltage (VDRV) 4.5 5 5.5 Control Logic Supply Voltage (VCIN) 4.5 5 5.5 BOOT to PHASE (VBOOT-PHASE, DC voltage) 4 4.5 5.5 Thermal Resistance from Junction to PCB - 5 - Thermal Resistance from Junction to Case - 2.5 - S15-0170-Rev. B, 09-Feb-15 UNIT V °C/W Document Number: 62989 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC521, SiC521A www.vishay.com Vishay Siliconix ELECTRICAL SPECIFICATIONS (ZCD_EN# = 5 V, VIN = 12 V, VDRV and VCIN = 5 V, TA = 25 °C) PARAMETER SYMBOL TEST CONDITION LIMITS UNIT MIN. TYP. MAX. no switching, VPWM = FLOAT fS = 300 kHz, D = 0.1 fS = 300 kHz, D = 0.1 fS = 1 MHz, D = 0.1 no switching, VPWM = FLOAT - 300 300 8 30 50 15 - IF = 2 mA - - 0.4 V VPWM = FLOAT 3.4 0.72 0.9 3.1 3.7 0.9 2.3 1.15 3.35 4.0 1.1 1.38 3.6 V VHYS_TRI_R - 225 - VHYS_TRI_F - 325 - VPWM = 5 V VPWM = 0 V - - 350 -350 μA VPWM = FLOAT 2.2 0.72 0.9 1.95 2.45 0.9 1.8 1.15 2.2 2.7 1.1 1.38 2.45 V VHYS_TRI_R - 225 - VHYS_TRI_F - 275 - - - 225 -225 tPD_TRI_R - 20 - tTSHO tPD_OFF_GH - 150 20 - - 10 - tPD_OFF_GL - 20 - tPD_ON_GL - 10 - tPWM_ON_MIN 30 - - POWER SUPPLY Control Logic Supply Current IVCIN Drive Supply Current IVDRV BOOTSTRAP SUPPLY Bootstrap Diode Forward Voltage PWM CONTROL INPUT (SiC521) Rising Threshold Falling Threshold Tri-state Voltage Tri-state Rising Threshold Tri-state Falling Threshold Tri-state Rising Threshold Hysteresis Tri-state Falling Threshold Hysteresis PWM Input Current PWM CONTROL INPUT (SiC521A) Rising Threshold Falling Threshold Tri-state Voltage Tri-state Rising Threshold Tri-state Falling Threshold Tri-state Rising Threshold Hysteresis Tri-state Falling Threshold Hysteresis PWM Input Current TIMING SPECIFICATIONS Tri-State to GH/GL Rising Propagation Delay Tri-state Hold-Off Time GH - Turn Off Propagation Delay GH - Turn On Propagation Delay (Dead time rising) GL - Turn Off Propagation Delay GL - Turn On Propagation Delay (Dead time falling) PWM Minimum On-Time ZCD_EN# INPUT ZCD_EN# Logic Input Voltage VF VTH_PWM_R VTH_PWM_F VTRI VTRI_TH_R VTRI_TH_F μA mA μA mV IPWM VTH_PWM_R VTH_PWM_F VTRI VTRI_TH_R VTRI_TH_F mV IPWM tPD_ON_GH VPWM = 3.3 V VPWM = 0 V No load, see fig. 4 VIH_ZCD_EN# VIL_ZCD_EN# Input logic high Input logic low 2 - - 0.8 VUVLO VCIN rising, on threshold VCIN falling, off threshold 2.7 - 3.7 3.1 575 4.1 - μA ns V PROTECTION Under Voltage Lockout Under Voltage Lockout Hysteresis VUVLO_HYST V mV Notes (1) Typical limits are established by characterization and are not production tested. (2) Guaranteed by design. S15-0170-Rev. B, 09-Feb-15 Document Number: 62989 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC521, SiC521A www.vishay.com Vishay Siliconix DETAILED OPERATIONAL DESCRIPTION PWM Input with Tri-state Function Ground Connections (CGND and PGND) The PWM input receives the PWM control signal from the VR controller IC. The PWM input is designed to be compatible with standard controllers using two state logic (H and L) and advanced controllers that incorporate tri-state logic (H, L and tri-state) on the PWM output. For two state logic, the PWM input operates as follows. When PWM is driven above VPWM_TH_R the low-side is turned OFF and the high-side is turned ON. When PWM input is driven below VPWM_TH_F the high-side is turned OFF and the low-side is turned ON. For tri-state logic, the PWM input operates as previously stated for driving the MOSFETs when PWM is logic high and logic low. However, there is a third state that is entered as the PWM output of tri-state compatible controller enters its high impedance state during shut-down. The high impedance state of the controller’s PWM output allows the SiC521 and SiC521A to pull the PWM input into the tri-state region (see definition of PWM logic and Tri-State, fig. 4). If the PWM input stays in this region for the Tri-state Hold-Off Period, tTSHO, both high-side and low-side MOSFETs are turned OFF. The function allows the VR phase to be disabled without negative output voltage swing caused by inductor ringing and saves a Schottky diode clamp. The PWM and tri-state regions are separated by hysteresis to prevent false triggering. The SiC521A incorporates PWM voltage thresholds that are compatible with 3.3 V logic and the SiC521 thresholds are compatible with 5 V logic. PGND (power ground) should be externally connected to CGND (control signal ground). The layout of the printed circuit board should be such that the inductance separating CGND and PGND is minimized. Transient differences due to inductance effects between these two pins should not exceed 0.5 V. Diode Emulation Mode (ZCD_EN#) When ZCD_EN# pin is logic low and PWM signal switches low, GL is forced ON (after normal BBM time). During this time, it is under control of the ZCD (zero crossing detect) comparator. If, after the internal blanking delay, the inductor current becomes zero, the low-side is turned OFF. This improves light load efficiency by avoiding discharge of output capacitors. If PWM enters tri-state, then device will go into normal tri-state mode after tri-state delay. The GL output will be turned OFF regardless of Inductor current, this is an alternative method of improving light load efficiency by reducing switching losses. Voltage Input (VIN) This is the power input to the drain of the high-side power MOSFET. This pin is connected to the high power intermediate BUS rail. Switch Node (VSWH and PHASE) Control and Drive Supply Voltage Input (VDRV, VCIN) VCIN is the bias supply for the gate drive control IC. VDRV is the bias supply for the gate drivers. It is recommended to separate these pins through a resistor. This creates a low pass filtering effect to avoid coupling of high frequency gate drive noise into the IC. Bootstrap Circuit (BOOT) The internal bootstrap diode and an external bootstrap capacitor form a charge pump that supplies voltage to the BOOT pin. An integrated bootstrap diode is incorporated so that only an external capacitor is necessary to complete the bootstrap circuit. Connect a boot strap capacitor with one leg tied to BOOT pin and the other tied to PHASE pin. Shoot-Through Protection and Adaptive Dead Time The SiC521 and SiC521A have an internal adaptive logic to avoid shoot through and optimize dead time. The shoot through protection ensures that both high-side and low-side MOSFETs are not turned ON at the same time. The adaptive dead time control operates as follows. The high-side and low-side gate voltages are monitored to prevent the MOSFET turning ON from tuning ON until the other MOSFET's gate voltage is sufficiently low (< 1 V). Built in delays also ensure that one power MOSFET is completely OFF, before the other can be turned ON. This feature helps to adjust dead time as gate transitions change with respect to output current and temperature. Under Voltage Lockout (UVLO) During the start up cycle, the UVLO disables the gate drive, holding high-side and low-side MOSFET gates low, until the supply voltage rail has reached a point at which the logic circuitry can be safely activated. The SiC521 and SiC521A also incorporate logic to clamp the gate drive signals to zero when the UVLO falling edge triggers the shutdown of the device. As an added precaution, a 20 kΩ resistor is connected between GH and PHASE to provide a discharge path for the HS MOSFET. The switch node, VSWH, is the circuit power stage output. This is the output applied to the power inductor and output filter to deliver the output for the buck converter. The PHASE pin is internally connected to the switch node, VSWH. This pin is to be used exclusively as the return pin for the BOOT capacitor. A 20 kΩ resistor is connected between GH and PHASE to provide a discharge path for the HS MOSFET in the event that VCIN goes to zero while VIN is still applied. S15-0170-Rev. B, 09-Feb-15 Document Number: 62989 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC521, SiC521A www.vishay.com Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM V IN BOOT VDRV UVLO VCIN VCIN 20K Anti-cross conduction control logic PWM logic control & state machine PWM GL PHASE Vref = 1 V VSWH Vref = 1 V VDRV C GND SW PGND PGND ZCD_EN# Fig. 3 - SiC521 and SiC521A Functional Block Diagram DEVICE TRUTH TABLE ZCD_EN# PWM GH GL L L L H, IL > 0A L, IL < 0A L H H L L Tri-state L L H L L H H H H L H Tri-state L L PWM TIMING DIAGRAM VTH_PWM_R VTH_TRI_F VTH_TRI_R VTH_PWM_F PWM t PD_OFF_GL t TSHO GL t PD_ON_GL t PD_TRI_R t TSHO t PD_ON_GH t PD_OFF_GH t PD_TRI_R GH Fig. 4 - Definition of PWM Logic and Tri-State S15-0170-Rev. B, 09-Feb-15 Document Number: 62989 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC521, SiC521A www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS Test condition: VIN = 12 V, VDRV = VCIN = 5 V, ZCD_EN# = 5 V, VOUT = 1 V, LOUT = 360 nH, (DCR = 0.32 mΩ), TA = 25 °C (All power loss and normalized power loss curves show SiC521 and SiC521A losses only unless otherwise stated) 12.0 94 300 kHz 10.5 90 500 kHz 9.0 Power Loss, PL (W) Efficiency (%) 86 1 MHz 82 800 kHz 78 74 800 kHz 7.5 1 MHz 6.0 4.5 3.0 70 Complete converter efficiency PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)] POUT = VOUT x IOUT, measured at output capacitor 66 500 kHz 1.5 300 kHz 0.0 62 0 5 10 15 20 Output Current, IOUT (A) 25 0 30 3 6 9 12 15 18 21 Output Current, IOUT (A) 24 27 30 Fig. 8 - Power Loss vs. Output Current Fig. 5 - Efficiency vs. Output Current 40 94 VOUT = 1 V 35 VOUT = 1.2 V 90 Efficiency (%) Output Current, IOUT (A) 300 kHz 86 VOUT = 0.6 V 82 VOUT = 0.8 V 78 74 70 30 25 1 MHz 20 15 10 fS = 500 kHz 5 66 0 62 0 5 10 15 20 Output Current, IOUT (A) 25 0 30 4.0 0.35 BOOT Diode Forward Voltage, VF (V) Control Logic Supply Voltage, VCIN (V) 0.40 VUVLO_RISING 3.6 3.4 3.2 VUVLO_FALLING 2.8 2.6 -60 -40 -20 0 20 40 60 80 45 60 75 90 105 120 135 150 Fig. 9 - Safe Operating Area 4.2 3.0 30 PCB Temperature, TPCB (°C) Fig. 6 - Efficiency vs. Output Current 3.8 15 100 120 140 IF = 2 mA 0.30 0.25 0.20 0.15 0.10 0.05 0.00 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) Temperature (°C) Fig. 7 - UVLO Threshold vs. Temperature Fig. 10 - BOOT Diode Forward Voltage vs. Temperature S15-0170-Rev. B, 09-Feb-15 Document Number: 62989 7 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC521, SiC521A www.vishay.com Vishay Siliconix 3.2 3.4 PWM Threshold Voltage, VPWM (V) PWM Threshold Voltage, VPWM (V) 3.0 VTH_PWM_R 2.6 2.2 VTRI_TH_F 1.8 VTRI 1.4 VTRI_TH_R 1.0 VTH_PWM_F 0.6 2.8 VTH_PWM_R 2.4 VTRI_TH_F 2.0 VTRI 1.6 VTRI_TH_R 1.2 0.8 VTH_PWM_F 0.4 0.0 0.2 -60 -40 -20 0 20 40 60 80 4.5 100 120 140 4.6 Temperature (°C) Fig. 11 - PWM Threshold vs. Temperature (SiC521A) 4.9 5.0 5.1 5.2 5.3 5.4 5.5 4.8 VTH_PWM_R 4.2 VTH_PWM_R 3.6 VTRI_TH_F 3.0 2.4 VTRI 1.8 VTRI_TH_R 1.2 0.6 PWM Threshold Voltage, VPWM (V) 4.2 PWM Threshold Voltage, VPWM (V) 4.8 Fig. 14 - PWM Threshold vs. Driver Supply Voltage (SiC521A) 4.8 3.6 VTRI_TH_F 3.0 2.4 VTRI 1.8 VTRI_TH_R 1.2 0.6 VTH_PWM_F VTH_PWM_F 0.0 0.0 -60 -40 -20 0 20 40 60 80 4.5 100 120 140 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 Temperature (°C) Control Logic Supply Voltage, VCIN (V) Fig. 12 - PWM Threshold vs. Temperature (SiC521) Fig. 15 - PWM Threshold vs. Driver Supply Voltage (SiC521) 2.2 2.2 ZCD_EN# Threshold Voltage, VZCD_EN# (V) ZCD_EN# Threshold Voltage, VZCD_EN# (V) 4.7 Control Logic Supply Voltage, VCIN (V) 2.0 1.8 VIH_ZCD_EN# 1.6 1.4 1.2 1.0 VIL_ZCD_EN# 0.8 0.6 2.0 1.8 VIH_ZCD_EN# 1.6 1.4 VIL_ZCD_EN# 1.2 1.0 0.8 0.6 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) Fig. 13 - ZCD_EN# Threshold vs. Temperature S15-0170-Rev. B, 09-Feb-15 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 Control Logic Supply Voltage, VCIN (V) Fig. 16 - ZCD_EN# Threshold vs. Driver Supply Voltage Document Number: 62989 8 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC521, SiC521A www.vishay.com Vishay Siliconix 430 -9.5 VZCD_EN# = 0 V -10.0 -10.5 -11.0 -11.5 -12.0 -12.5 -13.0 -60 -40 -20 Driver Supply Current, IVDVR & IVCIN (V) ZCD_EN# Pull-Up Current, IZCD_EN# (uA) -9.0 410 VPWM = FLOAT 390 370 350 330 310 290 270 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) Temperature (°C) Fig. 17 - ZCD_EN# Pull-Up Current vs. Temperature Fig. 18 - Driver Quiescent Current vs. Temperature PCB LAYOUT RECOMMENDATIONS Step 1: VIN / PGND Planes and Decoupling Step 2: VSWH Plane VIN Plane VSWH VIN PGND VSWH Snubber PGND Plane PGND Plane 1. Layout VIN and PGND planes as shown above. 2. Ceramic capacitors should be placed directly between VIN and PGND, and very close to the device for best decoupling effect. 3. Different values / packages of ceramic capacitors should be used to cover entire decoupling spectrum e.g. 1210, 0805, 0603, 0402. 4. Smaller capacitance values, placed closer to the devices, VIN pin(s), results in better high frequency noise absorbing. S15-0170-Rev. B, 09-Feb-15 1. Connect output inductor to IC with large plane to lower resistance. 2. VSWH plane also serves as a heat-sink for low-side MOSFET. Make the plane wide and short to achieve the best thermal path. 3. If any snubber network is required, place the components as shown above and the network can be placed at bottom. Document Number: 62989 9 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC521, SiC521A www.vishay.com Vishay Siliconix Step 3: VCIN / VDRV Input Filter Step 5: Signal Routing Cvdrv AGND AGND Cvcin AGND PGND PGND 1. The VCIN / VDRV input filter ceramic cap should be placed as close as possible to the IC. It is recommended to connect two capacitors separately. 2. VCIN capacitor should be placed between pin 2 and pin 3 (AGND of driver IC) to achieve best noise filtering. 3. VDRV capacitor should be placed between pin 20 (PGND of driver IC) and pin 21 to provide maximum instantaneous driver current for low side MOSFET during switching cycle. 4. For connecting VCIN to AGND, it is recommended to use a large plane to reduce parasitic inductance. Step 4: BOOT Resistor and Capacitor Placement 1. Route the PWM and ZCD_EN# signal traces out of the top left corner next to pin 1. 2. The PWM signal is an important signal, both signal and return traces should not cross any power nodes on any layer. 3. It is best to “shield” these traces from power switching nodes, e.g. VSWH, with a GND island to improve signal integrity. 4. GL (pin 19) has been connected with GL pad (pin 24) internally. Step 6: Adding Thermal Relief Vias VSWH AGND PGND Cboot VIN PGND Plane Rboot VIN Plane 1. The components need to be placed as close as possible to IC, directly between PHASE (pin 5) and BOOT (pin 4). 2. To reduce parasitic inductance, chip size 0402 can be used. 1. Thermal relief vias can be added on the VIN and AGND pads to utilize inner layers for high-current and thermal dissipation. 2. To achieve better thermal performance, additional vias can be placed on VIN plane and PGND plane. 3. VSWH pad is a noise source, it is not recommended to place vias on this pad. 4. 8 mil vias for pads and 10 mils vias for planes are the optimal via sizes. Vias on pad may drain solder during assembly and cause assembly issues. Consult with the assembly house for guidelines. S15-0170-Rev. B, 09-Feb-15 Document Number: 62989 10 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC521, SiC521A www.vishay.com Vishay Siliconix Step 7: Ground Connection AGND VSWH PGND 1. It is recommended to make a single connection between AGND and PGND which can be made on the top layer. 2. It is recommended to make the entire first inner layer (below top layer) the ground plane and separate them into AGND and PGND planes. 3. These ground planes provide shielding between noise sources on top layer and signal traces on bottom layer. RECOMMENDED LAND PATTERN POWERPAK® MLP4535-22L 0.29 1.2 0.4 0.3 0.25 1.16 4 0.8 0.3 16 0.14 15 14 1.61 13 12 S15-0170-Rev. B, 09-Feb-15 8 9 1 10 0.5 x 2 =1 11 0.75 21 20 19 18 17 1 16 2 15 3 14 4 13 5 12 6 7 8 9 10 11 3 7 0.5 x 2 =1 0. 6 0.75 0.1 0.37 0.3 0.3 0.59 0.75 5 22 0.31 2.05 0.37 3 0.3 17 0.45 0.9 3.5 0.5 x 4 = 2 3.05 0.29 0.21 0.29 0.36 18 0.55 0.5 0.3 0.75 0.74 21 20 19 1 2 0.5 0.75 0.75 0.45 22 1 0.75 0.3 0.3 0.5 x 4 = 2 4.5 0.75 0.5 x 3 = 1.5 All dimensions in millimeters Document Number: 62989 11 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC521, SiC521A www.vishay.com Vishay Siliconix PACKAGE OUTLINE DRAWING MLP4535-22L 2x 0.1 C A D A 5 6 Pin 1 dot by marking A 0.08 C K1 D1-2 D1-1 A1 22 21 20 19 A2 18 17 D2-1 K4 D2-4 17 18 19 20 21 22 2x 12 E 3 K2 4 5 b 12 B 6 7 8 9 11 10 9 10 11 C DIM. A (8) A1 b 7 D2-2 L INCHES NOM. MAX. MIN. NOM. 0.70 0.75 0.80 0.027 0.0029 0.031 0.00 - 0.05 0.000 - 0.002 0.20 ref. 0.20 0.25 0.30 0.0078 0.0098 4.50 BSC 0.177 BSC e 0.50 BSC 0.019 BSC E 3.50 BSC 0.35 0.40 MAX. 0.008 ref. D L 6 MIN. A2 (4) 8 D2-3 MILLIMETERS E1-2 5 14 13 E2-2 13 2 e 14 4 K3 E2-3 E1-1 3 1 E1-5 15 E1-3 E2-4 16 15 E1-4 16 2 E2-1 0.1 C B 1 0.0110 0.137 BSC 0.45 0.013 0.015 N (3) 22 22 Nd (3) 6 6 Ne (3) 5 5 0.017 D1-1 0.35 0.40 0.45 0.013 0.015 0.017 D1-2 0.15 0.20 0.25 0.005 0.007 0.009 D2-1 1.02 1.07 1.12 0.040 0.042 0.044 D2-2 1.02 1.07 1.12 0.040 0.042 0.044 D2-3 1.47 1.52 1.57 0.057 0.059 0.061 D2-4 0.25 0.30 0.35 0.009 0.011 0.013 E1-1 1.095 1.145 1.195 0.043 0.045 0.047 E1-2 2.67 2.72 2.77 0.105 0.107 0.109 E1-3 0.35 0.40 0.45 0.013 0.015 0.017 E1-4 1.85 1.90 1.95 0.072 0.074 0.076 E1-5 0.095 0.145 0.195 0.0037 0.0057 0.0076 E2-1 3.05 3.10 3.15 0.120 0.122 0.124 E2-2 1.065 1.115 1.165 0.0419 0.0438 0.0458 E2-3 0.695 0.745 0.795 0.027 0.029 0.031 E2-4 0.40 0.45 0.50 0.015 0.017 0.019 K1 0.40 BSC 0.015 BSC K2 0.07 BSC 0.002 BSC K3 0.05 BSC 0.001 BSC K4 0.40 BSC 0.015 BSC Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?62989. S15-0170-Rev. B, 09-Feb-15 Document Number: 62989 12 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix MLP 4.5 x 3.5-22L BWL Case Outline 2x D A 5 6 Pin 1 dot by marking A 0.08 C K1 0.1 C A D1-2 D1-1 A1 22 21 20 19 A2 18 17 D2-1 K4 D2-4 17 18 19 20 21 22 2x 12 E2-2 2 3 e K2 4 5 B 6 7 8 9 11 10 9 10 11 C DIM. 8 D2-3 MILLIMETERS E1-2 13 12 K3 E2-3 E1-1 13 5 b 4 E1-5 15 14 E1-3 E2-4 14 E2-1 15 3 E 2 1 16 16 E1-4 0.1 C B 1 7 D2-2 6 L INCHES MIN. NOM. MAX. MIN. NOM. A (8) 0.70 0.75 0.80 0.027 0.0029 0.031 A1 0.00 - 0.05 0.000 - 0.002 0.30 0.0078 A2 b (4) 0.20 ref. 0.20 0.25 0.008 ref. 0.0098 D 4.50 BSC 0.177 BSC e 0.50 BSC 0.019 BSC E L 3.50 BSC 0.35 0.40 MAX. 0.0110 0.137 BSC 0.45 0.013 0.015 N (3) 22 22 Nd (3) 6 6 Ne (3) 5 5 0.017 D1-1 0.35 0.40 0.45 0.013 0.015 0.017 D1-2 0.15 0.20 0.25 0.005 0.007 0.009 D2-1 1.02 1.07 1.12 0.040 0.042 0.044 D2-2 1.02 1.07 1.12 0.040 0.042 0.044 D2-3 1.47 1.52 1.57 0.057 0.059 0.061 D2-4 0.25 0.30 0.35 0.009 0.011 0.013 E1-1 1.095 1.145 1.195 0.043 0.045 0.047 E1-2 2.67 2.72 2.77 0.105 0.107 0.109 E1-3 0.35 0.40 0.45 0.013 0.015 0.017 E1-4 1.85 1.90 1.95 0.072 0.074 0.076 E1-5 0.095 0.145 0.195 0.0037 0.0057 0.0076 E2-1 3.05 3.10 3.15 0.120 0.122 0.124 E2-2 1.065 1.115 1.165 0.0419 0.0438 0.0458 E2-3 0.695 0.745 0.795 0.027 0.029 0.031 E2-4 0.40 0.45 0.50 0.015 0.017 0.019 K1 0.40 BSC 0.015 BSC K2 0.07 BSC 0.002 BSC K3 0.05 BSC 0.001 BSC K4 0.40 BSC 0.015 BSC Document Number: 67234 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Revision: 20-Oct-14 Package Information www.vishay.com Vishay Siliconix Notes 1. Use millimeters as the primary measurement 2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994 3. N is the number of terminals, Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction. 4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip 5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body 6. Exact shape and size of this feature is optional 7. Package warpage max. 0.08 mm 8. Applied only for terminals T14-0626-Rev. A, 20-Oct-14 DWG: 6028 Document Number: 67234 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Revision: 20-Oct-14 PAD Pattern www.vishay.com Vishay Siliconix Recommended Land Pattern PowerPAK® MLP4535-22L Land pattern 0.74 0.3 0.75 1.2 2 0.29 0.25 1.16 4 0.31 0.8 0.3 16 0.14 15 14 1.61 13 2.05 0.37 3 5 12 22 10 11 21 20 19 18 16 2 15 3 14 4 13 5 12 Revision: 05-Nov-14 7 8 9 10 0.75 7 8 0.5 x 2 =1 9 1 10 0.5 x 2 =1 11 0.75 17 1 6 6 3 9 (D2-3) 1.52 0. 8 0.1 7 (D2-2) 1.07 0.37 0.3 0.3 6 (L) 0.4 0.59 0.75 12 0.4 0.3 0.3 17 0.45 0.9 13 3.5 14 0.36 18 0.75 0.75 0.3 (E2-3) 0.75 (e) 0.5 5 15 0.5 21 20 19 1 0.5 x 4 = 2 3.05 0.29 0.21 (K2) 0.07 16 (b) 0.25 (E2-1) 3.1 3.5 (D1-5) 0.14 3 4 (E1-1) 1.15 (K3) 0.05 (E1-4) 1.9 (E1-2) 2.72 (E2-2) 1.11 1 2 0.45 22 18 17 (E2-4) 0.45 21 20 19 (E1-3) 0.4 22 1 0.5 x 4 = 2 4.5 0.75 0.5 x 3 = 1.5 0.3 0.55 0.5 (D1-2) 0.2 (D1-1) 0.4 0.29 4.5 (K4) (D2-4) 0.3 0.4 (D2-1) (K1) 1.07 0.4 0.75 Package outline top view, transparent (not bottom view) All dimensions in millimeters 11 Document Number: 66914 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. 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