INTERSIL CA3079

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Oct 1999
CA3059, CA3079
Zero-Voltage Switches for 50Hz-60Hz and
400Hz Thyristor Control Applications
Features
Description
• Relay Control
The CA3059 and CA3079 zero-voltage switches are monolithic silicon integrated circuits designed to control a thyristor
in a variety of AC power switching applications for AC input
voltages of 24V, 120V, 208/230V, and 277V at 50Hz-60Hz
and 400Hz. Each of the zero-voltage switches incorporates
4 functional blocks (see the Functional Block Diagram) as
follows:
• Valve Control
• Synchronous Switching of Flashing Lights
• On-Off Motor Switching
• Differential Comparator with Self-Contained Power
Supply for Industrial Applications
• Photosensitive Control
1. Limiter-Power Supply - Permits operation directly from an
AC line.
• Power One-Shot Control
• Heater Control
2. Differential On/Off Sensing Amplifier - Tests the condition
of external sensors or command signals. Hysteresis or
proportional-control capability may easily be implemented in this section.
• Lamp Control
Type Features
CA3059 CA3079
• 24V, 120V, 208/230V, 277V at 50/60 . . .
or 400Hz Operation
X
X
• Differential Input . . . . . . . . . . . . . . . . . .
X
X
• Low Balance Input Current (Max) - µA. . .
1
2
• Built-In Protection Circuit for . . . . . . . .
Opened or Shorted Sensor (Term 14)
X
X
3. Zero-Crossing Detector - Synchronizes the output pulses
of the circuit at the time when the AC cycle is at zero voltage point; thereby eliminating radio-frequency interference (RFI) when used with resistive loads.
4. Triac Gating Circuit - Provides high-current pulses to the
gate of the power controlling thyristor.
• Sensor Range (Rx) - kΩ. . . . . . . . . . . . . 2 - 100 2 - 50
• DC Mode (Term 12) . . . . . . . . . . . . . . . .
X
• External Trigger (Term 6) . . . . . . . . . . .
X
• External Inhibit (Term 1) . . . . . . . . . . . .
X
• DC Supply Volts (Max) . . . . . . . . . . . . .
oC) .
• Operating Temperature Range (
..
14
In addition, the CA3059 provides the following important
auxiliary functions (see the Functional Block Diagram).
1. A built-in protection circuit that may be actuated to remove
drive from the triac if the sensor opens or shorts.
10
2. Thyristor firing may be inhibited through the action of an
internal diode gate connected to Terminal 1.
-55 to +125
3. High-power dc comparator operation is provided by overriding the action of the zero-crossing detector. This is accomplished by connecting Terminal 12 to Terminal 7.
Gate current to the thyristor is continuous when Terminal
13 is positive with respect to Terminal 9.
Ordering Information
PART NUMBER
TEMPERATURE
-55oC
CA3059
o
CA3079
to
+125oC
o
-55 C to +125 C
PACKAGE
14 Lead Plastic DIP
The CA3059 and CA3079 are supplied in 14 lead dual-inline plastic packages.
14 Lead Plastic DIP
Pinouts
CA3059 (PDIP)
TOP VIEW
INHIBIT 1
DC SUPPLY 2
HIGH CURRENT 3
NEG. TRIGGER
TRIGGER OUT 4
AC IN 5
TRIGGER IN 6
COMMON 7
CA3079 (PDIP)
TOP VIEW
14 FAIL-SAFE
DO NOT USE 1
13 SENSE AMP IN
DC SUPPLY 2
12 ZCD OVERRIDE
11 R DRIVER (COM)
10 R DRIVER
V+
9 SENSE AMP REF
12 DO NOT USE
AC IN 5
10 R DRIVER V+
COMMON 7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
3
13 SENSE AMP IN
HIGH CURRENT 3
NEG. TRIGGER
TRIGGER OUT 4
DO NOT USE 6
8 COMMON
14 DO NOT USE
11 R DRIVER (COM)
9 SENSE AMP REF
8 COMMON
FN490.5
CA3059, CA3079
Functional Block Diagram
12 IC
RS
5
IC
2
AC INPUT
VOLTAGE
RL
POWER
SUPPLY
LIMITER
CURRENT
BOOST
3
“0”
CROSSING
DET.
EXTERNAL
INHIBIT
TRIAC
GATING
CIRCUIT
1
PROTECTION
CIRCUIT
RP 14
G
MT1
INHIBIT
13
+
-
100µF
15V
4
MT2
ON/OFF
SENSING
AMPL.
RX 8
7
* NTC SENSOR
9
10
11
6 IC
* NEGATIVE TEMPERATURE COEFFICIENT
AC INPUT VOLTAGE (50/60 OR 400Hz)
V AC
INPUT SERIES RESISTOR (RS)
kΩ
DISSIPATION RATING FOR RS
W
24
2
0.5
120
10
2
208/230
20
4
277
25
5
NOTE: Circuitry within shaded areas, not included in CA3079
See chart
IC = Internal connection - DO NOT USE (Terminal restriction applies only to CA3079)
IC
RS
AC
LINE
INPUT
12
FOR DC MODE
OR 400Hz
OPERATION
R1
5K
5
D7
D2
D13
D3
D4
D5
2
R2
27K
D6
RSENSOR
13
COMMON
R7
10K
D8
D1
RP
CF
100µF
15V
COMMON
R3
12K
10
D9
Q6
Q2
Q3
R10
40K
8
TO
COMMON
D12
Q10
14 IC
7
TO
COMMON
R5
9.6K
3
R9
25
IC = Internal connection - DO NOT USE (Terminal restriction applies only to
FIGURE 1. SCHEMATIC DIAGRAM OF CA3059 AND CA3079
FOR
INCREASED
GATE DRIVE
Q8
Q9
D11
1 IC
INHIBIT
INPUT
4
R8
15
R6
15K
Q7
D10
D15
All resistance values are in Ω
NOTE: Circuitry within shaded areas
not included in CA3079
9
11
Q4 Q5
Q1
FAIL-SAFE INPUT
R4
10K
6 IC
FOR
EXTERNAL
TRIGGER
4
TO
THYRISTOR
GATE
Specifications CA3059, CA3079
Absolute Maximum Ratings TA = +25oC
Thermal Information
DC Supply Voltage (Between Terminals 2 & 7)
CA3059 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
CA3079 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V
DC Supply Voltage (Between Terminals 2 & 8)
CA3059 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
CA3079 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V
Peak Supply Current (Terminals 5 & 7) . . . . . . . . . . . . . . . . . . .±50mA
Output Pulse Current (Terminal 4) . . . . . . . . . . . . . . . . . . . . . 150mA
Thermal Resistance
θJA
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100oC/W
Power Dissipation
Up to TA = +55oC CA3059, CA3079 . . . . . . . . . . . . . . . . . 950mW
Above TA = +55oC CA3059, CA3079 . . Derate Linearly 10mW/oC
Ambient Temperature
Operating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At distance 1/16” ± 1/32” (1.59 ± 0.79) from case
for 10 seconds max
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
TA = +25oC, For all Types, Unless Otherwise Specified. All voltages are measured with respect to
Terminal 7. For Operating at 120VRMS, 50-60Hz (AC Line Voltage) (Note 1)
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
RS = 8kΩ, IL = 0
6.1
6.5
7
V
RS = 10kΩ, IL = 0
-
6.8
-
V
DC SUPPLY VOLTAGE (Figure 2A, 2B, 2C)
Inhibit Mode
At 50/60Hz
VS
At 400Hz
At 50/60Hz
Pulse Mode
At 50/60Hz
VS
At 400Hz
At 50/60Hz
Gate Trigger Current (Figures 3, 4A)
IGT
Terminal 4
RS = 5kΩ, IL = 0
-
6.4
-
V
RS = 8kΩ, IL = 0
6
6.4
7
V
RS = 10kΩ, IL = 0
-
6.7
-
V
RS = 5kΩ, IL = 0
-
6.3
-
V
Terminals 3 and 2 Connected,
VGT = 1V
-
105
-
mA
Terminal 3 open, Gate Trigger
Voltage (VGT) = 0
50
84
-
mA
Terminals 3 and 2 Connected, Gate
Trigger Voltage (VGT) = 0
90
124
-
mA
Terminal 3 open, V+ = 12V, VGT = 0
-
170
-
mA
240
-
mA
0.465
0.485
0.520
-
70
100
140
µs
PEAK OUTPUT CURRENT (PULSED) (Figures 4, 5)
With Internal Power Supply
Figure 4a, 4b
IOM
Terminal 4
With External Power Supply
Figure 5a, 5b, 5c
IOM
Terminal 4
Inhibit Input Ratio (Figure 6)
V 9/V2
Terminals 3 and 2 Connected,
V+ = 12V, VGT = 0
Voltage Ratio of Terminals 9 to 2
TOTAL GATE PULSE DURATION (Note 2) (Figure 7A, 7B, 7C, 7D)
For Positive dv/dt
50-60Hz
For Negative dv/dt
50-60Hz
tP
CEXT = 0
CEXT = 0, REXT = ∞
400Hz
tN
CEXT = 0
CEXT = 0, REXT = ∞
400Hz
-
12
-
µs
70
100
140
µs
-
10
-
µs
-
50
-
µs
PULSE DURATION AFTER ZERO CROSSING (50-60Hz) (Figure 7A)
CEXT = 0, REXT = ∞
For Positive dv/dt
tP1
For Negative dv/dt
tN1
-
60
-
µs
I4
-
0.001
10
µA
II
-
220
1000
nA
-
220
2000
nA
-
1.5 to
5
-
V
OUTPUT LEAKAGE CURRENT (Figure 8)
Inhibit Mode
INPUT BIAS CURRENT (Figure 9)
CA3059
CA3079
Common-mode Input Voltage Range
VCMR
Terminals 9 and 13 Connected
5
Specifications CA3059, CA3079
Electrical Specifications
TA = +25oC, For all Types, Unless Otherwise Specified. All voltages are measured with respect to
Terminal 7. For Operating at 120VRMS, 50-60Hz (AC Line Voltage) (Note 1) (Continued)
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
6
-
mV
SENSITIVITY (Note 3) (Figures 4(a), 11)
∆V13
Pulse Mode
Terminal 12 open
NOTES:
1. The values given in the Electrical Characteristics Chart at 120V also apply for operation at input voltages of 208/230V, and 277V, except
for Pulse Duration. However, the series resistor (R S) must have the indicated value, shown in the chart in the Functional Block Diagram,
for the specified input voltage.
2. Pulse Duration in 50Hz applications is approximately 15% longer than shown in Figure 7(b).
3. Required voltage change at Terminal 13 to either turn OFF the triac when ON or turn ON the triac when OFF.
Maximum Voltage Ratings TA = +25oC
MAXIMUM
CURRENT
RATINGS
MAXIMUM VOLTAGE RATINGS TA = +25oC
TERM. NOTE 3
NO.
1
1
Note 3
2
3
4
5
Note 1
6
Note 3
7
NOTE 1 NOTE 3
2
3
4
5
Note 4 Note 4 Note 4 Note 4
0
-15
0
-15
0
-15
2
-14
6
7
15
0
10
-2
0
-14
NOTES
2, 3
NOTE 3
8
9
10
11
12
13
14
Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4
0
0
Note 5 Note 5
-14
-14
0
-14
0
-14
0
-14
Note 4
0
-14
0
-14
IIN
mA
IOUT
mA
10
0.1
150
10
Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4
Note 4
2
-10
Note 4
Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4
0.1
150
50
10
7
-7
Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4
14
0
Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4
Note 4
8
9
14
0
Note 4
20
0
2.5
-2.5
14
0
6
-6
10
0
Note 4 Note 4 Note 4 Note 4 Note 4
Note 4 Note 4
0.1
2
Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4
10
Note 4 Note 4 Note 4 Note 4 Note 4 Note4
11
Note 4 Note 4 Note 4 Note 4 Note4
Note 4 Note 4
12
Note 3
50
50
13
Note 4 Note 4 Note4
14
Note 3
2
2
This chart gives the range of voltages which can be applied to the terminals listed horizontally with respect to the terminals listed vertically.
For example, the voltage range of horizontal Terminal 6 to vertical Terminal 4 is 2V to -10V.
NOTES:
1. Resistance should be inserted between Terminal 5 and external supply or line voltage for limiting current into Terminal 5 to less than
50mA.
2. Resistance should be inserted between Terminal 14 and external supply for limiting current into Terminal 14 to less than 2mA.
3. For the CA3079 indicated terminal is internally connected and, therefore, should not be used.
4. Voltages are not normally applied between these terminals; however, voltages appearing between these terminals are safe, if the specified voltage limits between all other terminals are not exceeded.
5. For CA3079 (0V to -10V).
6
CA3059, CA3079
4.6K
0.3K
120VRMS, 50/60Hz OPERATION
INPUT RESISTANCE (RS) = 10kΩ
NO EXTERNAL LOAD
2
13
INTERNAL DC SUPPLY (V)
PULSE
INHIBIT
4.6K
RL
RS
5
CA3059
CA3079
AC LINE
100µF
11
VS
7
7.00
INHIBIT MODE
6.75
6.50
PULSE MODE
6.25
6.00
IL
8
4
9
5.75
EXTERNAL
LOAD
CURRENT
10
ALL RESISTANCE
VALUES ARE IN Ω
-75
GATE TRIGGER CURRENT (mA)
INTERNAL DC SUPPLY (V)
6.5
RS = 5kΩ
(INHIBIT
MODE)
6.0
5.5
5.0
RS = 10kΩ
(INHIBIT
MODE)
4.5
RS = 5kΩ
(PULSE
MODE)
RS = 10kΩ
(PULSE
MODE)
4.0
1
2
130
3
4
5
6
7
75
100
125
110
100
TERMINALS 2 AND 3
CONNECTED
90
80
70
60
50
TERMINAL 3 OPEN
0
8
1
10
11
5
CA3059
CA3079
4
IOM (4)
OR
IGT(4)
13
2
1Ω
±1%
3
FIGURE 3. GATE TRIGGER CURRENT vs GATE TRIGGER
VOLTAGE FOR CA3059 AND CA3079
PEAK OUTPUT CURRENT, PULSED (mA)
9
2
GATE TRIGGER (V)
RS
10K
8
50
120
40
FIGURE 2C. DC SUPPLY VOLTAGE vs EXTERNAL LOAD
CURRENT FOR CA3059 AND CA3079
7
25
120VRMS, 50/60Hz OPERATION
TA = +25o C
EXTERNAL LOAD CURRENT (mA)
AC LINE
0
FIGURE 2B. DC SUPPLY VOLTAGE vs AMBIENT TEMPERATURE FOR CA3059 AND CA3079
120VRMS, 50/60Hz OPERATION
TA = +25 oC
0
-25
AMBIENT TEMPERATURE (oC)
FIGURE 2A. DC SUPPLY VOLTAGE TEST CIRCUIT FOR CA3059
AND CA3079
3.5
-50
OSCILLOSCOPE
WITH
HIGH GAIN
INPUT
3
120VRMS, 50/60Hz OPERATION
GATE TRIGGER, VGT = 0 (V)
175
150
TERMINALS 2 AND 3
CONNECTED
125
100
75
TERMINAL 3 OPEN
50
-75
VGT
-50
-25
0
25
50
75
100
125
o
AMBIENT TEMPERATURE ( C)
6K
5K
100µF
FIGURE 4B. PEAK OUTPUT CURRENT (PULSED) vs AMBIENT
TEMPERATURE FOR CA3059 AND CA3079
FIGURE 4A. PEAK OUTPUT (PULSED) AND GATE TRIGGER
CURRENT WITH INTERNAL POWER SUPPLY
TEST CIRCUIT FOR CA3059 AND CA3079
7
CA3059, CA3079
V+
3
2
5K
RS
10K
13
5
120VRMS
60Hz
6K
CA3059
4
11
7
IOM(4)
10
9
1Ω
±1%
8
5
OSCILLOSCOPE
WITH
HIGH GAIN
INPUT
120VRMS, 50/60Hz OPERATION
GATE TRIGGER, VGT = 0 (V)
300
PEAK OUTPUT, PULSED (mA)
100µF
TERMINALS 2 AND 3
CONNECTED
250
200
TERMINAL 3 OPEN
150
100
50
0
VGT
0
5
10
15
20
EXTERNAL POWER SUPPLY, V+ (V)
ALL RESISTANCE VALUES ARE IN Ω
FIGURE 5B. PEAK OUTPUT CURRENT (PULSED) vs EXTERNAL POWER SUPPLY VOLTAGE FOR CA3059
FIGURE 5A. PEAK OUTPUT CURRENT (PULSED) WITH EXTERNAL POWER SUPPLY TEST CIRCUIT FOR CA3059
9
10
6
11
RS
10K
5
250
120VRMS
60Hz
CA3059
CA3079
4
7
EXTERNAL
SUPPLY
V+ = 13V
8
12V
13
R1
ALL RESISTANCE
VALUES IN Ω
2
14
R2
100µF
10V
150
13V
12V
8V
FIGURE 6(A). INPUT INHIBIT VOLTAGE RATIO TEST CIRCUIT
FOR CA3059 AND CA3079
10V
100
INPUT INHIBIT VOLTAGE RATIO, V9/V2
PEAK OUTPUT, PULSED (mA)
200
8V
5V
5V
50
3V
3V
120VRMS, 50/60Hz OPERATION
GATE TRIGGER VOLTS (VGT) = 0
TERMINALS 2 AND 3 CONNECTED
TERMINAL 3 OPEN
0
-50
-20
10
40
70
100
120VRMS, 50/60Hz OPERATION
0.60
0.55
0.50
0.45
0.40
0.35
0.30
130
o
-50
-25
0
25
50
75
100
125
o
AMBIENT TEMPERATURE ( C)
AMBIENT TEMPERATURE ( C)
FIGURE 6B. INPUT INHIBIT VOLTAGE RATIO vs AMBIENT TEMPERATURE FOR CA3059 AND CA3079
FIGURE 5C. PEAK OUTPUT CURRENT (PULSED) vs AMBIENT
TEMPERATURE FOR CA3059
8
GATE
PULSE
TOTAL GATE PULSE DURATION (µs)
CA3059, CA3079
AC LINE
- dv/dt
+ dv/dt
0V
tP1
tP
RS
10K
120VRMS
60Hz
tN1
tN
9
10
11
5
CA3059
CA3079
C(EXT)
4
7
1M
OSC.
WITH
HIGH
GAIN
INPUT
120VRMS, 50/60Hz OPERATION
TA = +25o C
300
tP (POSITIVE dv/dt)
200
tN (NEGATIVE dv/dt)
100
0
8
12
6K
REXT
0
2
13
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09
5K
EXTERNAL CAPACITANCE (µF)
100µF
NOTE: Circuitry within shaded area not included in CA3079.
All resistance values are in Ω
FIGURE 7B. TOTAL GATE PULSE DURATION vs EXTERNAL
CAPACITANCE FOR CA3059 AND CA3079
FIGURE 7A. GATE PULSE DURATION TEST CIRCUIT WITH
ASSOCIATED WAVEFORM FOR CA3059 AND
CA3079
700
500
TOTAL GATE PULSE DURATION (µs)
600
PULSE DURATION AFTER
ZERO CROSSING (µs)
40
120VRMS, 50/60Hz OPERATION
TA = +25oC
tN1 (NEGATIVE dv/dt)
400
300
tP1 (POSITIVE dv/dt)
200
100
0
0
120VRMS, 50/60Hz OPERATION
TA = +25oC
30
20
tP (POSITIVE dv/dt)
10
tN (NEGATIVE dv/dt)
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
10
EXTERNAL CAPACITANCE (µF)
100
EXTERNAL RESISTANCE (kΩ)
FIGURE 7C. PULSE DURATION AFTER ZERO CROSSING vs
EXTERNAL CAPACITANCE FOR CA3059 & CA3079
FIGURE 7D. TOTAL GATE PULSE DURATION vs EXTERNAL
RESISTANCE FOR CA3059
OUTPUT LEAKAGE (nA)
100
V+ = 6V
120VRMS, 50/60Hz OPERATION
INPUT RESISTANCE (RS = 100kΩ
NO EXTERNAL LOAD
2
10
CA3059
CA3079
1
+3V
9
8
7
13
0.1
-80 -60 -40 -20
0
20
40
60
II
80 100 120 140
AMBIENT TEMPERATURE (oC)
FIGURE 9. INPUT BIAS CURRENT TEST CIRCUIT FOR CA3059
AND CA3079
FIGURE 8. OUTPUT LEAKAGE CURRENT (INHIBIT MODE) vs
AMBIENT TEMPERATURE FOR CA3059 AND CA3079
9
220VRMS, 50/60Hz OPERATION
INPUT RESISTANCE (RS) = 10kΩ
300
60Hz, tP
(+ dv/dt)
50Hz, tP
(+ dv/dt)
200
100
60Hz, tN
(- dv/dt)
50Hz, tN
(- dv/dt)
0
0
0.02
0.04
0.06
600
TOTAL GATE PULSE DURATION (µs)
TOTAL GATE PULSE DURATION (µs)
CA3059, CA3079
0.08
220VRMS, 50/60Hz OPERATION
INPUT RESISTANCE (RS) = 20kΩ
60Hz, tP
(+ dv/dt)
400
200
0
0
0.1
0.02
0.04
50Hz, tN1
(- dv/dt)
TIME FROM ZERO CROSSING
TO END OF PULSE (µs)
TIME FROM ZERO CROSSING
TO END OF PULSE (µs)
220VRMS, 50/60Hz OPERATION
INPUT RESISTANCE (RS) = 10kΩ
60Hz, tN1
(- dv/dt)
60Hz, tP1
(+ dv/dt)
50Hz, tP1
(+ dv/dt)
0
0.02
0.04
0.08
0.1
FIGURE 10B.
200
0
0.06
EXTERNAL CAPACITANCE (µF)
FIGURE 10A.
400
60Hz, tN
(- dv/dt)
50Hz, tN
(- dv/dt)
EXTERNAL CAPACITANCE (µF)
600
50Hz, tP
(+ dv/dt)
0.06
0.08
220VRMS, 50/60Hz OPERATION
INPUT RESISTANCE (RS) = 20kΩ
600
60Hz, tN1
(- dv/dt)
50Hz, tN1
(- dv/dt)
400
50Hz, tP1
(+ dv/dt)
200
60Hz, tP1
(+ dv/dt)
0
0.1
0
0.02
EXTERNAL CAPACITANCE (µF)
0.04
0.06
0.08
0.1
EXTERNAL CAPACITANCE (µF)
FIGURE 10C.
FIGURE 10D.
7
SENSOR RESISTANCE = 5kΩ
30
12
TERMINALS 7 AND 12 CONNECTED
DC GATE CURRENT MODE
(CA3058 & CA3059)
6
10
TERMINAL 12 OPEN
PULSED GATE CURRENT MODE
(ALL TYPES)
0
-75
-25
0
25
50
75
100
AREA OF UNCERTAIN
OPERATION
5
4
AREA OF NORMAL
OPERATION
3
2
AREA OF UNCERTAIN
OPERATION
1
0
-50
THYRISTOR TURN-OFF
6
TERMINAL 14 (V)
20
18
SENSITIVITY, ∆V13 (mV)
∆SENSOR RESISTANCE, ∆RON - ROFF (Ω)
FIGURE 10. RELATIVE PULSE WIDTH AND LOCATION OF ZERO CROSSING FOR 220V OPERATION FOR CA3059 AND CA3079
THYRISTOR TURN-OFF
0
125
-50
-25
0
25
50
75
AMBIENT TEMPERATURE (oC)
AMBIENT TEMPERATURE (oC)
FIGURE 11. SENSITIVITY vs AMBIENT TEMPERATURE FOR
CA3059 AND CA3079
FIGURE 12. OPERATING REGIONS FOR BUILT-IN PROTECTION CIRCUIT FOR CA3059
10
CA3059, CA3079
OFF
10KΩ
2W
120VAC
60Hz
5
ON
100µF
15VDC
+
OFF
6
RL
1
ON
G
14
C1
4
CA3059
13
-
C1
+
100µF
15VDC
10
3
MT2
CA3059
CA3079
9
4
8
R1
9
1
G
14
-
7
7
12
3
6
2
MT1
6
R1
5
120VAC
60Hz
2
RL
10KΩ
2W
MT2
11
13
tON = 0.67 R1C1
R1(max. value allowable) = 1mΩ
10
11
12
td = 0.67 R1C1
FIGURE 13. LINE-OPERATED ONE-SHOT TIMER
FIGURE 14. LINE-OPERATED THYRISTOR CONTROL TIME
DELAY TURN-ON CIRCUIT
ON
OFF
10KΩ
2W
C1
5
R2
RL
R1
6
MT2
1
2
120VAC
60Hz
100µF
15VDC
RP
+
4
CA3059
13
-
MT1
6
NTC
SENSOR
td = RT C1
RT =
G
14
7
12
3
R 1R2
9
10
11
R 1 + R2
FIGURE 15. ON/OFF TEMPERATURE CONTROL CIRCUIT WITH DELAYED TURN-ON
12
SWITCHED
LOAD
10
11
5
120VAC
5KΩ
2W
MT2
13
CA3059
RECTIFIER
AND TRIAC
CONTROL
1
T2300B
MAX LOAD = 2.5A
1KΩ
4
MT1
G
8
7
6
9
100µF
-
10KΩ
+
10
KΩ
2
R2
68KΩ
R6
2MΩ
RESET 11
OUTPUT
NOTE:
Terminal 1 goes “High”
(Logic “1”) after 2048
pulses are applied to
Terminal 10.
For 8 hour delay:
R1 = 12MΩ
C1 = 2µF
1
SENSOR
16
COS/MOS CD4040A
12-STAGE COUNTER
1
R7
5KΩ
VDD+
6
10
7
R5
1KΩ
8
12
3
15
8
10
2
4
14
16
R4
10KΩ
FIGURE 16A. LINE-OPERATED IC TIMER FOR LONG TIME PERIODS
11
R1
11
PULSE GENERATOR
CA3097E THYRISTOR/
TRANSISTOR ARRAY
9
IN
5
13
R3
100KΩ
C1
MT1
CA3059, CA3079
“NIGHT”
“DAY”
SENSOR ILLUMINATION
COUNTER RESET
(TERMINAL 11 OF CD4040)
e.g., 8 HRS
“CLOCK” PULSES
(TERMINAL 9 OF CA3097E)
1 PULSE/SEC
COUNTER OUTPUT
(TERMINAL 1 OF CD4040)
TERMINAL 6 OF CA3059 AND
TERMINAL 5 OF CA3097E
TERMINAL 4 OF CA3059
AND POWER IN LOAD
FIGURE 16B. TIMING DIAGRAM FOR FIGURE 16A
C1
100µF
2
RL
10
120VAC
60Hz
11
10K
2W
14
CA3059
RESET
SW1
RUN
1K
120pps
13
5
9
TRIAC
CONTROL
RECTIFIER
PULSE
GENERATOR
T2302B
MAX LOAD = 2.5A
4
200Ω
6
G
1
8
7
10K
TRIAC
MONOSTABLE
4
1K
ASTABLE
SW2
+VDD (≅ +6.5V)
RESET
120pps
11
C2
0.001
10
16
+VDD (≅ +6.5V)
COS/MOS CD4020A
14-STAGE BINARY
COUNTER
8
2 7 2 8 29 210
211
212
2
16
213
214
H
G
VDD Kd
10
Ka
F
a
b
c
d
e
f
g
h
CD4048A
EXPANDABLE
8 INPUT GATE
E
D
C
PROGRAMMING
INTERCONNECTIONS
B
A
VSS
8
EXP
FIGURE 17A. PROGRAMMABLE ULTRA-ACCURATE LINE-OPERATED TIMER.
12
Kb
Kc
7
9
15
1
OUTPUT
CA3059, CA3079
TIME PERIODS (t = 0.5333 s)
1t
2t
4t
8t
16t
32t
64t
128t
f
g
h
tO
CD4020A TERMINALS
a
b
c
d
e
CD4048A TERMINALS
A
B
C
D
E
F
G
H
C
NC
NC
NC
NC
NC
NC
NC
NC
C
NC
NC
NC
NC
NC
NC
2t
C
C
NC
NC
NC
NC
NC
NC
3t
NC
NC
C
NC
NC
NC
NC
NC
4t
C
NC
C
NC
NC
NC
NC
NC
5t
NC
C
C
NC
NC
NC
NC
NC
6t
1t
C
C
C
NC
NC
NC
NC
NC
7t
NC
NC
NC
C
NC
NC
NC
NC
8t
C
NC
NC
C
NC
NC
NC
NC
9t
NC
C
NC
C
NC
NC
NC
NC
10t
C
C
NC
C
NC
NC
NC
NC
11t
NC
NC
C
C
NC
NC
NC
NC
12t
C
NC
C
C
NC
NC
NC
NC
13t
NC
C
C
C
NC
NC
NC
NC
14t
C
C
C
C
NC
NC
NC
NC
15t
C
C
C
C
NC
C
C
NC
111t
NC
NC
NC
NC
C
C
C
NC
112t
C
NC
NC
NC
C
C
C
NC
113t
C
C
C
C
C
C
C
C
255t
NOTES:
1. tO = Total time delay = n1 t + n2 t + . . . nnt.
2. C = Connect. For example, interconnect terminal a of the CD4020A and terminal A of the CD4048A.
3. NC = No Connection. For example, terminal b of the CD4020A open and terminal B of the CD4048A connected to +VDD bus.
AC
SUPPLY
VOLTAGE
CA3059
OUTPUT
(PIN 4 AND PIN 6)
CD4048A
OUTPUT
AC IN LOAD (R L )
FIGURE 17B. “PROGRAMMING” TABLE FOR FIGURE 17(A).
13
CA3059, CA3079
Operating Considerations
2. Set the value of RP and sensor resistance (R X) between
2kΩ and 100kΩ.
Power Supply Considerations for CA3059 and CA3079
The CA3059 and CA3079 are intended for operation as selfpowered circuits with the power supplied from and AC line
through a dropping resistor. The internal supply is designed
to allow for some current to be drawn by the auxiliary power
circuits. Typical power supply characteristics are given in
Figures 2(b) and 2(c).
3. The ratio of RX to RP, typically, should be greater than
0.33 and less than 3. If either of these ratios is not met
with an unmodified sensor over the entire anticipated
temperature range, then either a series or shunt resistor
must be added to avoid undesired activation of the circuit.
Power Supply Considerations for CA3059
If operation of the protection circuit is desired under conditions other than those specified above, then apply the data
given in Figure 12.
The output current available from the internal supply may not
be adequate for higher power applications. In such applications an external power supply with a higher voltage should
be used with a resulting increase in the output level. (See
Figure 4 for the peak output current characteristics.) When
an external power supply is used, Terminal 5 should be connected to Terminal 7 and the synchronizing voltage applied
to Terminal 12 as illustrated in Figure 5(a).
External Inhibit Function for the CA3059
A priority inhibit command may be applied to Terminal 1. The
presence of at least +1.2V at 10µA will remove drive from
the thyristor. This required level is compatible with DTL or
T2L logic. A logical 1 activates the inhibit function.
DC Gate Current Mode for the CA3059
Operation of Built-In Protection for the CA3059
Connecting Terminals 7 and 12 disables the zero-crossing
detector and permits the flow of gate current on demand
from the differential sensing amplifier. This mode of operation is useful when comparator operation is desired or when
inductive loads are switched. Care must be exercised to
avoid overloading the internal power supply when operating
in this mode. A sensitive gate thyristor should be used with a
resistor placed between Terminal 4 and the gate in order to
limit the gate current.
A special feature of the CA3059 is the inclusion of a protection circuit which, when connected, removes power from the
load if the sensor either shorts or opens. The protection circuit is activated by connecting Terminal 14 to Terminal 13 as
shown in the Functional Block Diagram. To assure proper
operation of the protection circuit the following conditions
should be observed:
1. Use the internal supply and limit the external load current
to 2mA with a 5kΩ dropping resistor.
The photographs and dimensions represent a chip when it is par of
the wafer. When the wafer is cut into chips, the cleavage angles are
57o instead of 90o with respect to the face of the chip. Therefore, the
isolated chip is actually 7 mils (0.17mm) larger in both dimensions.
Dimensions in parentheses are in millimeters and are derived from
the basic inch dimensions as indicated. Grid gradations are in mils
(10-3 inch).
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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14