LatticeECP2™ Standard Evaluation Board User’s Guide May 2007 Revision: ebdug18_01.3 LatticeECP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Introduction The LatticeECP2 Standard Evaluation Board is a complete, integrated design, featuring a LatticeECP2 FPGA and a variety of both application-specific and general-purpose peripheral interfaces. This board provides a convenient platform to evaluate, test, and debug user designs, including designs requiring PCI/PCI-X. This board includes the following features: • LatticeECP2 FPGA device in 484 fpBGA package • SPI Serial Flash device included for low-cost, non-volatile configuration storage • PCI/PCI-X edge connector (188-pin) supporting Master or Target – PCI 2.2 - 32/64 bit, 33/66 MHz, 3.3V – PCI-X - 32/64 bit, 66/133 MHz, parity or ECC, 3.3V (Mode 1) • RS-232 connector • 33.33 MHz oscillator • RJ-45 connector • LCD connector • Compact Flash connector • Prototyping area with access to over 210 I/O pins • Optional SMA/SMB connectors (up to eight) for high-speed clock and data interfacing • 7-segment display, eight general purpose switches, two momentary switches, eight user LEDs, and various status LEDs • Required voltages supplied by PCI/PCI-X or one external 5V DC supply • ispVM® System programming support Figure 1. Lattice ECP2 Standard Evaluation Board Electrical, Mechanical, and Environmental Specifications The nominal board dimensions are 9.75 inches by 4.2 inches. The environmental specifications are as follows: • Operating temperature: 0ºC to 55ºC • Storage temperature: -40ºC to 75ºC 2 LatticeECP2 Standard Evaluation Board User’s Guide Lattice Semiconductor • Humidity: < 95% without condensation • 5VDC input (+/- 10%) up to 4A, or 3.3V input from PCI/PCI-X backplane Additional Resources Additional resources relating to the LatticeECP2 Standard Evaluation Board (including updated documentation, and sample programs) can be found at the following URL: www.latticesemi.com/products/developmenthardware/fpgafspcboards/ecp2stardevaluationboard.cfm Features LatticeECP2 Device This board features a LatticeECP2 FPGA with a 1.2V DC core in a 484-ball fpBGA package. A complete description of this device can be found in the LatticeECP2 Family Data Sheet available on the Lattice web site at www.latticesemi.com/ecp2. On-Board Oscillator The 3.3V oscillator socket at Y1 accepts both full-size (14-pin) and half-size (8-pin) oscillators, and will route the oscillator output to a LatticeECP2 primary clock input or a PLL input, depending on the oscillator’s position in the socket (see Figure 2). When a full size oscillator is installed such that pin 1 of the oscillator aligns with pin 1 of the socket, the output of the oscillator drives the primary clock at LatticeECP2 pin J21 (this is the default position). When pin 1 of the oscillator is aligned to pin 2 of the socket, the clock is routed to LatticeECP2 pin J21. When using a half size oscillator, align pin 1 of the oscillator to pin 1 of the socket to drive the primary clock, or align pin 1 of the oscillator to pin 5 of the socket to drive the PLL. Note that pin 1 of the oscillator is expected to be a no-connect pin. Figure 2. Oscillator Options Pin-1 Pin-16 Pin-1 Full-Size 33.33 MHz Default Position Primary Clock (J21) PLL Clock (N21) GND Pin-1 3.3V Primary Clock (J21) PLL Clock (N21) GND Pin-16 Pin-1 Pin-16 3.3V 3.3V Primary Clock (J21) Primary Clock (J21) PLL Clock (N21) GND Half-Size 33.33 MHz Full-Size 33.33 MHz GND Pin-16 Half-Size 33.33 MHz 3.3V PLL Clock (N21) SPI Serial Flash SPI Serial Flash are available in three package styles, two of those packages, 8-pin SO and 16-pin SO, are supported by this board. In general, the 8-pin devices support densities up to 16Mb, while the 16-pin devices support larger densities. The device chosen for inclusion on this board depends on the density of the installed LatticeECP2, but the SPI Serial Flash will be large enough to allow two bitstreams to be stored simultaneously in order to support SPIm mode. 3 LatticeECP2 Standard Evaluation Board User’s Guide Lattice Semiconductor The 8-pin device footprint is at U4; the 16-pin device footprint is at U5. Only one location can be populated at a time. Configuration/Programming Headers Two programming headers are provided on the evaluation board, providing access to the LatticeECP2 JTAG port and sysCONFIG™ port. The JTAG connector is a 1x10 header and the sysCONFIG connector is a 2x17 header. Both the JTAG and the sysCONFIG ports are also provided with loop-through connectors to allow for easy daisy chaining of multiple boards. With proper jumper selection (see the next section) standard IDC ribbon cable can be used without the need to swap wires on the cable. See the Configuring/Programming The Board section of this document for more information on this topic. The pinouts for these headers are provided in the following tables. Note: A parallel port ispDOWNLOAD® cable is included with each LatticeECP2 Standard Evaluation Board. When using a parallel port (1x8) ispDOWNLOAD cable, connect pin 1 of the cable to pin 1 of the 1x10 JTAG header. For more information on the ispDOWNLOAD Cable, see the ispDOWNLOAD Cables Data Sheet available on the Lattice web site at www.latticesemi.com. Table 1. JTAG Programming Header Pinout J4 (1x10) Function Vcc (3.3V) 1 1 2 TDO TDI 3 1 PROGN 4 N/C 5 TMS 6 Ground 7 1 8 TCK DONE 9 1 10 INIT Chain 1. See section below on jumpers. Table 2. JTAG Loop-Through Header Pinout J5 (1x10) Function N/C 1 TDO Chain1 2 TDI Chain1 3 PROGN1 4 N/C 5 TMS 6 Ground 7 TCK1 8 DONE 9 INIT Chain1 10 1. See section below on jumpers. 4 LatticeECP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Table 3. sysCONFIG Header Pinout (J40) Function Pin Function CCLK 1 2 BUSY / SISPI 3 4 D6 DI/D01 5 6 Vcc Bank8 D7 / DOUT1 7 8 INITN DONE Ground 9 10 PROGRAMN D7 11 12 Ground D6 13 14 Ground D5 15 16 Ground D4 17 18 Ground D3 19 20 Ground D2 21 22 Ground D1 23 24 Ground D0 25 26 Ground 27 28 WRITEN CS1N 29 30 CFG0 Vcc Bank8 31 32 CFG1 Ground 33 34 CFG2 CSN1 1 1. See section below on jumpers. Table 4. sysCONFIG Loop-Through Header Pinout (J41) Function Pin Function CCLK 1 2 Ground N/C 3 4 N/C DOUT / CSSON 5 6 N/C N/C 7 8 INITN DONE 9 10 PROGRAMN D7 11 12 Ground D6 13 14 Ground D5 15 16 Ground D4 17 18 Ground D3 19 20 Ground D2 21 22 Ground D1 23 24 Ground D0 25 26 Ground CSN / N/C1 27 28 WRITEN CS1N / N/C1 29 30 N/C N/C 31 32 N/C Ground 33 34 N/C 1. See section below on jumpers. JTAG and sysCONFIG Jumpers There are several JTAG and sysCONFIG cabling options that can be selected using jumpers. 5 LatticeECP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Default Jumpers Settings This table lists the default settings for all of the jumpers on the LatticeECP2 Standard Evaluation Board. For a complete description of each jumper refer to the next sections. Table 5. Default Jumper Settings Location Position Location Position J1 1 to 2 J29 1 to 2 J3 1 to 2 J30 1 to 2 3 to 4 5 to 6 J7 2 to 3 J31 Open J8 1 to 2 J32 Open J9 Open J33 1 to 2 J10 Open J34 2 to 3 J11 Open J35 Open J13 Open J36 Open J17 1 to 2 J37 1 to 2 J18 1 to 2 J38 Open J19 Open J39 1 to 2 J22 Open J43 1 to 2 3 to 4 5 to 6 J23 Open J44 1 to 2 J24 Open JTAG Jumpers Table 6. TDO Chain Jumper Location J7 Position Function 1 to 2 Multiple boards, but not the last board in the chain 2 to 3 Single board, or the last board in a chain Default X Determines the JTAG TDO path. Table 7. TCK Pull-Down Location J8 Position Function 1 to 2 Pull-down, 4.7K to ground Open No pull-down Default X There should be only one TCK pull-down on a JTAG chain. Table 8. PROGRAMN Pin to JTAG Location J10 Position Function 1 to 2 Connects PROGRAMN pin to the JTAG chain Open Disconnects PROGRAMN pin from JTAG chain This jumper is normally not installed. 6 Default X LatticeECP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Table 9. INITN Pin to JTAG Location Position J11 Function 1 to 2 Connects INITN pin to the JTAG chain Open Disconnects INITN pin from the JTAG chain Default X This jumper is normally not installed. sysCONFIG Jumpers Table 10. CS1N Location Position J31 Function 1 to 2 Pulls CS1N high 2 to 3 Pulls CS1N low Open No pull-up or pull-down on CS1N Default X Table 11. CSN Location Position J32 Function 1 to 2 Pulls CSN high 2 to 3 Pulls CSN low Open No pull-up or pull-down on CSN Default X Table 12. DI/D[0] Location Position J33 Function 1 to 2 Routes DI to J40-5 to support serial mode 2 to 3 Routes data bit D[0] to J40-5 for SPIFAST support Default X Table 13. D[7]/DOUT Location J34 Position Function 1 to 2 Routes D[7] to J40-7 for SPI sysCONFIG support 2 to 3 Routes DOUT to J40-7 to support serial mode Default X Table 14. CSON to CS1N (Loop-Through) Location J35 Position Function 1 to 2 CSON drives CS1N on the loop-through connector Open CS1N on the loop-through connector is open Default X Table 15. CSON to CSN (Loop-Through) Location J36 Position Function 1 to 2 CSON drives CSN on the loop-through connector Open CSN on the loop-through connector is open 7 Default X LatticeECP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Table 16. Configuration Mode (J43) Configuration Mode SPI (default) Reserved SPIm CFG[2], 1 to 2 CFG[1], 3 to 4 CFG[0], 5 to 6 Jumper (0) Jumper (0) Jumper (0) Jumper (0) Jumper (0) Open (1) Jumper (0) Open (1) Jumper (0) Reserved Jumper (0) Open (1) Open (1) Reserved Open (1) Jumper (0) Jumper (0) Slave Serial Open (1) Jumper (0) Open (1) Reserved Open (1) Open (1) Jumper (0) Slave Parallel Open (1) Open (1) Open (1) Table 17. SPIFAST Location J44 Position Function 1 to 2 SPI fast read, enables read op-code 0x0B Open SPI normal read, enables read op-code 0x03 Default X All SPI Serial Flash shipped with this board support fast read. This jumper must be removed when using the sysCONFIG parallel port. Table 18. Jumper Settings for sysCONFIG Parallel Location Position Notes J31 Open See schematic J32 Open See schematic J33 1 to 2 J34 2 to 3 J43 All Open J44 Open J35, J36 Open Bypass Overflow J35, J36 1 to 2 Flow-through Overflow Table 19. Jumper Settings for sysCONFIG Serial Location Position J31 Open J32 Open J33 1 to 2 J34 2 to 3 Notes Open J43 3 to 4 Open if driven by cable Open J44 Don’t Care J35, J36 Open Bypass Overflow J35, J36 1 to 2 Not allowed 8 LatticeECP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Table 20. Jumper Settings for SPI Emulation via J40 Location Position J31 Open J32 Open J33 2 to 3 J34 1 to 2 J43 J44 Notes 1 to 2 Open if driven by cable 3 to 4 Open if driven by cable 5 to 6 Open if driven by cable Open J35, J36 Open Bypass Overflow J35, J36 1 to 2 Not allowed Power Setup For stand-alone board operation, i.e. outside of a PCI/PCI-X backplane, the evaluation board must be supplied with a single 5V DC power supply. 5V DC power may be applied using an AC adapter, such as the Condor Electronics S-5V0-4A0-U11-206IP (or similar), plugged into the power jack at J47, or via the banana jacks at J45 (ground) and J46 (5V DC). Table 21. AC Adaptor Specifications Voltage 5VDC +/- 10% Current Capacity Up to 4A Polarity Positive Center Connector I.D. 0.1” (2.5mm) Connector O.D. 0.218” (5.5mm) When the board is inserted into a PCI/PCI-X backplane, the on-board 3.3V regulator is automatically disabled; all onboard power will be derived from the PCI/PCI-X 3.3V power rail. Additional on-board regulators supply 1.2V, an adjustable voltage, and 5V (for the optional LCD panel). The adjustable voltage is set by the potentiometer R36, on the right side of the board, and can be set to any value between 1.22V and 2.5V. The header at J30 allows a current measuring device to be inserted between 1.2V and the FPGA core. To measure current remove power from the board, remove all of the jumpers at J30, install a meter between the odd pins and the even pins, for example between pins 1 and 2, and apply power to the board. When measurement is complete, remove power from the board and re-install all three jumpers. Table 22. 1.2V to VCC Core Location Position Function 1 to 2 J30 3 to 4 Default X Connects 1.2V to the FPGA Core 5 to 6 X X The header at J29 allows a current measuring device to be inserted between 3.3V and the FPGA’s VCCAUX. To measure current, remove power from the board, remove the jumper at J29, install a meter between pins 1 and 2, and apply power to the board. When measurement is complete, remove power from the board and re-install the jumper. 9 LatticeECP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Table 23. 3.3V to VCCAUX Location J29 Position 1 to 2 Function Default Connects 3.3V to VCCAUX X The LatticeECP2 is divided into 10 banks of I/Os (see Table 24), and each of these banks has a separate and independent VCC. Each bank supports voltages from 1.2V to 3.3V. However, because some banks, such as banks 4 and 5, which connect to PCI/PCI-X, require a fixed voltage, not all of the banks on this evaluation board are adjustable. The jumpers listed in Table 24 allow the user to select the voltage (VCCIO) applied to the adjustable banks. Note that if the LatticeECP2 will be configured from the SPI Serial Flash, bank 8 must be set to 3.3V (because SPI Serial Flash is 3.3V). Also, if the board is plugged into a PCI/PCI-X connector, bank 6 must be set to 3.3V (because the PCI clock is routed to bank 6 on this board). Table 24. Bank Voltage Selection Bank Function Jumper Settings 0 I/O — 3.3V Only 1 I/O — 3.3V Only 2 I/O J37 1 - 2 = 3.3V 3 - 4 = ADJ 5 - 6 = 1.2V 3 I/O — 3.3V Only 4 I/O — 3.3V Only 5 I/O — 3.3V Only 6 I/O J18 1 - 2 = 3.3V 3 - 4 = ADJ 5 - 6 = 1.2V 7 I/O J17 1 - 2 = 3.3V 3 - 4 = ADJ 5 - 6 = 1.2V 8 sysCONFIG J39 1 - 2 = 3.3V 3 - 4 = ADJ 5 - 6 = 1.2V VCCJ ispJTAG™ — 3.3V Only J17, 18, 37, and 39 must have no more than one jumper installed. The following tables detail the various I/O standards supported by the LatticeECP2 sysIO™ structures. More information can be found in Lattice technical note TN1102, LatticeECP2 sysIO Usage Guide, available on the Lattice web site at www.latticesemi.com. Table 25. Mixed Voltage I/O Support Input sysIO Standards VCCIO 1.2V 1.2V Yes 1.5V Yes 1.8V Yes 2.5V 3.3V 1.5V 1.8V Output sysIO Standards 2.5V 3.3V 1.2V Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 1.5V 1.8V 2.5V 3.3V Yes Yes Yes Yes For example, if VCCIO is 3.3V, then signals from devices powered by 1.2V, 2.5V, or 3.3V can be input and the thresholds will be correct, assuming the user has also selected the desired input level using ispLEVER® software. Output levels are tied directly to VCCIO. 10 LatticeECP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Table 26. sysIO Standards Supported per Bank Top Side, Banks 0-1 Description Right Side, Banks 2-3 Bottom Side, Banks 4-5 Left Side, Banks 6-7 Types of I/O Buffers Single-ended Single-ended and Differential Single-ended Single-ended and Differential Output Standards Supported LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 SSTL18 Class I, II SSTL25 Class I, II SSTL33 Class I, II SSTL18 Class I, II SSTL25 Class I, II SSTL33 Class I, II SSTL18 Class I SSTL2 Class I, II SSTL3 Class I, II SSTL18 Class I SSTL2 Class I, II SSTL3 Class I, II HSTL15 Class I HSTL18_I, II HSTL15 Class I HSTL18 Class I, II HSTL15 Class I HSTL18 Class I, II HSTL15 Class I, III HSTL18 Class I, II, III SSTL18D Class I, II SSTL25D Class I, II SSTL33D Class I, II SSTL18D Class I, II SSTL25D Class I, II SSTL33D Class I, II SSTL18D Class I, II SSTL25D Class I, II, SSTL33D Class I, II SSTL18D Class I, SSTL25D Class I, II, SSTL33D_I, II HSTL15D Class I HSTL18D Class I, II HSTL15D Class I, II HSTL18D Class I, II HSTL15D Class I HSTL18D Class I, II HSTL15D Class I HSTL18D Class I, II PCI33 LVDS25E1 LVPECL1 BLVDS1 RSDS1 PCI33 LVDS LVDS25E1 LVPECL1 BLVDS1 RSDS1 PCI33 LVDS25E1 LVPECL1 BLVDS1 RSDS1 PCI33 LVDS LVDS25E1 LVPECL1 BLVDS1 RSDS1 Inputs All Single-ended, Differ- All Single-ended, ential Differential All Single-ended, Differential All Single-ended, Differential Clock Inputs All Single-ended, Differ- All Single-ended, ential Differential All Single-ended, Differential All Single-ended, Differential PCI Support PCI33 no clamp PCI33 with clamp PCI33 no clamp LVDS (3.5mA) Buffers2 LVDS Output Buffers PCI33 no clamp LVDS (3.5mA) Buffers2 1. These differential standards are implemented by using complementary LVCMOS drivers and external resistors. 2. Available on 50% of the I/Os in the Bank. PCI/PCI-X The LatticeECP2 Standard Evaluation Board is designed to be compatible with PCI (PCI SIG 2.2 specification) and PCI-X (Mode 1). All necessary signals required for 64-bit PCI/PCI-X operation are provided, as shown in Table 27 and Table 28. Table 27. PCI Connections - Solder Side J48 LatticeECP2 Pin sysIO Bank 1 PCI_TRSTN Signal Name - - TP10, PD if master 2 +12V - - Decoupling cap 3 PCI_TMS - - TP11, PU if master 4 PCI_TDI - - TP12, J14-4, J13 5 +5V - - NC 6 PCI_INTA_N - - J19 7 PCI_INTC_N - - J19 11 Note LatticeECP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Table 27. PCI Connections - Solder Side (Continued) J48 Signal Name 8 +5V LatticeECP2 Pin sysIO Bank - - W4 5 - - W5 5 - - Y4 5 - - Y5 5 - - 9 PCIX_ECC5 10 +3.3V 11 PCIX_ECC3 14 +3.3VAUX 15 PCI_RST_N 16 +3.3V 17 PCI_GNT_N 18 GND 19 PME# 20 PCI_AD30 21 3.3V - - 22 PCI_AD28 Y6 5 23 PCI_AD26 W7 5 24 GND - - 25 PCI_AD24 Y7 5 26 PCI_IDSEL U9 5 27 +3.3V - - 28 PCI_AD22 W8 5 29 PCI_AD20 Y8 5 30 GND 31 PCI_AD18 V9 5 32 PCI_AD16 W9 5 33 +3.3V 34 PCI_FRAME_N 35 GND 36 PCI_TRDY_N 37 GND 38 PCI_STOP_N 39 40 41 PCI_SMBDAT 42 GND 43 PCI_PAR Y10 5 44 PCI_AD15 W11 5 45 +3.3V - - 46 PCI_AD13 U12 4 47 PCI_AD11 Y12 4 48 GND - - 49 PCI_AD9 W12 4 52 PCI_CBE0_N V12 4 53 +3.3V - - 54 PCI_AD6 U13 4 55 PCI_AD4 Y13 4 - - W6 5 - - U10 5 - - V10 5 Note NC TP13 TP9 - - W10 5 +3.3V - - PCI_SMBCLK - - TP8, PU if master - - TP14, PU if master - - 12 LatticeECP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Table 27. PCI Connections - Solder Side (Continued) J48 Signal Name LatticeECP2 Pin sysIO Bank - - PCI_AD2 W13 4 PCI_AD0 U14 4 56 GND 57 58 59 +3.3V 60 PCI_REQ64_N 61 62 63 GND - - 64 PCI_CBE7_N V14 4 65 PCI_CBE5_N U15 4 66 +3.3V - - 67 PAR64 T15 4 68 PCI_AD62 Y15 4 69 GND - - 70 PCI_AD60 W15 4 71 PCI_AD58 U16 4 72 GND - - 73 PCI_AD56 V16 4 74 PCI_AD54 T16 4 75 +3.3V - - 76 PCI_AD52 Y16 4 77 PCI_AD50 W16 4 78 GND - - 79 PCI_AD48 Y17 4 80 PCI_AD46 W17 4 81 GND - - 82 PCI_AD44 Y18 4 83 PCI_AD42 W18 4 84 +3.3V - - 85 PCI_AD40 Y19 4 86 PCI_AD38 Y20 4 87 GND - - 88 PCI_AD36 V17 4 89 PCI_AD34 V18 4 90 GND - - 91 PCI_AD32 U18 4 92 NC - - 93 GND - - 94 NC - - - - W14 4 NC - - NC - - Note: PD = pull-down resistor, PU = pull-up resistor, NC = no-connect, TP = test point. 13 Note LatticeECP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Table 28. PCI Connections - Component Side J14 Signal Name LatticeECP2 Pin sysIO Bank Notes 1 -12V - - Decoupling cap 2 PCI_TCK - - TP16, PD if master 3 GND - - 4 PCI_TDO - - TP17, J3, J13 5 +5V - - NC 6 +5V - - NC 7 PCI_INTB_N - - J19 8 PCI_INTD_N - - J19 9 PCI_PRSNT1_N J14 - 10 PCIX_ECC4 W3 5 11 PCI_PRSNT2_N 14 PCIX_ECC2 15 GND 16 PCI_CLK 17 GND 18 PCI_REQ_N 19 +3.3V - - 20 PCI_AD31 AB2 5 21 PCI_AD29 AA3 5 22 GND - - 23 PCI_AD27 AB3 5 24 PCI_AD25 AB4 5 25 3.3V - - 26 PCI_CBE3_N AA5 5 27 PCI_AD23 AB5 5 28 GND - - 29 PCI_AD21 AA6 5 30 PCI_AD19 AB6 5 31 3.3V - - 32 PCI_AD17 AB7 5 33 PCI_CBE2_N AA7 5 34 GND - - 35 PCI_IRDY_N AB8 5 36 +3.3V - - 37 PCI_DEVSEL_N U11 5 38 PCIXCAP - - 39 LOCK# 40 PCI_PERR_N 41 +3.3V 42 PCI_SERR_N 43 +3.3V - - 44 PCI_CBE1_N AB9 5 45 PCI_AD14 AA10 5 46 GND - - - - Y2 5 - - R1 6 - - Y3 5 - - AA8 5 - - AA9 5 14 J23 D20, J22 TP15 LatticeECP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Table 28. PCI Connections - Component Side (Continued) J14 LatticeECP2 Pin sysIO Bank 47 PCI_AD12 Signal Name AB10 5 48 PCI_AD10 AA11 5 49 PCI_M66EN - - 52 PCI_AD8 AB11 5 53 PCI_AD7 Y11 5 54 +3.3V - - 55 PCI_AD5 AB12 5 56 PCI_AD3 AA12 5 57 PCI_GND_57 - - 58 PCI_AD1 AB13 5 59 +3.3V - - 60 PCI_ACK64_N AA13 4 61 +5V - - NC 62 +5V - - NC 63 NC - - 64 GND - - 65 PCI_CBE6_N AB14 5 66 PCI_CBE4_N AA14 4 67 GND - - 68 PCI_AD63 AB15 4 69 PCI_AD61 AA15 4 70 +3.3V - - 71 PCI_AD59 AB16 4 72 PCI_AD57 AA16 4 73 GND - - 74 PCI_AD55 AB17 4 75 PCI_AD53 AA17 4 76 GND - - 77 PCI_AD51 AB18 4 78 PCI_AD49 AA18 4 79 +3.3V - - 80 PCI_AD47 AB19 4 81 PCI_AD45 AB20 4 82 GND - - 83 PCI_AD43 AA20 4 84 PCI_AD41 AB21 4 85 GND - - 86 PCI_AD39 AA22 4 87 PCI_AD37 AA21 4 88 +3.3V - - 89 PCI_AD35 Y22 4 90 PCI_AD33 Y21 4 91 GND - - 92 NC - - 15 Notes J38 U6 LatticeECP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Table 28. PCI Connections - Component Side (Continued) J14 LatticeECP2 Pin sysIO Bank 93 NC Signal Name - - 94 GND - - Notes Note: PD = pull-down resistor, PU = pull-up resistor, NC = no-connect, TP = test point. PCI/PCI-X Jumpers Table 29. PRSNT1 Location Position 1 to 2 J9 Function Default Master PCI/PCI-X 2 to 3 Target PCI/PCI-X Open Target PCI/PCI-X X Not installed. If installing header, first cut trace between 2 and 3. If master, also install R51 and C39. Table 30. PRSNT2 Location Position J23 Function 1 to 2 Master PCI/PCI-X Open Target PCI/PCI-X Default X Not installed. If master, also install R62 and C47. Table 31. PCIXCAP and M66EN Encoding Frequency PCIXCAP(J24) M66EN(J38) PCI PCI-X 1 to 2 2 to 3 33MHz 66MHz 1 to 2 Open 66MHz 66MHz Open 2 to 3 33MHz 133MHz Open Open 66MHz 133MHz Don’t Care 1 to 2 Master Master Default X If master, also install R126 and C111. Table 32. PCI TDI and TDO Location J13 Position Function 1 to 2 Target PCI/PCI-X Open Master PCI/PCI-X Default X Not installed. If master then cut the trace between 1 and 2. Table 33. PCI Interrupt Location J19 Position Function 2 to 4 INT = INTA 1 to 3 INT = INTB 4 to 6 INT = INTC 3 to 5 INT = INTD Default X Not installed. If installing header, first cut trace between 2 and 4. 16 LatticeECP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Table 34. PCI CLK Location Position Function 1 to 2 Routes PCI_CLK to FPGA, only used if installing this board in a PCI or PCI-X backplane. For signal integrity, also remove R27 and R30. D20 provides PCI clamping for this signal. Open Disconnects this signal from the FPGA J22 Default X The differential signals at J20 and J21 can not be used if this jumper is installed (1 to 2). If the board is to be a master, in addition to properly setting the jumpers, the following resistors and capacitors must be installed. Table 35. Install These Resistors and Caps if PCI/PCI-X is a Master Location Value R1, 51, 59, 60, 61, 62, 106, 107, 126 C39, 111 Manufacturer Part Number1 5.6K Panasonic ERJ-3GEYJ562V 0.01uF Panasonic ECU-V1H103KBV 1. Or equivalent. Signal Testing This board supports testing of single-ended and differential signals. High-Speed Single-Ended There are eight FPGA signals that have been routed to special test points on the board. Each signal can include a series resistor, as well as a pull-up resistor and a pull-down resistor (for maximum flexibility these resistors are not included with the board). Each series resistor footprint has a shorting trace that must be cut before installing a resistor (see Figure 3). Next to each signal’s test point a ground point has been added in order to make signal integrity measurements easier and more accurate. Figure 3. Resistor Shorting Trace Cut this trace Table 36. Single Ended SI Test Points Resistors Test Point Pin Series1 Pull-Up Pull-Down TP_SI7 J4 R8 R71 R2 TP_SI6 J5 R9 R72 R3 TP_SI5 L6 R10 R73 R4 TP_SI4 L5 R11 R74 R5 TP_SI3 K2 R12 R75 R6 TP_SI2 K1 R13 R76 R7 TP_SI1 L2 R22 R82 R20 TP_SI0 L1 R23 R83 R21 1. Cut shorting trace before installation. 17 LatticeECP2 Standard Evaluation Board User’s Guide Lattice Semiconductor High-Speed Differential The board supports testing of up to eight differential pairs using two types of connectors, SMA and RJ45. Each pair has provision for a “line-to-line” resistor as well as single-ended series resistors (for maximum flexibility these resistors are not included with the board). The resistors can be used as termination or in combination to provide signal emulation (level shifting). For more information on signal emulation and signal types, please refer to Lattice technical note number TN1102, LatticeECP2 sysIO Usage Guide, available on the Lattice web site at www.latticesemi.com. Table 37. Differential SI Connectors Connector Location J27 J28 J26 J25 J21 J20 J15 J16 U6-1 U6-2 U6-3 U6-4 U6-5 U6-6 U6-7 U6-8 LatticeECP2 Type SMA SMA SMA SMA RJ45 RJ45 RJ45 RJ45 Resistors Type1 Series2 P1 GDLLT IN R24 P2 GDLLC IN R25 M5 PCLKT IN R84 M6 PCLKC IN R85 R1 GPLLT IN R28 R2 GPLLC IN R29 R3 GPLLT FB R89 T4 GPLLC FB R90 E2 GPIO R14 E1 GPIO R15 J2 GPIO R16 J1 GPIO R17 K3 GPIO R77 K4 GPIO R78 Pin L4 GPIO R79 L3 GPIO R87 Line-to-Line R26 R86 R303 R91 R18 R19 R80 R81 1. All support true LVDS. 2. The shorting trace must be cut before installing the resistor. 3. R27 must be installed and J22 must be open if using J21. Test Points For GPIO (general purpose I/O) testing or monitoring, numerous test points are provided. The test points are labeled according to the associated I/O pin location, for example TP_A21. These test points have been arranged in grids that have grounds and VCCIOs placed nearby to allow for easy prototyping. Please refer the schematics at the end of this document for more information. Note that the test points for J21 and N21 have locations for zero ohm resistors (R115 and R117) to allow isolation of the test points from the oscillator clock. By default these resistors are not installed on the board. Switches Switch 1 (SW1) on the top edge of the board is an eight-switch block that is part of the prototyping area. A switch in the down position produces a low (logic 0), while the up position produces a high (logic 1). All SW1 signals go to bank 1. 18 LatticeECP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Table 38. SW1 Connections Switch Pin SW1-1 C12 SW1-2 B12 SW1-3 A11 SW1-4 A12 SW1-5 D12 SW1-6 E12 SW1-7 D13 SW1-8 E13 SW2 is a momentary switch that, when pressed, forces the FPGA to start a configuration cycle. SW3 is a momentary switch that the user can define for any purpose, such as a global reset. SW3 is wired to I/O E18 (bank 1) and applies a low logic level (0) when pressed. LEDs Eight user-definable LEDs are provided on the top of the board under SW1. These LEDs are each wired to a separate GPIO on bank 1 as defined in the Table 39. The current limiting resistors associated with these LEDs are wired to 3.3V, but it is safe to drive these signals with any FPGA I/O voltage. The LED will light when its associated I/O pin is driven low. Table 39. LED Connections LED Pin D1 B14 D2 A14 D3 D14 D4 C13 D5 E14 D6 F14 D7 A13 D8 B13 There are also three LEDs associated with the dedicated programming pins. Table 40. Programming LEDs LED Pin Color D12 PROGRAMN Yellow D11 INITN Red D10 DONE Green Function On when signal is low On when initializing On when configuration is complete Note: During JTAG programming, the state of the DONE LED has no meaning. This is because the DONE pin, which drives the LED, is being controlled by the pin’s BSCAN cell. See Lattice technical note number TN1108, LatticeECP2 sysCONFIG Usage Guide, for more information on the dedicated programming pins. Seven-Segment Display This board contains a seven-segment display, with decimal point, at U2. The segments are wired to GPIO as defined in Table 41. A low on the pin will turn on the associated segment. 19 LatticeECP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Table 41. Seven-Segment Display Connections Segment Pin A A15 B A17 C C15 D E15 E F15 F B15 G A16 DP D15 Figure 4. Seven-Segment Display A F B G E C DP D LCD Connector The LCD Connector has 18 pins, but only 16 are required for simple LCD panels. If using an OPTREX 51505 or equivalent, use pins 1-16, if using a LUMEX LCM-S02002DSR or equivalent, use pins 3-18. Two potentiometers are provided for LCD control. R34 adjusts the backlight and R35 adjusts the contrast. Power for the LCD panel is provided by the 3.3V to 5V converter at U7. 20 LatticeECP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Table 42. LCD Connector J42 Signal FPGA Pin 1 Anode (R34) — 2 Cathode (GND) — 3 VSS (GND) — 4 VDD (5V) — 5 VO (R35) — 6 RS D16 7 R/W A20 8 E E16 9 DB0 A18 10 DB1 C17 11 DB2 B18 12 DB3 C16 13 DB4 G16 14 DB5 B17 15 DB6 G15 16 DB7 B16 17 Anode (R34) — 18 Cathode (GND) — Compact Flash The connector at J12 supports Type 1 and Type 2 Compact Flash cards. This connector supports PC Card Memory Mode, PC Card I/O Mode, and True IDE Mode. Ultra DMA is not supported. Table 43. Compact Flash Connector Signal J12 FPGA Pin J12 Signal GND 1 — D03 2 B10 B11 26 CD1 A9 27 D11 D04 3 D05 4 A10 C10 28 D12 C11 F11 29 D13 D06 5 E11 A7 30 D14 D07 6 A8 B9 31 D15 CE1 7 B8 A6 32 CE2 A10 8 B7 D8 33 VS1 OE 9 C8 E10 34 IORD A09 10 D10 C6 35 IOWR A08 11 C7 B5 36 WE A07 12 B6 D9 37 READY 3.3V 13 - — 38 3.3V A06 14 F10 E9 39 CSEL A05 15 F9 A4 40 VS2 A04 16 A5 A2 41 RESET A03 17 A3 E8 42 WAIT A02 18 G8 B3 43 INPACK A01 19 C3 D7 44 REG 21 LatticeECP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Table 43. Compact Flash Connector (Continued) Signal J12 A00 20 J12 Signal F8 D00 D01 FPGA Pin F7 45 BVD2 21 E7 D6 46 BVD1 22 D5 H7 47 D08 D02 23 D4 B1 48 D09 WP 24 B2 C4 49 D10 CD2 25 J7 — 50 GND RS-232 The DB9 connector at J2 provides a standard DCE RS-232 connection to the FPGA. There are two jumpers, J1 and J3, which allow use of a straight-wired cable or a null modem cable. Table 44. RS-232 Connector to FPGA Pins J1 J3 1 to 2 1 to 2 Use with a straight-wired cable. Function 2 to 3 2 to 3 Use with a null modem cable (wires 2 and 3 swapped). Default X Table 45. RS-232 Connector to FPGA Pins FPGA Pin RS-232 Signal C1 CTS D1 RTS C2 Transmit Data (to the cable)1 D3 Receive Data (from the cable)1 1. Wired to TD or RD depending on J1 and J3 Configuring/Programming the Board Requirements • PC with Lattice Semiconductor’s ispVM System version 16.0 (or later) programming software, installed with appropriate drivers (USB driver for USB Cable, Windows NT/2000/XP parallel port driver for ispDOWNLOAD Cable). Note: An option to install these drivers is included as part of the ispVM System setup. The ispVM System software can be download from the Lattice web site at: latticesemi.com/ispvm. • Any ispDOWNLOAD or Lattice USB Cable (pDS4102-DL2x, HW7265-DL3x, HW-USB-2x, etc.). For a complete discussion of the LatticeECP2’s configuration and programming options, refer to Lattice technical note number TN1108, LatticeECP2 sysCONFIG Usage Guide. SRAM Configuration The LatticeECP2 SRAM can be configured easily via the JTAG port. The LatticeECP2 device is SRAM-based, so it must remain powered to retain its configuration when programming just the SRAM. To program the SRAM, perform the following procedure: 1. Check that J7 and J8 are properly set (see Table 6 and Table 7), and that J10 and J11 are open. 2. Connect the ispDOWNLOAD cable to the JTAG header at J4. When using a 1x8 connector on the download cable, connect to the 1x10 header by justifying the alignment to pin 1 (pin 1 on the cable to pin 1 on the header, pin 1 is Vcc). 22 LatticeECP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWNLOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeECP2 FPGA device and render the board inoperable. 3. Connect the LatticeECP2 Evaluation Board to an external 5V supply. 4. Start the ispVM System software. 5. Press the SCAN button located on the toolbar. The LatticeECP2 device should be automatically detected. The resulting screen should be similar to Figure 5. Figure 5. ispVM System Interface 6. Double-click the device to open the device information dialog, as shown in Figure 6. In the device information dialog, click the Browse button located under Data File. Locate the desired bitstream file (.bit). Click OK to both dialog boxes. 23 LatticeECP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Figure 6. Device Information Dialog 7. Click the green GO button on the toolbar; this will begin the download process into the LatticeECP2. 8. Upon successful download, the LatticeECP2 will be operational. SPI Flash Download For non-volatile storage of configuration data, the LatticeECP2 device features an interface compatible with lowcost SPI Serial Flash. ispVM System has the ability to program the SPI Serial Flash through JTAG. After the SPI Serial Flash is programmed the LatticeECP2 can configure automatically from the configuration data stored in the Flash. The following steps describe the procedure for programming the SPI Serial Flash: 1. Install all three jumpers at J43, and the jumper at J44. This enables SPI mode by setting the CFG pins of the LatticeECP2, and it enables fast SPI reads. Check that J7 and J8 are properly set (see Table 6 and Table 7), and that J10 and J11 are open. 2. Connect the download cable to J4. When using a 1x8 connector on the download cable, connect to the 1x10 header by justifying the alignment to pin 1 (pin 1 on the cable to pin 1 on the header, pin 1 is Vcc). Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWNLOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeECP2 FPGA device and render the board inoperable. 3. Connect the evaluation board to an external 5V supply 4. Start the ispVM System software. 24 LatticeECP2 Standard Evaluation Board User’s Guide Lattice Semiconductor 5. Press the SCAN button located on the toolbar. The LatticeECP2 device should be automatically detected. The resulting screen should be similar to Figure 5. 6. Double-click the device to open the device information dialog as shown in Figure 6. In the Device Options dropdown box, select SPI Flash Programming; you should see a window similar to Figure 7. Select the Flash device that is on your board and then browse to the desired bitstream file (.bit). Click OK in both dialog boxes. 7. Click on the green GO button on the ispVM toolbar to program the SPI Serial Flash. 8. Press and release SW2 (Program) on the board to transfer the configuration data from the SPI Serial Flash to the LatticeECP2. The LatticeECP2 should now be running the new code. Figure 7. SPI Serial Flash Dialog Box Ordering Information Ordering Part Number Description LatticeECP2 Evaluation Board - Standard LFE2-50E-L-EV ispLEVER Base with LatticeECP2 50E Standard Development Kit LS-E2-L-BASE-PC-N Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: [email protected] Internet: www.latticesemi.com 25 China RoHS EnvironmentFriendly Use Period (EFUP) 10 LatticeECP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Revision History Date Version May 2006 01.0 Initial release. Change Summary March 2007 01.1 Added Ordering Information section. April 2007 01.2 Added important information for proper connection of ispDOWNLOAD (Programming) Cables. May 2007 01.3 Replaced two instances of “U3-J21” with “LatticeECP2 pin J21” on page 3. © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 26 27 A B C D Prototyping Single Ended SI Testing 5 (Page 6) JTAG for FPGA Differential SI Testing (Page 5) Area 5 4 Bank 5 Bank 4 FPGA Bank 8 Bank 3 Bank 2 Bank 1 3 (Page 4) SPI Flash sysCONFIG Area 1 (Page 6) (Page 3) (Page 9) Power Supply Prototyping 2 2 Document Number <Doc> Sheet 1 1 ECP2 Standard -- Block Diagram of 8 B Rev Lattice Semiconductor Corporation Date: Size A Title LCD and Compact Flash Connectors 64 Bit PCI, PCI-X JTAG Bank 6 Bank 7 3 (Page 2) Bank 0 RS-232 LEDs Seven Seg 4 A B C D Lattice Semiconductor LatticeECP2 Standard Evaluation Board User’s Guide Appendix A. Schematics Figure 8. Block Diagram A B C41 0.1uF C40 0.1uF CF_D03 CF_D04 CF_D05 CF_D06 CF_D07 CF_CE1 CF_A10 CF_OE CF_A09 CF_A08 CF_A07 CF_A06 CF_A05 CF_A04 CF_A03 CF_A02 CF_A01 CF_A00 CF_D00 CF_D01 CF_D02 CF_WP CF_CD2 CF11 CF12 CF13 CF14 CF15 CF16 CF17 CF18 CF19 CF20 CF21 CF22 CF42 R50 100K CF0 CF1 CF2 CF3 CF4 CF5 CF6 CF7 CF8 CF9 CF10 CF[45..0] R49 100K JBLOCK JBLOCK 5 Traces from the ECP2 to the CF connector must be less than 6 inches Ultra DMA is not supported VCC_3.3V [8] JB1 JB2 CF_BVD1 C NorComp 190-009-262-001 or Equiv. 1 to 2 for straight wired cable (default) 2 to 3 for null cable (wires 2 and 3 swapped) J3 J2 1 DCD 1 2 DSR 6 3 RD 2 RTS 7 TD 3 CTS 8 DTR 4 RI J1 9 SGND 5 1 2 DB9 3 CF_BVD2 DCE R57 100K 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 CF36 R53 47K VCC R2OUT R1OUT T2IN T1IN C2- C2+ C1- C1+ R48 47K CF21 R56 47K MAX3232 CF39 GND R2IN R1IN T2OUT T1OUT V- RS-232 Compact_Flash_Connector GND CD1 D03 D11 D04 D12 D05 D13 D06 D14 D07 D15 CE1/CE1/CS0 CE2/CE2/CS1 A10 VS1 OE/OE/ATASEL IORD A09 IOWR A08 WE A07 READY/IREQ/INTRQ VCC VCC A06 CSEL A05 VS2 A04 RESET A03 WAIT/WAIT/IORDY A02 INPACK/INPACK/DMARQ A01 REG/REG/DMACK A00 BVD2/SPKR/DASP D00 BVD1/STSCHG/PDIAG D01 D08 D02 D09 WP/IOIS16/IOCS16 D10 CD2 GND PC Card Memory Mode/ PC Card I/O Mode/ True IDE Mode J12 CF30 R55 100K 15 8 13 7 14 6 V+ U1 1 R54 47K 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CF34 16 9 12 10 11 5 4 3 Compact Flash Connector CF41 C34 0.1uF CC0603 CF_VS1 2 CF_INPACK C33 CF_WP 0.1uF CC0603 CF_READY RS-232 VCC_3.3V 4 CF35 CF36 CF37 CF38 CF39 CF40 CF41 CF42 CF43 CF44 CF45 CF23 CF24 CF25 CF26 CF27 CF28 CF29 CF30 CF31 CF32 CF33 CF34 CF22 HEADER 1 1 GND16 CF_CSEL CF_VS2 CF_RESET CF_WAIT CF_INPACK CF_REG CF_BVD2 CF_BVD1 CF_D08 CF_D09 CF_D10 CF_CD1 CF_D11 CF_D12 CF_D13 CF_D14 CF_D15 CF_CE2 CF_VS1 CF_IORD CF_IOWR CF_WE CF_READY CF23 R47 100K VCC_3.3V C37 0.1uF CC0603 C38 0.1uF CC0603 R58 100K CF38 4 C36 0.1uF CC0603 CF_CD1 F7 E7 CF41 CF_BVD2 CF18 CF_D00 CF35 CF_CSEL CF12 CF_A05 B5 B6 B9 B8 A7 A8 F11 E11 CF28 CF_D15 CF5 CF_CE1 CF27 CF_D14 CF4 CF_D07 CF26 CF_D13 CF3 CF_D06 + B11 B10 CF23 CF_CD1 CF0 CF_D03 C43 10uF SizeB G9 G10 H8 H9 A9 A10 CF24 CF_D11 CF1 CF_D04 C10 C11 A6 B7 CF29 CF_CE2 CF6 CF_A10 CF25 CF_D12 CF2 CF_D05 D8 C8 CF30 CF_VS1 CF7 CF_OE CF31 CF_IORD E10 CF8 CF_A09 D10 CF32 CF_IOWR C6 CF9 CF_A08 C7 CF33 CF_WE CF10 CF_A07 CF34 CF_READY D9 CF11 CF_A06 F10 A4 A5 E9 F9 CF36 CF_VS2 CF13 CF_A04 CF37 CF_RESET A2 CF14 CF_A03 A3 CF38 CF_WAIT E8 CF15 CF_A02 G8 CF39 CF_INPACKB3 CF16 CF_A01 C3 D7 F8 D6 D5 CF42 CF_BVD1 CF19 CF_D01 CF40 CF_REG CF17 CF_A00 C4 D4 CF45 CF_D10 CF20 CF_D02 B1 B2 H7 J7 CF43 CF_D08 CF22 CF_CD2 CF44 CF_D09 CF21 CF_WP C2 D3 C1 D1 RS232_OUTDAT RS232_INDAT RS232_CTS RS232_RTS C103 0.1uF CC0402 C48 0.1uF CC0402 ECP2-12/22/35/50-fpBGA484 VCCO0 VCCO0 VCCO0 VCCO0 3 VCC_3.3V BANK1 C53 0.1uF CC0402 VCCO1 VCCO1 VCCO1 VCCO1 VREF1_1/PT55/64/73/82A VREF2_1/PT55/64/73/82B PT54/63/72/81A PT54/63/72/81B PT53/62/71/80A PT53/62/71/80B PT52/61/70/79A PT52/61/70/79B PT51/60/69/78A PT51/60/69/78B PT50/59/68/77A PT50/59/68/77B PT49/58/67/76A PT49/58/67/76B PT48/57/66/75A PT48/57/66/75B PT47/56/65/74A PT47/56/65/74B PT46/55/55/64A PT46/55/55/64B PT45/54/54/63A PT45/54/54/63B PT44/53/53/62A PT44/53/53/62B PT43/52/52/61A PT43/52/52/61B PT42/51/51/60A PT42/51/51/60B PT40/49/49/58A PT40/49/49/58B PT39/48/48/57A PT39/48/48/57B PT37/46/46/55A PT37/46/46/55B PT36/45/45/54A PT36/45/45/54B PT35/44/44/53A PT35/44/44/53B PT34/43/43/52A PT34/43/43/52B PT33/42/42/51A PT33/42/42/51B PT31/40/40/49A PT31/40/40/49B PCLKT1_0/PT30/39/39/48A PCLKC1_0/PT30/39/39/48B (1 of 6) PT28/37/37/46A/PCLKT0_0 PT28/37/37/46B/PCLKC0_0 Pad Name = PT{12/22/35/50} PT27/36/36/45A PT27/36/36/45B PT26/35/35/44A PT26/35/35/44B PT25/34/34/43A PT25/34/34/43B PT24/33/33/42A PT24/33/33/42B PT23/32/32/41A PT23/32/32/41B PT21/30/30/39A PT21/30/30/39B PT20/29/29/38A PT20/29/29/38B PT18/27/27/36A PT18/27/27/36B PT17/26/26/35A PT17/26/26/35B PT16/25/25/34A PT16/25/25/34B PT15/24/24/33A PT15/24/24/33B PT14/23/23/32A PT14/23/23/32B PT13/22/22/31A PT13/22/22/31B PT12/21/21/30A PT12/21/21/30B PT11/20/20/29A PT11/20/20/29B PT10/10/10/10A PT10/10/10/10B PT9/9/9/9A PT9/9/9/9B PT8/8/8/8A PT8/8/8/8B PT7/7/7/7A PT7/7/7/7B PT6/6/6/6A PT6/6/6/6B PT5/5/5/5A PT5/5/5/5B PT4/4/4/4A PT4/4/4/4B PT3/3/3/3A PT3/3/3/3B PT2/2/2/2A/VREF1_0 PT2/2/2/2B/VREF2_0 BANK0 U3A 3 LCD_DB2 LCD_DB0 + C49 10uF SizeB LCD_RW TP_B22 TP_B21 TP_C19 TP_C20 TP_D18 TP_A19 TP_B20 TP_C18 TP_D17 LCD0 TP_A21 LCD2 LCD1 LCD4 LCD3 LCD6 LCD5 LCD_E LCD_RS LCD_DB6 LCD_DB4 LCD8 LCD7 LCD_DB3 LCD_DB1 LCD10 LCD9 SSEG_G SSEG_B SSEG_DP SSEG_C SSEG_E SSEG_D SSEG_A SSEG_F LED1 LED0 LED3 LED2 LED5 LED4 LED7 LED6 SW1 SW0 SW3 SW2 SW5 SW4 SW7 SW6 LCD_DB7 LCD_DB5 C83 0.1uF CC0402 G11 G12 G13 G14 B22 B21 C19 C20 E18 D18 A19 B20 C18 D17 A20 A21 B18 A18 G15 G16 E16 D16 C16 C17 B16 B17 A16 A17 D15 C15 F15 E15 A15 B15 A14 B14 C13 D14 F14 E14 B13 A13 D13 E13 D12 E12 A11 A12 C12 B12 R96 10K R92 10K 2 470 470 470 470 470 R35 20K 2 R34 100 R108 470 R104 R112 R111 R110 R109 C102 1uF CC0603 R114 10K Contrast VCC_3.3V LED0 LED1 LED2 LED3 LED4 LED5 R102 470 R103 470 2 R64 10K U2 cathode A cathode F annode1 NC1 NC2 NC3 cathode E cathode D cathode DP cathode C cathode G NC4 cathode B annode2 470 470 470 470 470 470 470 470 R63 10K A2 B2 SW3 A1 B1 D9 LED_Yellow 16 15 14 13 12 11 10 9 C93 0.1uF CC0603 1 3 5 7 9 11 13 15 17 SW DIP-8 861milX425mil SW1 CATHODE VDD RS E DB1 DB3 DB5 DB7 CATHODE LCD_Connector ANODE VSS VO R/W DB0 DB2 DB4 DB6 ANODE J42 2 4 6 8 10 12 14 16 18 LCD Connector LCD_RS LCD_E LCD_DB1 LCD_DB3 LCD_DB5 LCD_DB7 D(Pin 8) G(Pin 11) A(Pin 1) HEADER 1 1 GND17 1 A2 A1 [8] LCD[10..0] LCD5 LCD6 LCD7 LCD8 LCD9 LCD10 C116 0.1uF VCC_5V DP(Pin 9) Document Number <Doc> 1 Sheet 2 of 8 B Rev ECP2 Standard -- LCD, CF, RS-232, LEDs Lattice Semiconductor Corporation Date: Size C Title B2 B1 SW PUSHBUTTON HEADER 1 1 GND18 LUMEX or Equiv. use pins 4-18 OPTREX 51505 or Equiv. use pins 1-16 1 2 3 4 5 6 7 8 VCC_3.3V User Defined LCD0 LCD1 LCD2 LCD3 LCD4 LCD_RW LCD_DB0 LCD_DB2 LCD_DB4 LCD_DB6 Seven Segment LED 738milX386mil 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ANODE R113 470 R65 R66 R68 R70 R93 R95 VCC_3.3V D1 D2 D3 D4 D5 D6 R97 D7 D8 R67 10K R99 R69 10K LED6 LED_Green R94 10K LED7 LED[7:0] SW[7:0] SW7 SW6 SW5 SW4 SW3 SW2 SW1 SW0 R98 10K Backlight 2 F(Pin 2) E(Pin 7) D CF_VS2 3 B(Pin 12) C(Pin 10) 5 CF_CD2 3 1 28 1 A B C D Lattice Semiconductor LatticeECP2 Standard Evaluation Board User’s Guide Figure 9. LCD, CF, RS-232, LEDs CF_WAIT 29 A B C D [8] VCC_3.3V VCC_ADJ VCC_1.2V VCCIO3 GND VCC_3.3V VCC_ADJ VCC_1.2V 5 + J37 2 4 6 C110 10uF SizeB JB5 TP_VCC1 TP_VCC2 TP_VCC3 TP_VCC4 TP_VCC5 TP_VCC6 C77 0.1uF CC0402 C74 0.1uF CC0402 [8] R119 10 C96 0.01uF CC0603 H16 H17 TP_H16 TP_H17 VCC_1.2V C105 0.1uF CC0603 4 TP_L17 TP_M18 J16 H14 H15 J15 K16 L20 L19 L17 M18 TP_L20 TP_L19 VCCIO2 K17 L18 TP_K17 TP_L18 K19 K18 H18 H20 TP_H18 TP_H20 F22 G22 E22 F21 TP_E22 TP_F21 TP_K19 TP_K18 E21 D22 TP_E21 TP_D22 TP_F22 TP_G22 F20 G20 TP_F20 TP_G20 J18 J17 G19 H19 TP_G19 TP_H19 J19 K20 F19 G17 TP_F19 TP_G17 TP_J18 TP_J17 D20 E20 TP_D20 TP_E20 TP_J19 TP_K20 F16 F18 TP_F16 TP_F18 G21 H21 C22 C21 TP_C22 TP_C21 TP_G21 TP_H21 E19 D19 TP_E19 TP_D19 = Unconnected, Plated Holes Prototype Area Map (VCCIO2) JBLOCK HEADER 3X2 1 3 5 A B C D E F G H J K L M N P R TP_GND1 TP_GND2 TP_GND3 TP_GND4 TP_GND5 TP_GND6 VCCIO2 16 17 18 19 20 21 22 4 BANK2 U3B DQS Group ECP2-12/22/35/50-fpBGA484 PLLVCC VCCO2 VCCO2 VCCO2 VCCO2 Pad Name = PR{12/22/35/50} PR13/19/25/44A/PCLKT2_0 PR13/19/25/44B/PCLKC2_0 PR12/18/24/43AH PR12/18/24/43BH PR11/17/23/42A PR11/17/23/42B PR10/16/22/41AH/RDQS PR10/16/22/41BH PR9/15/21/40A PR9/15/21/40B PR8/14/20/39AH PR8/14/20/39BH PR7/13/19/38A PR7/13/19/38B PR6/12/18/37AH PR6/12/18/37BH PRNC/NC/NC/26A/SPLLT_FB PRNC/NC/NC/26B/SPLLC_FB BANK3 3 C98 0.01uF CC0603 N18 N17 L16 M16 N16 P16 R21 R22 P19 P18 P22 R20 N21 P21 N20 N22 C97 0.1uF CC0603 TP_M19 TP_N19 R116 10 (VCCIO3) TP_VCC7 TP_VCC8 TP_VCC9 TP_R21 TP_R22 TP_P19 TP_P18 TP_P22 TP_R20 TP_N21 TP_P21 TP_N20 TP_N22 TP_M21 TP_M22 TP_K22 TP_L22 M19 N19 M21 M22 TP_H22 TP_J22 K22 L22 TP_J21 TP_K21 TP_L21 TP_M20 R117 0 R115 0 H22 J22 J21 K21 3 L21 M20 C84 5.6nF CC0603 PLLVCC PLLCAP VCCO3 VCCO3 VCCO3 VCCO3 PRnnxH = True LVDS PR23/33/47/66A PR23/33/47/66B PR22/32/46/65AH PR22/32/46/65BH GPLLT_FB/PR21/31/45/64A GPLLC_FB/PR21/31/45/64B GPLLT_IN/PR20/30/44/63AH GPLLC_IN/PR20/30/44/63BH GDLLT_FB/PR18/28/42/61A GDLLC_FB/PR18/28/42/61B GDLLT_IN/PR17/27/41/60AH GDLLC_IN/PR17/27/41/60BH PRNC/26/40/59A PRNC/26/40/59B PRNC/24/30/49A PRNC/24/30/49B PRNC/23/29/48AH PRNC/23/29/48BH VREF1_3/PR16/22/28/47A VREF2_3/PR16/22/28/47B PCLKT3_0/PR15/21/27/46AH PCLKC3_0/PR15/21/27/46BH (2 of 6) PRNC/NC/NC/25A/SPLLT_IN PRNC/NC/NC/25B/SPLLC_IN PRNC/11/17/19A PRNC/11/17/19B PRNC/10/16/18AH PRNC/10/16/18BH PRNC/9/15/17A PRNC/9/15/17B PRNC/8/14/16AH/RDQS PRNC/8/14/16BH PR5/7/13/15A PR5/7/13/15B PR4/6/12/14AH PR4/6/12/14BH PR3/5/11/13A PR3/5/11/13B PRNC/4/10/12AH PRNC/4/10/12BH PR2/2/2/2AH/VREF1_2 PR2/2/2/2BH/VREF2_2 DQS Group 5 VCC_1.2V [8] 2 C115 0.1uF CC0402 2 C66 0.1uF CC0402 C104 0.1uF CC0603 + DIP16 OSC_PCLK OSC_PLLCLK Vcc OSC14A GND CLK NC Y4 8 14 (33.33 MHz OSC Installed) Oscillator Socket 16 15 14 13 12 11 10 9 VCC_3.3V C101 10uF SizeB VCC_3.3V [8] (Default) 2 1 4 pin Osc. To PLL To PCLK Oscillator position relative to the socket 5 1 Default is a 14 pin oscillator aligned pin 1 to pin 1 14 pin Osc. Document Number <Doc> 1 Sheet 3 of ECP2 Standard -- Prototyping Area 8 Lattice Semiconductor Corporation Date: Size C Title 33.33 MHz Oscillator 7 1 1 2 3 4 5 6 7 8 Y1 1 B Rev A B C D Lattice Semiconductor LatticeECP2 Standard Evaluation Board User’s Guide Figure 10. Prototyping Area A B 1 2 3 HEADER 2 J23 1 2 C39 0.01uF CC0603 PCI_PRSNT1_N R51 5.6K Load for Master Only R62 5.6K 5 PCI_PRSNT2_N Load for Master Only These 0.01 µF capacitors must be located within 0.25 inches of their PCI edge connector pin. C47 0.01uF CC0603 1-2 = Master N/C = Target 1-2 = Master 2-3 = Target N/C = Target J9 Load for Master Only VCC_3.3V VCC_3.3V [8] 1 2 R61 5.6K HEADER 2 J13 R1 5.6K C42 0.1uF CC0603 1-2 = Target N/C = Master Load for Master Only R59 5.6K R60 5.6K C1 0.1uF CC0603 + C9 10uF SizeB Y4 AA3 Y6 Y7 PCI_AD28 PCI_AD24 Y8 AA8 W9 V9 PCI_PAR C99 0.1uF CC0402 PCI_CBE6_N C61 0.1uF CC0402 AB12 AA12 AB13 AB14 PCI_AD5 PCI_AD3 PCI_AD1 R9 T9 T10 T11 Y11 W11 PCI_AD7 PCI_AD15 PCI_AD8 AB11 PCI_AD10 AA11 U10 U11 Y10 PCI_AD14 AA10 PCI_CBE1_N PCI_FRAME_N PCI_DEVSEL_N AB8 AA9 AB9 PCI_AD12 AB10 PCI_IRDY_N PCI_SERR_N W10 V10 PCI_AD20 PCI_AD16 PCI_AD18 U8 U9 AA7 AB7 W7 W8 PCI_AD17 AB6 AA6 PCI_AD19 PCI_AD21 AA5 Y5 AB5 AB4 PCI_AD26 PCI_AD22 PCI_AD23 PCI_AD25 PCI_AD29 PCI_STOP_N PCI_TRDY_N PCIX_ECC5 J48 PCI/PCI-X 64bit EDGE CON Bottom TP13 C HEADER 3X2 PCI_PERR_N PCIX_ECC3 PCI_INTC_N PCIX_ECC2 PCI_INTD_N TP9 PCI_INTA_N PCI_RST_N 2 4 6 PCI_GNT_N J19 PCI_CLK 1 3 5 PCI_REQ_N PCI_INTB_N PCI_INT_N PCI_IDSEL PCI_CBE2_N PCI_CBE3_N PCI_GNT_N PCI_RST_N W5 W6 AB3 AB2 PCI_AD27 PCI_AD31 PCI_AD30 PCI_AD31 PCI_AD29 D Load for Master Only PCI_AD30 PCI_AD28 PCI_AD26 PCI_CLK PCI_AD27 PCI_AD25 PCI_TRSTN PCIX_ECC3 PCI_IDSEL PCI_CBE3_N PCI_INTA_N PCI_INTC_N W4 W3 3 ECP2-12/22/35/50-fpBGA484 VCCO5 VCCO5 VCCO5 VCCO5 [5] BANK4 VCCO4 VCCO4 VCCO4 VCCO4 VREF2_4/PB55/64/73/82A VREF1_4/PB55/64/73/82B PB54/63/72/81A PB54/63/72/81B PB53/62/71/80A PB53/62/71/80B PB52/61/70/79A PB52/61/70/79B BDQS/PB51/60/69/78A PB51/60/69/78B PB50/59/68/77A PB50/59/68/77B PB49/58/67/76A PB49/58/67/76B PB48/57/66/75A PB48/57/66/75B PB46/55/55/64A PB46/55/55/64B PB45/54/54/63A PB45/54/54/63B PB44/53/53/62A PB44/53/53/62B PB43/52/52/61A PB43/52/52/61B BDQS/PB42/51/51/60A PB42/51/51/60B PB41/50/50/59A PB41/50/50/59B PB40/49/49/58A PB40/49/49/58B PB39/48/48/57A PB39/48/48/57B PB37/46/46/55A PB37/46/46/55B PB36/45/45/54A PB36/45/45/54B PB35/44/44/53A PB35/44/44/53B PB34/43/43/52A PB34/43/43/52B BDQS/PB33/42/42/51A PB33/42/42/51B PB32/41/41/50A PB32/41/41/50B PCLKT4_0/PB31/40/40/49A PCLKC4_0/PB31/40/40/49B (3 of 6) Pad Name = PB{12/22/35/50} PB26/35/35/44A/PCLKT5_0 PB26/35/35/44B/PCLKC5_0 PB25/34/34/43A PB25/34/34/43B PB24/33/33/42A/BDQS PB24/33/33/42B PB23/32/32/41A PB23/32/32/41B PB22/31/31/40A PB22/31/31/40B PB21/30/30/39A PB21/30/30/39B PB20/29/29/38A PB20/29/29/38B PB18/27/27/36A PB18/27/27/36B PB17/26/26/35A PB17/26/26/35B PB16/25/25/34A PB16/25/25/34B PB15/24/24/33A/BDQS PB15/24/24/33B PB14/23/23/32A PB14/23/23/32B PB13/22/22/31A PB13/22/22/31B PB12/21/21/30A PB12/21/21/30B PB11/20/20/29A PB11/20/20/29B PB9/9/9/9A PB9/9/9/9B PB8/8/8/8A PB8/8/8/8B PB7/7/7/7A PB7/7/7/7B PB6/6/6/6A/BDQS PB6/6/6/6B PB5/5/5/5A PB5/5/5/5B PB4/4/4/4A PB4/4/4/4B PB3/3/3/3A PB3/3/3/3B PB2/2/2/2A/VREF2_5 PB2/2/2/2B/VREF1_5 PCI_FRAME_N PCIX_ECC5 PCIX_ECC4 PCI_AD24 BANK5 PCI_TRDY_N Y3 Y2 PCI_AD23 TP10 PCI_TCK PCI_PAR U3C PCI_CBE2_N PCI_TMS PCI_TDI TP16 PCI_AD13 PCI_AD11 PCI_REQ_N PCIX_ECC2 PCI_IRDY_N TP11 TP12 TP17 PCI_AD18 PCI_AD16 PCI_AD17 1 2 3 4 5 6 7 8 9 10 11 PCI_TDO PCI_STOP_N PCI_DEVSEL_N PCI_PCIXCAP 4 PCI_AD21 PCI_AD19 5 TP15 TRST# +12V TMS TDI +5V_5 INTA# INTC# +5V_8 Reserved_9 +VIO_10 Reserved_11 PCI_AD22 PCI_AD20 DQS Group DQS Group PCI_SMBCLK PCI_SMBDAT PCI_PERR_N PCI_AD44 PCI_AD48 PCI_AD40 PCI_AD38 Y19 Y20 R14 T12 T13 T14 T15 T16 U18 V18 Y21 Y22 4 J14 PCI/PCI-X 64bit EDGE CON Top 3 PCI_AD54 PCI_AD32 PCI_AD34 PCI_AD33 PCI_AD35 PCI_AD46 PCI_AD42 PCI_AD56 PCI_AD36 Y18 Y17 W17 W18 PCI_AD37 PCI_AD39 PCI_AD57 PCI_AD53 AA16 AA17 AA21 AA22 PCI_AD62 PCI_AD61 Y15 AA15 V16 V17 PCI_AD60 V14 W15 PCI_AD49 PCI_AD43 PCI_AD51 PCI_AD47 AB18 AB19 AA18 AA20 PCI_AD2 W13 W14 PCI_AD52 PCI_AD50 PCI_AD59 PCI_AD55 AB16 AB17 PCI_AD58 PCI_AD63 AB15 AA14 Y16 W16 PCI_AD6 PCI_AD0 PCI_AD45 PCI_AD41 PCI_AD4 AA13 Y13 U13 U14 U15 U16 PCI_AD11 PCI_AD9 Y12 W12 AB20 AB21 PCI_AD13 U12 V12 C92 0.1uF CC0402 PAR64 C107 0.1uF CC0603 C112 0.1uF CC0603 PCI_CBE5_N PCI_CBE7_N PCI_REQ64_N PCI_CBE4_N PCI_ACK64_N PCI_CBE0_N 2 C10 0.1uF CC0402 C108 0.1uF CC0603 C51 0.1uF CC0603 + C45 10uF SizeB C4 0.1uF CC0603 C100 0.1uF CC0603 PCI_AD36 PCI_AD34 DQS Group PCI_SERR_N PCI_CBE0_N PCI_GND_57 1 2 3 4 5 6 7 8 9 10 11 PCI_INTB_N PCI_INTD_N PCI_PRSNT1_N PCIX_ECC4 PCI_PRSNT2_N PCI_AD15 PCI_CBE1_N PCI_CBE7_N PCI_CBE5_N PAR64 PCI_CBE6_N PCI_CBE4_N PCI_AD9 -12V TCK Ground_3 TDO +5V_5 +5V_7 INTB# INTD# PRSNT1# Reserved_10 PRSNT2# PCI_AD14 PCI_AD60 PCI_AD58 [8] PCI_AD59 PCI_AD57 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 PCI_M66EN PCI_AD56 PCI_AD54 PCI_AD55 PCI_AD53 3.3VAUX RST# +VIO_16 GNT# Ground_18 PME# AD[30] +3.3V_21 AD[28] AD[26] Ground_24 AD[24] IDSEL +3.3V_27 AD[22] AD[20] Ground_30 AD[18] AD[16] +3.3V_33 FRAME# Ground_35 TRDY# Ground_37 STOP# +3.3V_39 Reserved_40 Reserved_41 Ground_42 PAR AD[15] +3.3V_45 AD[13] AD[11] Ground_48 AD[09] PCI_AD12 PCI_AD10 PCI_AD52 PCI_AD50 PCI_AD51 PCI_AD49 PCI_REQ64_N 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 PCI_AD48 PCI_AD46 PCI_AD47 PCI_AD45 PCI_AD2 PCI_AD0 Reserved_14 Ground_15 CLK Ground_17 REQ# +VIO_19 AD[31] AD[29] Ground_22 AD[27] AD[25] +3.3V_25 C/BE#[3] AD[23] Ground_28 AD[21] AD[19] +3.3V_31 AD[17] C/BE#[2] Ground_34 IRDY# +3.3V_36 DEVSEL# Ground_38 LOCK# PERR# +3.3V_41 SERR# +3.3V_43 C/BE#[1] AD[14] Ground_46 AD[12] AD[10] M66EN PCI_AD8 PCI_AD7 PCI_AD44 PCI_AD42 PCI_AD43 PCI_AD41 PCI_AD6 PCI_AD4 PCI_AD5 PCI_AD3 PCI_AD40 PCI_AD38 PCI_AD39 PCI_AD37 52 53 54 55 56 57 58 59 60 61 62 PCI_ACK64_N PCI_AD62 PCI_AD63 PCI_AD61 C/BE#[0] +3.3V_53 AD[06] AD[04] Ground_56 AD[02] AD[00] +VIO_59 REQ64# +5V_61 +5V_62 PCI_AD1 52 53 54 55 56 57 58 59 60 61 62 AD[08] AD[07] +3.3V_54 AD[05] AD[03] Ground_57 AD[01] +VIO_59 ACK64# +5V_61 +5V_62 2 C5 0.1uF CC0603 C11 0.1uF CC0603 PCI_AD[63:0] VCC_3.3V C3 0.1uF CC0603 C90 0.1uF CC0603 PCI_AD32 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 30 PCI_AD35 PCI_AD33 DQS Group Ground_63 C/BE[7]# CBE[5]#/AD[48] +VIO_66 PAR64/ECC[7] AD[62] Ground_69 AD[60] AD[58] Ground_72 AD[56] AD[54] +VIO_75 AD[52] AD[50] Ground_78 AD[48]/CBE[5]# AD[46] Ground_81 AD[44] AD[42] +VIO_84 AD[40] AD[38] Ground_87 AD[36] AD[34] Ground_90 AD[32] Reserved_92 Ground_93 Reserved_94 DQS Group 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 DQS Group Reserved_63 Ground_64 C/BE[6]# CBE[4]#/AD[49] Ground_67 AD[63] AD[61] +VIO_70 AD[59] AD[57] Ground_73 AD[55] AD[53] Ground_76 AD[51] AD[49]/CBE[4]# +VIO_79 AD[47] AD[45] Ground_82 AD[43] AD[41] Ground_85 AD[39] AD[37] +VIO_88 AD[35] AD[33] Ground_91 Reserved_92 Reserved_93 Ground_94 C46 0.01uF CC0603 + R106 5.6K TP8 TP14 Load for Master Only C114 0.1uF CC0603 C60 0.1uF CC0603 C7 10uF SizeB J38 R88 10K J24 Document Number <Doc> 1 Sheet 4 of ECP2 Standard -- 64 Bit PCI, PCI-X 8 B Rev 1-2 = 66MHz PCI-X N/C = 133 MHz PCI-X HEADER 2 1 2 These 0.01 µF capacitors must be located within 0.25 inches of their PCI edge connector pin. 1-2 = Master 2-3 = 33 MHz PCI N/C = 66 MHz PCI 1 2 3 Load for Master Only R107 5.6K C59 0.1uF CC0603 Load for Master Only C111 0.01uF CC0603 PCI_PCIXCAP + C58 0.1uF CC0603 R126 5.6K VCC_3.3V C52 0.1uF CC0603 C8 0.1uF CC0603 PCI_M66EN C109 0.1uF CC0603 C6 0.1uF CC0603 C12 10uF SizeB Lattice Semiconductor Corporation Date: Size C Title C50 0.1uF CC0603 C113 0.1uF CC0603 PCI Decoupling 1 A B C D Lattice Semiconductor LatticeECP2 Standard Evaluation Board User’s Guide Figure 11. 64-Bit PCI, PCI-X 31 A B C D RJ-45 J6A 1 2 3 4 5 6 7 8 SMA Connector SMA Connector J28 E F G H J TP_SI1 TP_SI0 TP_GSI1 TP_GSI0 3 TP_SI2 1 TP_SI4 TP_SI3 TP_GSI2 TP_SI5 TP_GSI5 TP_GSI3 TP_SI6 TP_GSI4 TP_SI7 TP_GSI6 1 TP_GSI7 2 AMP 6368150-1 Vertical Mount 2 3 4 5 2 3 4 5 1 5 5 R2 DNL R71 DNL R4 DNL R73 DNL R81 DNL VCCIO7 6 7 R3 DNL R72 DNL Diff pair, equal length, 50 ohms 4 R19 DNL R18 DNL Diff pair, R80 equal length, DNL 50 ohms Diff pair, equal length, 50 ohms Diff pair, equal length, 50 ohms R6 DNL R5 DNL R7 DNL R76 DNL R87 R20 DNL R82 DNL R21 DNL R83 DNL DNL DNL DNL DNL DNL R10 R11 R12 R13 R22 R23 [8] VCC_3.3V VCC_ADJ VCC_1.2V J17 2 4 6 VCC_1.2V SI0 SI1 SI2 SI3 SI4 SI5 SI6 SI7 R26 DNL JB11 JBLOCK HEADER 3X2 1 3 5 = Unconnected, Plated Holes [8] DNL DNL R9 DNL R8 Place resistor trio as close to the FPGA as possible Place resistor trio as close to the FPGA as possible Place resistor trio as close to the FPGA as possible Place resistor trio as close to the FPGA as possible Prototype Area Map R75 DNL R74 DNL DNL R78 R79 DNL R77 DNL DNL R17 R16 DNL R15 DNL R14 DNL DNL Diff pair, equal length, 50 ohms SI[7:0] 4 4 SI1 SI0 SI3 SI2 SI5 SI4 + R25 DNL SI7 SI6 R24 DNL E3 F3 F4 F5 TP_E3 TP_F3 TP_F4 TP_F5 H6 J6 H3 H2 H1 TP_H6 TP_J6 TP_H3 TP_H2 TP_H1 C55 0.01uF CC0603 G1 G2 TP_G1 TP_G2 C68 0.1uF CC0402 TP_GND14 TP_GND15 TP_VCC17 TP_VCC18 TP_VCC19 C69 0.1uF CC0402 K6 J8 K7 L7 M7 L2 L1 L4 L3 K2 K1 K3 K4 L6 L5 J2 J1 J4 J5 F1 F2 G3 G4 TP_F1 TP_F2 H4 H5 TP_H4 TP_H5 TP_G3 TP_G4 G6 G7 TP_G6 TP_G7 E2 E1 E4 E5 TP_E4 TP_E5 (VCCIO7) C54 0.1uF CC0603 R100 10 VCCIO7 C2 10uF SizeB Place resistor trio as close to the FPGA as possible BANK6 ECP2-12/22/35/50-fpBGA484 PLLVCC VCCO7 VCCO7 VCCO7 VCCO7 Pad Name = PL{12/22/35/50} PL13/19/25/44A/PCLKT7_0 PL13/19/25/44B/PCLKC7_0 PL12/18/24/43AH PL12/18/24/43BH PL11/17/23/42A PL11/17/23/42B PL10/16/22/41AH/LDQS PL10/16/22/41BH PL9/15/21/40A PL9/15/21/40B PL8/14/20/39AH PL8/14/20/39BH PL7/13/19/38A PL7/13/19/38B 3 PLLVCC PLLCAP VCCO6 VCCO6 VCCO6 VCCO6 PLnnxH = True LVDS PL31/45/59/78A PL31/45/59/78B PL30/44/58/77AH PL30/44/58/77BH PL29/43/57/76A PL29/43/57/76B LDQS/PL28/42/56/75AH PL28/42/56/75BH PL27/41/55/74A PL27/41/55/74B PL26/40/54/73AH PL26/40/54/73BH PL25/39/53/72A PL25/39/53/72B PL24/38/52/71AH PL24/38/52/71BH PL23/33/47/66A PL23/33/47/66B PL22/32/46/65AH PL22/32/46/65BH PLNC/NC/NC/26A/SPLLT_FB PLNC/NC/NC/26B/SPLLC_FB PL6/12/18/37A GPLLT_FB/PL21/31/45/64A GPLLC_FB/PL21/31/45/64B PLNC/NC/NC/25A/SPLLT_IN PLNC/NC/NC/25B/SPLLC_IN GDLLT_FB/PL18/28/42/61A GDLLC_FB/PL18/28/42/61B GDLLT_IN/PL17/27/41/60AH GDLLC_IN/PL17/27/41/60BH PLNC/26/40/59A PLNC/26/40/59B LDQS/PLNC/25/39/58AH PLNC/25/39/58BH PLNC/24/30/49A PLNC/24/30/49B PLNC/23/29/48AH PLNC/23/29/48BH VREF2_6/PL16/22/28/47A VREF1_6/PL16/22/28/47B PCLKT6_0/PL15/21/27/46AH PCLKC6_0/PL15/21/27/46BH GPLLT_IN/PL20/30/44/63AH GPLLC_IN/PL20/30/44/63BH (4 of 6) 3 PLNC/11/17/19A PLNC/11/17/19B PLNC/10/16/18AH PLNC/10/16/18BH PLNC/9/15/17A PLNC/9/15/17B PLNC/8/14/16AH/LDQS PLNC/8/14/16BH PL5/7/13/15A PL5/7/13/15B PL4/6/12/14AH PL4/6/12/14BH PL3/5/11/13A PL3/5/11/13B PLNC/4/10/12AH PLNC/4/10/12BH PL2/2/2/2/2AH/VREF2_7 PL2/2/2/2/2BH/VREF1_7 BANK7 U3D DQS Group 5 DQS Group C79 5.6nF CC0603 TP_N5 TP_P5 N5 P5 TP_U1 TP_U2 TP_V1 TP_V2 TP_R6 TP_T6 U1 U2 V1 V2 R6 T6 N6 P6 N7 P7 P8 R8 AA2 AA1 V4 V3 R7 T7 Y1 W1 C81 0.1uF CC0402 TP_GND10 TP_GND11 TP_GND12 TP_GND13 TP_VCC10 TP_VCC11 TP_VCC12 TP_VCC13 TP_VCC14 TP_VCC15 + C56 0.1uF CC0603 R101 10 C80 0.1uF CC0402 (VCCIO6) C57 0.01uF CC0603 VCCIO6 TP_AA2 TP_AA1 TP_V4 TP_V3 TP_R7 TP_T7 TP_Y1 TP_W1 TP_U3 TP_U4 TP_T5 TP_T3 T5 T3 U3 U4 TP_T1 TP_T2 T1 T2 R3 T4 R1 R2 P4 R4 TP_P4 TP_R4 TP_N3 TP_N4 N3 N4 P1 P2 TP_N1 TP_N2 TP_M2 TP_M1 M2 M1 N1 N2 TP_M3 TP_M4 M5 M6 M3 M4 C44 10uF SizeB 1 [4] [8] 3 2 2 1 3 5 JB12 3 D20 R85 R84 R86 DNL DNL DNL 1 DNL R91 DNL R30 DNL 3 [8] 2 DNL VCC_3.3V VCC_ADJ VCC_1.2V M N P R T U V W Y AA R90 R89 Place resistor trio as close to the FPGA as possible R29 R28 Place resistor trio as close to the FPGA as possible Diff pair, equal length, 50 ohms R27 J22 0 HEADER 2 1 2 VCCIO6 VCCIO6 6 7 SMA Connector SMA Connector J16 J15 SMA Connector SMA Connector J20 J21 SMA Connector SMA Connector J25 J26 2 3 4 5 2 3 4 5 2 3 4 5 2 3 4 5 2 3 4 5 2 3 4 5 = Unconnected, Plated Holes Prototype Area Map 1 1 1 1 1 1 Document Number <Doc> 1 Sheet ECP2 Standard -- SI Testing 5 of 8 Lattice Semiconductor Corporation 5 Diff pair, equal length, 50 ohms Diff pair, equal length, 50 ohms Date: Size C Title 4 1 50 ohm SMA Connectors Add jumper if using PCI or PCI-X Place pad for header pin 2 directly on the trace to avoid a stub. 1 DNL DNL Place resistor trio as close to the FPGA as possible BAS70-04 JBLOCK HEADER 3X2 2 4 6 J18 VCC_1.2V [8] PCI_CLK VCC_3.3V SOT-23 BAS70-04 2 2 J27 DQS Group GND DQS Group GND B Rev A B C D Lattice Semiconductor LatticeECP2 Standard Evaluation Board User’s Guide Figure 12. SI Testing 32 A B C D [8] C D N/C8 N/C7 N/C6 N/C5 VSS /W 16 15 14 13 12 11 10 9 JB7 J39 2 4 6 JBLOCK 5 HEADER 3X2 1 3 5 HEADER 1 1 GND20 Load one Flash, not both W25P32VSFIG /HOLD VCC N/C1 N/C2 N/C3 N/C4 /S Q VCC_3.3V VCC_ADJ VCC_1.2V 1 2 3 4 5 6 7 8 U5 SPI Serial Flash (Dual Footprint) C35 0.1uF CC0603 VCC_3.3V HEADER 10 1 2 3 4 5 6 7 8 9 10 1x10 JTAG Chain Input Header J4 JTAG 1 2 3 4 SPID0 W25P16VSSIG /S Q /W VSS 8 7 6 5 JBLOCK JB22 1 2 C106 0.1uF CC0603 HEADER 2 J44 10K R121 CCLK SISPI J7 VCC_BANK8 + C13 10uF SizeB C86 0.1uF CC0402 4 HEADER 10 J5 Jumper Normally Not Installed 1 2 3 4 5 6 7 8 9 10 HEADER 1 1 GND19 J10 HEADER 2 Jumper Normally Not Installed DI 3 DOUT J34 J33 3 1 3 1 R122 R123 10K 10K J31 J32 2 2 FPGA_D7 FPGA_D0 VCC_BANK8 JBLOCK JBLOCK 2 2 C62 0.1uF CC0402 3 1 CSON 2 2 HEADER 2 J35 HEADER 2 J36 FPGA_D0 FPGA_D1 FPGA_D2 FPGA_D3 FPGA_D4 FPGA_D5 FPGA_D6 FPGA_D7 DOUT CCLK FPGA_D7 FPGA_D6 FPGA_D5 FPGA_D4 FPGA_D3 FPGA_D2 FPGA_D1 FPGA_D0 CSN CS1N CCLK BUSY 3 VCCJ CFG2 CFG1 CFG0 DOUT/CSON/PR71B 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 J41 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 HEADER 17X2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 sysCONFIG Output sysCONFIG HEADER 17X2 J40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 ECP2-12/22/35/50-fpBGA484 VCCO8 VCCO8 PR77B/WRITEN R19 R18 WRITEN INITN PROGRAMN WRITEN CFG0 CFG1 CFG2 INITN PROGRAMN FPGA_D6 DONE 2 V20 PROGRAMN V21 DONE V22 INITN W22 W19 CFG2 V19 CFG1 W20 CFG0 DOUT WRITEN PR76A/D0(MSb)/SPIFASTN PR75B/D1 PR75A/D2 PR74B/D3 PR74A/D4 PR73B/D5 PR73A/D6 PR72B/D7(LSb)/SPID0 BUSY/SISPI/PR71A PR77A/CS1N PR76B/CSN CFG0 CFG1 CFG2 2 PROGRAMN CCLK DONE INITN R130 10K R129 10K R128 10K PROGRAMN DONE INITN CCLK TP_101 (5 of 6) VCC_3.3V PR72A/DI/CSSPIN TDO TDI TMS TCK VCCJ U3E VCC_BANK8 FPGA_D6 P15 R15 R16 R17 U19 U20 U22 U21 T20 T19 T17 T18 T21 T22 V6 U5 V5 U7 T8 sysCONFIG Connectors FPGA_D7 FPGA_D6 FPGA_D5 FPGA_D4 FPGA_D3 FPGA_D2 FPGA_D1 FPGA_D0 FPGA_D[0:7] Jumpers normally not installed 1 CSON Jumpers normally not installed VCC_3.3V JB19 JB18 1 3 1 FPGA_D7 FPGA_D0 CCLK VCC_3.3V DONE INITN INIT_CHN 1 2 PROGRAMN PROGN HEADER 2 J11 1x10 JTAG Chain Output Header R127 10K TCK DONE INIT_CHN TMS TDO_CH TDI_CH PROGN TDO TDI TMS TCK SPIFASTN R120 4.7K Installed = Fast Read (0Bx) (default) Removed = Normal Read (03x) Note: Not all SPI Serial Flash support Fast Read VCC /HOLD C D CSSPIN VCC_BANK8 U4 JBLOCK J8 HEADER 2 JB17 4.7K R52 Only One Board in the Chain Should Have this Jumper Installed TCK DONE INIT_CHN TMS TDO_DL TDI PROGN JB16 JBLOCK 1 2 3 1 to 2 = Multiple devices and not last in the chain 2 to 3 = Single device or last in the chain (default) 1 2 4 1 2 5 JB13 JB14 JB15 J43 2 4 6 R124 10K INITN DONE PROGRAMN HEADER 3X2 1 3 5 JBLOCK JBLOCK JBLOCK VCC_3.3V Gate SOT-23 VCC_3.3V VCC_3.3V X 1(OFF) 1(OFF) 0(ON) B1 B2 ispJTAG Slave Parallel Reserved Slave Serial Reserved Reserved SPIm Flash Reserved SPI Flash (Default) Document Number <Doc> 1 Sheet 6 of 8 ECP2 Standard -- JTAG & sysCONFIG B Rev Initializing D11 LED_Red Q1 BSS138LT1 Done D10 LED_Green Program D12 LED_Yellow Program Push Button Configuration Status On When Low R125 470 10K R32 Source Drain On When High 470 R31 PROGRAMN On When Low 470 R33 A2 B2 SW2 SW PUSHBUTTON A1 B1 A2 A1 X 1(OFF) 0(ON) 1(OFF) 0(ON) 1(OFF) 0(ON) Configuration Mode Lattice Semiconductor Corporation Date: Size C Title TP_103 TP_102 TP_100 R118 10K X 1(OFF) 1(OFF) 1(OFF) 0(ON) 1(OFF) 0(ON) 1(OFF) 1(OFF) 0(ON) 0(ON) 0(ON) 1(OFF) 0(ON) 0(ON) 0(ON) 1 CFG0 CFG1 CFG2 A B C D Lattice Semiconductor LatticeECP2 Standard Evaluation Board User’s Guide Figure 13. JTAG and sysCONFIG 33 A B C D 5 [8]VCC_3.3V [8] VCC_1.2V C94 10uF SizeB C95 10uF SizeB + + C65 0.1uF CC0402 C76 0.1uF CC0402 4 4 C64 0.1uF CC0402 C72 0.1uF CC0402 2 4 6 C89 0.1uF CC0402 C73 0.1uF CC0402 C78 0.1uF CC0402 C85 0.1uF CC0402 JBLOCK HEADER 2 J29 JB27 C91 0.1uF CC0402 C75 0.1uF CC0402 C67 0.1uF CC0402 C63 0.1uF CC0402 C71 0.1uF CC0402 VCC_AUX VCC_CORE C82 0.1uF CC0402 Current Measurement (remove jumper, insert meter) JBLOCK JBLOCK JBLOCK JB26 J30 HEADER 3X2 JB24 JB25 1 3 5 Current Measurement (remove jumpers, insert meter) 1 2 5 3 3 C88 0.1uF CC0402 C70 0.1uF CC0402 C87 0.1uF CC0402 R105 10K 1% XRES A1 A22 AA4 AA19 AB1 AB22 B4 B19 C9 C14 F12 C5 D11 E6 E17 F13 G5 G18 K5 M17 P17 R5 V7 V8 V11 V13 V15 J10 J11 J12 J13 K9 K14 L9 L14 M9 M14 N9 N14 P10 P11 P12 P13 (6 of 6) 2 ECP2-12/22/35/50-fpBGA484 GND GND GND GND GND GND GND GND GND GND XRES (10K 1% to GND) VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCC CORE VCC CORE VCC CORE VCC CORE VCC CORE VCC CORE VCC CORE VCC CORE VCC CORE VCC CORE VCC CORE VCC CORE VCC CORE VCC CORE VCC CORE VCC CORE U3F 2 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND D2 D21 F6 F17 H10 H11 H12 H13 J3 J9 J14 J20 K8 K10 K11 K12 K13 K15 L8 L10 L11 L12 L13 L15 M8 M10 M11 M12 M13 M15 N8 N10 N11 N12 N13 N15 P3 P9 P14 P20 R10 R11 R12 R13 U6 U17 W2 W21 Y9 Y14 Document Number <Doc> 1 Sheet 7 ECP2 Standard -- FPGA Power of 8 Rev B Lattice Semiconductor Corporation Date: Size B Title 1 A B C D Lattice Semiconductor LatticeECP2 Standard Evaluation Board User’s Guide Figure 14. FPGA Power A B C D S 1 1 2 3 1 Banana Jack CONN_BLACK S J45 2.5mm Pin, (+) 5.5mm Barrel, (-) PWR JACK J47 5W to 23W 5V DC Only Banana Jack CONN_RED J46 [4] PCI_GND_57 5 VCC_IN C31 + 10uF SizeC VCC_IN D19 MBRS340 SMC Reverse polarity protection VCC_IN 1 2 3 C117 22uF CC1210 16V X5R R40 100K CR0603 SW VIN ISENSE SOT23-6 TPS64203DVB /EN GND FB U9 R46 10 C30 1800pF CC0603 DRAIN_ADV R44 100 CR0805 6 5 4 C24 0.1uF CC0603 8 7 VCC_IN SS EN PAD 9 GND 4 FB SW 5 3 C23 4.7nF DNL CC0603 CC0603 SOD-123 1N5819 D17 R39 5.6K CR0603 10nF CC0603 ECJ-1VB1H103K C32 COMP ECJ-2VB1H472K 6 C22 BS VIN MP2307 1 2 U6 D18 BAT54 SOD-123 VCC_IN D14 B320A SMA L1 4 2 500K 2 R45 200K R36 HEADER 1 1 GND22 C19 4.7pF CC0603 6.2uH 7mmX7mm 1 Q3 Si5447DC Output Voltage Adjust C14 + 100uF SizeD + C20 1uF SizeA C27 10uF CC1210 X7R C21 + 47uF SizeB 3 3 LMK325BJ106MN-T R37 10K 1% CR0603 26.1K 1% CR0603 R38 L3 2 10uH 8.3mmX8.3mm 1 Sumida CDRH8D43-100NC Adjustable, 1.2V to 2.5V, 3A Place Switch next to DC input jack C3225X5R1C226M 4 When this board is plugged into PCI this signal disables the 3.3V converter. 3.3V will then come from the PCI bus. 3 5 5 6 7 8 S D D D G D D D 4 3 2 1 R41 10K VCC_3.3V 1 2 19 20 3 C26 2.2uF CC0805 X7R 8 6 18 7 14 PAD PGND PGND PGND PGND C2- C2+ PG 21 9 10 11 12 13 15 17 5 16 4 1 2 3 SOT23-6 R42 10 C28 1800pF CC0603 DRAIN_1.2 R43 100 CR0805 6 5 4 LMK212BJ225MG-T C25 2.2uF CC0805 X7R 2 C17 10uF CC1210 X7R LMK325BJ106MN-T SW VIN ISENSE TPS64203DVB /EN GND FB U8 VCC_3.3V OUT OUT FB TPS60131 GND GND GND GND ENABLE C1- C1+ NC IN IN U7 D16 1N5820 267-05 C29 + 10uF SizeC VCC_IN D15 1N5820 267-05 HEADER 1 1 GND21 2 5 6 7 8 S D D D G D D D 1 2 6.2uH 7mmX7mm L2 + C16 1uF SizeA 1.2V, 3A 3.3V, 3A 1 VCC_3.3V [2] VCC_5V [3,5,6,7] VCC_1.2V [3,5,6] VCC_ADJ [2,3,4,5,6,7] Document Number <Doc> 1 Sheet ECP2 Standard -- Power 8 of 8 Lattice Semiconductor Corporation Date: Size C Title For LCD Module 5V, 300mA C18 + 100uF SizeD Q2 Si5447DC LMK432BJ226MM-T C15 22uF CC1812 X5R D13 B320A SMA 4 3 2 1 34 1 B Rev A B C D Lattice Semiconductor LatticeECP2 Standard Evaluation Board User’s Guide Figure 15. Power T520B476M006ASE070