LatticeEC™ Advanced Evaluation Board – Revision C User’s Guide April 2007 EB11_02.4 LatticeEC Advanced Evaluation Board – Revision C User’s Guide Lattice Semiconductor Introduction The LatticeEC Advanced Evaluation Board provides a convenient platform to evaluate, test, and debug designs with the support of LatticeEC advanced interface capabilities. The board provides easy access to PCI, DDR SDRAM, FCDRAM and SPI4.2 interfaces. The information in this document pertains only to boards marked as ‘Rev C’. This marking is located on the front of the board, beneath the Lattice logo. Features • Required voltages supplied by PCI or one external 5V DC supply • ispVM® System programming support • SPI3 Flash device included for non-volatile configuration storage • ispDOWNLOAD® cable included • 5V AC adapter included • PCI edge connector (120-pin) for 32-bit PCI interface • SODIMM socket supporting 16-bit, 200MHz 200-pin DDR SDRAM • Onboard FCRAM • SPI4.2 interface via VHDM connectors • Prototyping area with access to over 150 I/O pins • SMA connectors included (10) for high-speed clock and data interfacing Figure 1. LatticeEC Advanced Evaluation Board Electrical, Mechanical and Environmental Specifications The nominal board dimensions are 9 inches by 4.2 inches. The environmental specifications are as follows: • Operating temperature: 0ºC to 55ºC • Storage temperature: -40ºC to 75ºC • Humidity: < 95% without condensation • 5V DC input (+/- 10%) up to 4A, or 3.3V input from PCI backplane 2 LatticeEC Advanced Evaluation Board – Revision C User’s Guide Lattice Semiconductor Additional Resources Additional resources related to this board can be downloaded from the web at www.latticesemi.com/boards. Click on the appropriate evaluation board, then see the blue “Resources” box on the right of the screen for items such as: updated documentation, software, sample designs, IP evaluation bitstreams, and more. Table 1. Embedded Functions Description Source LatticeEC Pin Notes 33.33MHz clock On-Board oscillator F6 / AF14 3.3V TTL Output The 3.3V oscillator socket accepts both full-size and half-size oscillators and can route to different clock inputs, depending on its position within the socket. The 16-pin socket will allow connection to PLL clock pin F6 when the bottom of the oscillator is aligned to socket pins 8 and 9. When the top of the oscillator is aligned to socket pins 1 and 16, the clock is provided to primary clock pin AF14. LatticeEC Device This board features a LatticeEC FPGA with a 1.2V DC core. It can accommodate all pin compatible LatticeEC devices in the 672-ball fpBGA (1mm pitch) package. A complete description of this device can be found in the LatticeECP/EC Family Data Sheet on the Lattice web site at www.latticesemi.com. Note: The connection tables listed in this document refer to the LFEC20E device. Available I/Os and associated sysIO™ banks may differ for other densities within this device family. Programming Headers Two programming headers are provided on the evaluation board, providing access to the LatticeEC JTAG port or the SPI Flash device. The pinouts for the headers are provided in Table 2. Table 2. JTAG Programming Headers Function JP6 (1x10) JP8 (2x5) Vcc (3.3V) 1 6 TDO 2 7 TDI / SFLASH_D 3 5 ISPEN_N / SFLASH_S_N 4 10 DONE 5 9 TMS 6 3 TCK / SFLASH_C 8 1 INITN 10 8 GND 7, 9 2, 4 Note: When using a 1x8 download cable, connect to the 1x10 header by justifying the alignment to pin 1 (VCC). A jumper installed on JP7 provides a connection between the configuration clock (CCLK) and a general-purpose I/O. JP7 must be installed to program the SPI Serial Flash through the LatticeEC device using JTAG; the jumper must be removed to configure the LatticeEC device from SPI Flash (see the section in this document entitled SPI Flash Download via JTAG). This evaluation board utilizes DOUT as the GPIO. When designing your own board choose the pin that is listed in Lattice technical note TN1078, SPI Serial Flash Programming Using ispJTAG on LatticeECP/EC FPGAs for your particular density and package 3 LatticeEC Advanced Evaluation Board – Revision C User’s Guide Lattice Semiconductor Power Setup For stand-alone board operation (i.e. outside of a PCI backplane), the evaluation board may be supplied with a single 5V DC power supply. On-board regulators will provide the supply voltages necessary for each component. The adjustable voltage supply (VCCADJ) is set by the potentiometer located at R32 within the approximate range of 1.22V to 3.26V. The 5V DC power may be applied using the power jack at J22 or the banana jacks at J21 (5V DC) and J20 (GND). The requirements for power jack J22 are listed in Table 3. Table 3. Power Jack J22 Specifications Polarity Positive Center Inside Diameter 0.1” (2.5mm) Outside Diameter 0.218” (5.5mm) Current Capacity 4A Power may also be supplied directly for each individual supply rail using banana jack connectors. To enable this mode of operation, the appropriate fuses must be removed. All power sources must be regulated to the specifications in Table 4. No special power sequencing is required for the evaluation board. Table 4. Individual Control of Supplies Supply Jack Fuse Requirement 3.3V J18 F3 (1.5A) +/- 0.3V 2.5V / 2.6V J16 F1 (3A) +/- 10% 1.2V J17 F2 (3A) +/- 5% VCC_ADJ J19 F4 (1.5A) User-Defined When the evaluation board is inserted into a PCI backplane, all onboard power will be derived from the PCI 3.3V power rail. The onboard 3.3V regulator (U5) will then be automatically be disabled, allowing power to be supplied directly from the PCI host system. Jumper J32 allows the adjustment of the 2.5V power supply for 2.6V operation. This may be necessary for compatibility with high-speed DDR memory modules. A jumper in position 1-2 provides a nominal 2.5V supply. To increase the voltage to 2.6V, place the jumper in position 2-3. Jumpers JP2, JP3, JP4, and JP5 allow the user to select the voltage (VCCIO) applied to the eight I/O banks of the FPGA, as shown in Table 5. Note: Care must be exercised to insure that only one voltage is strapped to each bank and certain restrictions apply depending on which features of the board are being used. 4 LatticeEC Advanced Evaluation Board – Revision C User’s Guide Lattice Semiconductor Table 5. VCCIO Selection Jumper JP2 JP3 JP4 JP5 3.3V 1.2V 2.5V / 2.6V Adjustable VCCIO 0 (Bank0) O O O O O O O O VCCIO 1 O O O O O O O O VCCIO 2 O O O O O O O O VCCIO 3 O O O O O O O O VCCIO 4 O O O O O O O O VCCIO 5 O O O O O O O O VCCIO 6 O O O O O O O O VCCIO 7 (Bank7) O O O O O O O O Note: Shown with factory default settings. Depending on the optional devices installed, some sysIO banks may have restrictions. Table 6. sysIO Bank Considerations Bank Setting 0 2.5V only (FCRAM interface) 1 2.5V/2.6V if DDR SDRAM installed in socket J11 2 2.5V if SPI4.2 interface used 3 2.5V if SPI4.2 interface used, 3.3V if SPI3 configuration mode used1. 4 3.3V when PCI interface used 5 3.3V when PCI interface used 6 Any 7 Any 1. The LatticeEC Advanced Evaluation Board connects 2.5V to the VCCIO of Bank 3 to maximize functionality of the board with the SPI4.2 interface in the same bank as the sysCONFIG™ port. For optimum sysIO compatibility, 3.3V VCCIO is recommended for the sysCONFIG port when interfacing to SPI3 Flash memory devices. The following tables detail the various standards supported by the LatticeEC FPGA Input/Output (sysIO) structures. More information can be found in Lattice technical note number TN1056, LatticeECP/EC sysIO Usage Guide, available on the Lattice web site at www.latticesemi.com. Table 7. Mixed Voltage Support Input sysIO Standards VCCIO 1.2V 1.2V Yes 1.5V Yes 1.8V Yes 2.5V Yes 3.3V Yes 1.5V 1.8V Yes Yes Output sysIO Standards 2.5V 3.3V 1.2V Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 1.5V 1.8V 2.5V 3.3V Yes Yes Yes Yes For example, if VCCIO is connected to 3.3V, the input threshold for any pin within that sysIO bank may be configured as 1.2V, 2.5V or 3.3V. Outputs are driven to the levels present on VCCIO. 5 LatticeEC Advanced Evaluation Board – Revision C User’s Guide Lattice Semiconductor Table 8. sysIO Standards Supported per Bank Description Top Side Banks 0-1 Right Side Banks 2-3 Bottom Side Banks 4-5 Left Side Banks 6-7 Types of I/O Buffers Single-ended Single-ended and Differential Single-ended Single-ended and Differential Output Standards Supported LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 SSTL18 Class I SSTL25 Class I, II SSTL33 Class I, II SSTL18 Class I SSTL25 Class I, II SSTL33 Class I, II SSTL18 Class I SSTL2 Class I, II SSTL3 Class I, II SSTL18 Class I SSTL2 Class I, II SSTL3 Class I, II HSTL15 Class I, III HSTL18_I, II, III HSTL15 Class I, III HSTL18 Class I, II, III HSTL15 Class I, III HSTL18 Class I, II, III HSTL15 Class I, III HSTL18 Class I, II, III SSTL18D Class I, SSTL25D Class I, II SSTL33D Class I, II SSTL18D Class I, SSTL25D Class I, II SSTL33D Class I, II SSTL18D Class I, SSTL25D Class I, II, SSTL33D Class I, II SSTL18D Class I, SSTL25D Class I, II, SSTL33D_I, II HSTL15D Class I, III, HSTL18D Class I, III HSTL15D Class I, III HSTL18D Class I, III HSTL15D Class I, III HSTL18D Class I, III HSTL15D Class I, III HSTL18D Class I, III PCI33 LVDS25E1 LVPECL1 BLVDS1 RSDS1 PCI33 LVDS LVDS25E1 LVPECL1 BLVDS1 RSDS1 PCI33 LVDS25E1 LVPECL1 BLVDS1 RSDS1 PCI33 LVDS LVDS25E1 LVPECL1 BLVDS1 RSDS1 Inputs All Single-ended, Differential All Single-ended, Differential All Single-ended, Differential All Single-ended, Differential Clock Inputs All Single-ended, Differential All Single-ended, Differential All Single-ended, Differential All Single-ended, Differential PCI Support PCI33 with clamp PCI33 no clamp PCI33 with clamp LVDS Output Buffers LVDS (3.5mA) Buffers PCI no clamp LVDS (3.5mA) Buffers 1. These differential standards are implemented by using complementary LVCMOS driver with external resistor pack. 6 LatticeEC Advanced Evaluation Board – Revision C User’s Guide Lattice Semiconductor PCI The LatticeEC Evaluation Board is designed to interface directly to PCI 2.2 compatible systems using the PCI edge connector. All necessary signals required for 32-bit PCI operation are provided to the connector, as shown in Tables 9 and 10. Table 9. PCI Connections – Solder Side J23 Description LatticeEC Pin sysIO Bank 6 PCI_INTA_N AB12 5 7 PCI_INTC_N Y12 5 15 PCI_RST_N AC13 5 17 PCI_GNT_N AB13 4 20 PCI_AD30 AD14 4 22 PCI_AD28 AB14 4 23 PCI_AD26 Y14 4 25 PCI_AD24 AE15 4 26 PCI_IDSEL AC15 4 28 PCI_AD22 AA15 4 29 PCI_AD20 AF16 4 31 PCI_AD18 AD16 4 32 PCI_AD16 AB16 4 34 PCI_FRAME_N Y16 4 36 PCI_TRDY_N AE17 4 38 PCI_STOP_N AC17 4 43 PCI_PAR Y17 4 44 PCI_AD15 AE18 4 46 PCI_AD13 AC18 4 47 PCI_AD11 AA18 4 49 PCI_AD9 AF19 4 52 PCI_CBE0_N AA19 4 54 PCI_AD6 AE20 4 55 PCI_AD4 AF21 4 57 PCI_AD2 AF22 4 58 PCI_AD0 AF23 4 60 PCI_REQ64_N AA13 4 7 LatticeEC Advanced Evaluation Board – Revision C User’s Guide Lattice Semiconductor Table 10. PCI Connections – Component Side J6 Description LatticeEC Pin sysIO Bank 7 PCI_INTB_N AA12 5 8 PCI_INTD_N AF13 5 9 PCI_PRSNT1_N AE13 5 11 PCI_PRSNT2_N AD13 5 16 PCI_CLK W1 6 18 PCI_REQ_N AA13 4 20 PCI_AD31 AE14 5 21 PCI_AD29 AC14 4 23 PCI_AD27 AA14 4 24 PCI_AD25 AF15 4 26 PCI_CBE3_N AD15 4 27 PCI_AD23 AB15 4 29 PCI_AD21 Y15 4 30 PCI_AD19 AE16 4 32 PCI_AD17 AC16 4 33 PCI_CBE2_N AA16 4 35 PCI_IRDY_N AF17 4 37 PCI_DEVSEL_N AD17 4 40 PCI_PERR_N AB17 4 42 PCI_SERR_N AA17 4 44 PCI_CBE1_N AF18 4 45 PCI_AD14 AD18 4 47 PCI_AD12 AB18 4 48 PCI_AD10 Y18 4 52 PCI_AD8 AE19 4 53 PCI_AD7 AF20 4 55 PCI_AD5 AA20 4 56 PCI_AD3 AE21 4 58 PCI_AD1 AE22 4 60 PCI_ACK64_N AF24 4 8 LatticeEC Advanced Evaluation Board – Revision C User’s Guide Lattice Semiconductor SPI 4.2 Provided for SPI 4.2 interfaces are two 6x10 backplane connectors. Connector J15 includes necessary data pairs and control signals for transmit data, while J14 has been configured for receive data. Standard 100-ohm differential termination is provided for all applicable receive signal pairs. Table 11. SPI4.2 Transmit Connections J15 Description LatticeEC Pin sysIO Bank A1 SPI4_TDAT_P0 AA26 3 A2 SPI4_TDAT_P2 U25 3 A3 SPI4_TDAT_P4 T26 3 A4 SPI4_TDAT_P6 T21 3 A7 SPI4_TDAT_P8 R23 3 A8 SPI4_TDAT_P10 P26 3 A9 SPI4_TDAT_P12 P22 3 A10 SPI4_TDAT_P14 N22 3 B1 SPI4_TDAT_N0 AB26 3 B2 SPI4_TDAT_N2 U24 3 B3 SPI4_TDAT_N4 T25 3 B4 SPI4_TDAT_N6 U21 3 B7 SPI4_TDAT_N8 T24 3 B8 SPI4_TDAT_N10 R26 3 B9 SPI4_TDAT_N12 P23 3 B10 SPI4_TDAT_N14 N23 3 C5 SPI4_TSCLK AC24 3 C6 SPI4_TSTAT0 AC26 3 C10 SPI4_TCTL_P N24 3 D6 SPI4_TSTAT1 AC25 3 D10 SPI4_TCTL_N N25 3 E1 SPI4_TDAT_P1 U22 3 E2 SPI4_TDAT_P3 U26 3 E3 SPI4_TDAT_P5 T23 3 E4 SPI4_TDAT_P7 R22 3 E5 SPI4_TDCLK_P AA25 3 E7 SPI4_TDAT_P9 R24 3 E8 SPI4_TDAT_P11 P24 3 E9 SPI4_TDAT_P13 P21 3 E10 SPI4_TDAT_P15 M26 3 F1 SPI4_TDAT_N1 U23 3 F2 SPI4_TDAT_N3 V26 3 F3 SPI4_TDAT_N5 T22 3 F4 SPI4_TDAT_N7 R21 3 F5 SPI4_TDCLK_N AB25 3 F7 SPI4_TDAT_N9 R25 3 F8 SPI4_TDAT_N11 P25 3 F9 SPI4_TDAT_N13 N21 3 F10 SPI4_TDAT_N15 N26 3 9 LatticeEC Advanced Evaluation Board – Revision C User’s Guide Lattice Semiconductor Table 12. SPI4.2 Receive Connections J14 Description LatticeEC Pin sysIO Bank Notes A1 SPI4_RDAT_P14 L21 2 100-ohm LVDS termination A2 SPI4_RDAT_P12 L24 2 100-ohm LVDS termination A3 SPI4_RDAT_P10 K22 2 100-ohm LVDS termination A4 SPI4_RDAT_P8 K26 2 100-ohm LVDS termination A7 SPI4_RDAT_P6 G25 2 100-ohm LVDS termination A8 SPI4_RDAT_P4 H26 2 100-ohm LVDS termination A9 SPI4_RDAT_P2 G22 2 100-ohm LVDS termination A10 SPI4_RDAT_P0 D25 2 100-ohm LVDS termination B1 SPI4_RDAT_N14 M21 2 100-ohm LVDS termination B2 SPI4_RDAT_N12 L25 2 100-ohm LVDS termination B3 SPI4_RDAT_N10 K21 2 100-ohm LVDS termination B4 SPI4_RDAT_N8 L26 2 100-ohm LVDS termination B7 SPI4_RDAT_N6 F25 2 100-ohm LVDS termination B8 SPI4_RDAT_N4 J26 2 100-ohm LVDS termination B9 SPI4_RDAT_N2 F21 2 100-ohm LVDS termination B10 SPI4_RDAT_N0 D26 2 100-ohm LVDS termination C1 SPI4_RCTL_P M23 2 100-ohm LVDS termination C5 SP4_RSTAT0 C25 2 C6 SPI4_RSCLK D23 2 D1 SPI4_RCTL_N M22 2 D5 SPI4_RSTAT1 C26 2 E1 SPI4_RDAT_P15 M24 2 100-ohm LVDS termination E2 SPI4_RDAT_P13 L23 2 100-ohm LVDS termination E3 SPI4_RDAT_P11 J20 2 100-ohm LVDS termination E4 SPI4_RDAT_P9 K24 2 100-ohm LVDS termination E6 SPI4_RDCLK_P H24 2 100-ohm LVDS termination E7 SPI4_RDAT_P7 J25 2 100-ohm LVDS termination E8 SPI4_RDAT_P5 J24 2 100-ohm LVDS termination E9 SPI4_RDAT_P3 G21 2 100-ohm LVDS termination E10 SPI4_RDAT_P1 G23 2 100-ohm LVDS termination F1 SPI4_RDAT_N15 M25 2 100-ohm LVDS termination F2 SPI4_RDAT_N13 L22 2 100-ohm LVDS termination F3 SPI4_RDAT_N11 K20 2 100-ohm LVDS termination F4 SPI4_RDAT_N9 K23 2 100-ohm LVDS termination F6 SPI4_RDCLK_N H23 2 100-ohm LVDS termination F7 SPI4_RDAT_N7 K25 2 100-ohm LVDS termination F8 SPI4_RDAT_N5 H25 2 100-ohm LVDS termination F9 SPI4_RDAT_N3 H21 2 100-ohm LVDS termination F10 SPI4_RDAT_N1 G24 2 100-ohm LVDS termination 10 100-ohm LVDS termination LatticeEC Advanced Evaluation Board – Revision C User’s Guide Lattice Semiconductor DDR SDRAM The included 200-pin SODIMM socket provides a built-in 16-bit interface to standard 2.5V DDR SDRAM memory modules. The required VREF and VTT voltages, as well as termination of each signal to VTT, are provided. Table 13. DDR Interface to SODIMM Socket J11 Description LatticeEC Pin sysIO Bank 5 SODIMM_DQ7 C15 1 6 SODIMM_DQ0 G14 1 7 SODIMM_DQ6 B16 1 8 SODIMM_DQ1 F14 1 11 SODIMM_DQS0 G15 1 12 SODIMM_DM0 F15 1 13 SODIMM_DQ3 D15 1 14 SODIMM_DQ4 E14 1 17 SODIMM_DQ2 E15 1 18 SODIMM_DQ5 C14 1 19 SODIMM_DQ11 F17 1 20 SODIMM_DQ12 D16 1 23 SODIMM_DQ8 G16 1 24 SODIMM_DQ13 C16 1 25 SODIMM_DQS1 A20 1 26 SODIMM_DM1 E16 1 29 SODIMM_DQ10 G17 1 30 SODIMM_DQ15 C17 1 31 SODIMM_DQ9 F16 1 32 SODIMM_DQ14 D17 1 35 SODIMM_CK0 A15 1 37 SODIMM_CK0_N B15 1 95 SODIMM_CKE1 E17 1 96 SODIMM_CKE0 B17 1 99 SODIMM_A12 D19 1 100 SODIMM_A11 A18 1 101 SODIMM_A9 E18 1 102 SODIMM_A8 B18 1 105 SODIMM_A7 F18 1 106 SODIMM_A6 D18 1 107 SODIMM_A5 F19 1 108 SODIMM_A4 C18 1 109 SODIMM_A3 G18 1 110 SODIMM_A2 A19 1 111 SODIMM_A1 G19 1 112 SODIMM_A0 B19 1 115 SODIMM_A10 E20 1 116 SODIMM_BA1 B20 1 117 SODIMM_BA0 B21 1 118 SODIMM_RAS_N A21 1 11 LatticeEC Advanced Evaluation Board – Revision C User’s Guide Lattice Semiconductor Table 13. DDR Interface to SODIMM Socket (Continued) J11 Description LatticeEC Pin sysIO Bank 119 SODIMM_WE_N B22 1 120 SODIMM_CAS_N A22 1 121 SODIMM_S0_N A23 1 122 SODIMM_S1_N A24 1 FCRAM Included with the evaluation board is a 256Mb (8Mb x 4 x 8-bit) FCRAM device. All necessary voltages and signal terminations are supplied. Table 14. FCRAM Connections U1 Description LatticeEC Pin sysIO Bank 2 FCRAM_DQ0 A14 0 5 FCRAM_DQ1 B14 0 8 FCRAM_DQ2 A13 0 11 FCRAM_DQ3 B13 0 21 FCRAM_A14 A11 0 22 FCRAM_A13 B11 0 23 FCRAM_FN C11 0 24 FCRAM_CS_N D11 0 26 FCRAM_BA0 A10 0 27 FCRAM_BA1 B10 0 28 FCRAM_A10 C10 0 29 FCRAM_A0 D10 0 30 FCRAM_A1 A9 0 31 FCRAM_A2 B9 0 32 FCRAM_A3 C9 0 35 FCRAM_A4 G10 0 36 FCRAM_A5 F10 0 37 FCRAM_A6 E10 0 38 FCRAM_A7 G11 0 39 FCRAM_A8 F11 0 40 FCRAM_A9 E11 0 41 FCRAM_A11 G12 0 42 FCRAM_A12 E12 0 44 FCRAM_PD_N F13 0 45 FCRAM_CLK A2 0 46 FCRAM_CLK_N A3 0 51 FCRAM_DQS F12 0 56 FCRAM_DQ4 D12 0 59 FCRAM_DQ5 C12 0 62 FCRAM_DQ6 B12 0 65 FCRAM_DQ7 A12 0 12 LatticeEC Advanced Evaluation Board – Revision C User’s Guide Lattice Semiconductor Proto Area For general purpose I/Os, numerous test points are provided for direct access. The test points are labeled according to the associated I/O pin location and are listed in Table 15. Table 15. LatticeEC Pins Accessible at Test Points F7 (0) K3 (7) N6 (6) U11 (6) AA11 (5) AE11 (5) K4 (7) 1 U2 (6) AB4 (6) AE12 (5) A4 (0) C8 (0) A5 (0) 2 D1 (7) A6 (0) D2 (7) F9 (0) K5 (7) P2 (6) U3 (6) AB6 (5) AE2 (5) A7 (0) D4 (0) G12 (7) K6 (7) P3 (6) U4 (6) AB7 (5) AE3 (5) F8 (0) P1 (6) A8 (0) D6 (0) G2 (7) L1 (7) P4 (6) U5 (6) AB8 (5) AE5 (5) A16 (1) D7 (0) G3 (7) L2 (7) P5 (6) V11 (6) AB9 (5) AE6 (5) A17 (1) D8 (0) G4 (7) L3 (7) P6 (6) V2 (6) AB10 (5) AE7 (5) B12 (7) D9 (0) G6 (7) L4 (7) R11 (6) W2 (6) AB11 (5) AE8 (5) B3 (0) E12 (7) G7 (0) L5 (7) R2 (6) W21 (3) AC4 (6) AE9 (5) B4 (0) E2 (7) G8 (0) L6 (6) R3 (6) W22 (3) AC5 (5) AF2 (6) B5 (0) E3 (7) G9 (0) L7 (6) R4 (6) Y8 (5) AC6 (5) AF3 (5) B6 (0) E4 (7) H12 (7) M1 (7) R5 (6) Y9 (5) AC7 (5) AF5 (5) B7 (0) E6 (0) H4 (7) M2 (7) R6 (6) Y10 (5) AC8 (5) AF6 (5) B8 (0) E7 (0) J12 (7) M3 (7) T11 (6) Y11 (5) AC9 (5) AF7 (5) C12 (7) E8 (0) J4 (7) M4 (7) T2 (6) AA6 (5) AC10 (5) AF8 (5) C4 (0) E9 (0) J5 (7) M5 (6) T3 (6) AA7 (5) AC11 (5) AF9 (5) C5 (0) 2 F1 (7) J6 (7) M6 (6) T4 (6) AA8 (5) AC12 (5) AF10 (5) C6 (0) F2 (7) K1 (7) N4 (6) T5 (6) AA9 (5) AC23 (3) AF11 (5) C7 (0) F3 (7) K2 (7) N5 (6) T6 (6) AA10 (5) AE10 (5) AF12 (5) Note: sysIO Bank indicated in parenthesis. 1. Also connected to SW1. See Table 16 for details. 2. Also connected to LEDs. See Table 18 for details. Switches Switch 1 (SW1) on the left side of the board is an eight-switch block that is part of the prototyping area. The pull-up resistors associated with SW1 are wired to 2.5V, but any I/O voltage up to 3.3V may be used. A switch in the down position produces a low (0), the up position produces a high (1). Table 16 shows the connections to the LatticeEC I/O pins. Table 16. SW1 Connections Switch I/O Ball sysIO Bank SW1(1) V1 6 SW1(2) U1 6 SW1(3) T1 6 SW1(4) R1 6 SW1(5) P1 6 SW1(6) M1 7 SW1(7) L1 7 SW1(8) K1 7 SW2 is a momentary switch that the user can define for any purpose, such as a global reset. SW2 is wired to I/O ball E23 (bank 4) and applies a low logic level when depressed. 13 LatticeEC Advanced Evaluation Board – Revision C User’s Guide Lattice Semiconductor SW3 is a momentary switch that, when pressed, forces the FPGA to start its programming cycle. SW4, when in position 1 (up), connects the download cable to the SPI Flash so that the user can program the Flash. When SW4 is in position 2 (down) the SPI Flash is connected to the LatticeEC FPGA; pressing and releasing SW3 (assuming the configuration switch, SW5, is properly set) will configure the FPGA. The FPGA may be accessed via the ispJTAG, using J6, no matter which position SW4 is in. SW5 determines which type of device the FPGA expects to receive programming information from and whether the FPGA will be master or slave during the transfer. Table 17 lists the possible configuration modes. A switch in the down position produces a low (0), the up position produces a high (1). Table 17. LatticeEC Configuration Settings SW5-1 SW5-2 SW5-3 Configuration Mode 0 0 0 SPI3 Flash 0 0 1 SPIX Flash 1 0 0 Master Serial 1 0 1 Slave Serial 1 1 0 Master Parallel 1 1 1 Slave Parallel X X X ispJTAG (always available) LEDs Eight user-definable LEDs are provided on the upper left side of the board above SW1. These LEDs are each wired to a separate general purpose I/O as defined in Table 18. The current limiting resistors associated with these LEDs are wired to 2.5V but any I/O voltage up to 3.3V may be used. The LED will light when its associated I/O pin is driven low. Table 18. LEDs LED I/O Ball sysIO Bank D1 B1 7 D2 C1 7 D3 D1 7 D4 E1 7 D5 F1 7 D6 G1 7 D7 H1 7 D8 J1 7 14 LatticeEC Advanced Evaluation Board – Revision C User’s Guide Lattice Semiconductor Miscellaneous Ten SMA connectors are provided for clocks or general purpose, user-definable signals. The center pin is wired to an I/O pin and the outer case is soldered to ground. Table 19 details to which I/O pin each SMA connector is wired. Table 19. SMA Connectors Location I/O Ball sysIO Bank Description J2 Y1 6 GP I/O (T) J3 Y2 6 GP I/O (C) J4 V6 6 PLL FB T, GP I/O J5 W6 6 PLL FB C, GP I/O J7 N2 7 PCLKT, GP I/O J8 N1 7 PCLKC, GP I/O J9 AE4 5 GP I/O (T) J10 AF4 5 GP I/O (C) J12 W24 3 PLL IN T, GP I/O J13 W23 3 PLL IN C, GP I/O Note: T and C can be used as a differential pair. One RJ-45 female connector is provided for general-purpose interfacing to the LatticeEC device. The connections are listed in Table 20. Table 20. RJ-45 Connections J1 LatticeEC Pin sysIO Bank Description 1 AA1 6 GP I/O (T), LDQS45 2 AB1 6 GP I/O (C) 3 Y4 6 GP I/O (T) 4 Y3 6 GP I/O (C) 5 W4 6 GP I/O (C) 6 W3 6 GP I/O (T) 7 AB2 6 GP I/O (C) 8 AC1 6 GP I/O (T) Download Procedures Requirements: • PC with ispVM System v.14.3 (or later) programming management software, installed with appropriate drivers (USB driver for USB Cable, Windows NT/2000/XP parallel port driver for ispDOWNLOAD Cable). Note: An option to install these drivers is included as part of the ispVM System setup. • ispDOWNLOAD Cable (pDS4102-DL2A, HW7265-DL3A, HW-USB-1A, etc.) JTAG Download The LatticeEC device can be configured easily via its JTAG port. The device is SRAM-based, so the it must remain powered on to retain its configuration when programmed in this fashion. 1. Connect the ispDOWNLOAD cable to the appropriate header. JP6 is used for the 1x10 cable, while JP8 is used for the 2x5 version. 15 LatticeEC Advanced Evaluation Board – Revision C User’s Guide Lattice Semiconductor Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWNLOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeECP/EC FPGA device and render the board inoperable. When using a 1x8 download cable, connect to the 1x10 header by justifying the alignment to pin 1 (VCC). 2. Connect the LatticeEC Evaluation Board to an external 5V supply. 3. Start the ispVM System software. 4. Press the ‘SCAN’ button located in the toolbar. The LatticeEC device should be automatically detected. The resulting screen should be similar to Figure 2. Figure 2. ispVM System Interface 5. Double-click the device to open the device information dialog, as shown in Figure 3. In the device information dialog, click the Browse button located under ‘Data File’. Locate the desired bitstream file (.bit). Click OK to both dialog boxes. 16 LatticeEC Advanced Evaluation Board – Revision C User’s Guide Lattice Semiconductor Figure 3. Device Information Dialog 6. Click the green ‘GO’ button. This will begin the download process into the device. 7. Upon successful download, the device will be operational. SPI Flash Download For non-volatile storage of configuration memory, the LatticeEC device features an interface compatible with lowcost SPI3 Flash memory devices. ispVM System has the capability to program the SPI3 Flash device directly. During the LatticeEC power-up cycle, the data stored in the SPI3 Flash device is automatically read into configuration memory. 1. Set switch SW5 to “000”. This enables SPI3 mode by setting the CFG pins of the LatticeEC device. 2. Set switch SW4 to position 1 (up) to enable the SPI3 connections from the programming headers directly to the SPI3 device. 3. Connect the ispDOWNLOAD cable to the appropriate header. JP6 is used for the 1x10 cable, while JP8 is used for the 2x5 version. Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWNLOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeECP/EC FPGA device and render the board inoperable. When using a 1x8 download cable, connect to the 1x10 header by justifying the alignment to pin 1 (VCC). 4. Connect the evaluation board to an external 5V supply. 5. Start the ispVM System software. 6. Create a new chain file (File->New). 17 LatticeEC Advanced Evaluation Board – Revision C User’s Guide Lattice Semiconductor 7. Insert a new device into the chain (Edit->Add Device). 8. In the resulting Device Information dialog, shown in Figure 4, press the ‘Select’ button. Figure 4. Device Selector Dialog 9. Use the pull-down menu to in the ‘Device Family’ field to choose the device ‘FGPA Loader’. Press OK. The resulting dialog should resemble Figure 5. Figure 5. FPGA Loader Setup 10. Choose the ‘Flash Device’ page and press the ‘Select’ button. 11. Select the ‘SPI Serial Flash’ family and choose the device SPI-M25P80, as shown in Figure 6. Press OK. Note: It may be necessary to select an alternate SPI3 Flash device, as the part number is subject to change. 18 LatticeEC Advanced Evaluation Board – Revision C User’s Guide Lattice Semiconductor Figure 6. SPI Device Selection 12. Choose the ‘Configuration Data Setup’ page, as shown in Figure 14. Figure 7. Configuration Data Setup Page 13. Click the ‘Browse’ button near the top of the window. Browse to the desired bitstream (.bit) file, created by the Lattice ispLEVER® design tool. 14. Press OK to exit the FPGA Loader setup. 15. Click the green ‘GO’ button. This will begin the download process into the Flash device. 16. Once the download is complete, toggle switch SW4 to position 2 to restore the SPI3 Flash connections to the LatticeEC device. 17. Cycle the board power. The data should automatically transfer from the Flash to the FPGA. 19 LatticeEC Advanced Evaluation Board – Revision C User’s Guide Lattice Semiconductor SPI Flash Download via JTAG The LatticeEC device is capable of programming the SPI FLASH device from its JTAG port. 1. Install a jumper on JP7. This provides the CCLK to GPIO connection, as described in Lattice technical note TN1078, SPI Serial Flash Programming Using ispJTAG on LatticeECP/EC FPGAs. 2. Ensure that SW2 is set to position 2 (down) and that SW5 is set to “000” to select the SPI configuration mode. 3. Connect the LatticeEC Evaluation Board to an external 5V supply. 4. Connect the ispDOWNLOAD cable to the appropriate header. JP6 is used for the 1x10 cable, while JP8 is used for the 2x5 version. Note: When using a 1x8 download cable, connect to the 1x10 header by justifying the alignment to pin 1 (Vcc). 5. Start the ispVM System software. 6. Press the ‘SCAN’ button located in the toolbar. The LatticeEC device should be automatically detected. The resulting screen should appear similar to Figure 8. Figure 8. ispVM System Interface 7. Double-click the device to open the device information dialog, as shown in Figure 9. In the device information dialog, set the ‘Device Access Options’ setting to ‘Advanced SPI Flash Programming’. The SPI Flash Programmer dialog should immediately appear, as shown in Figure 10. 20 LatticeEC Advanced Evaluation Board – Revision C User’s Guide Lattice Semiconductor Figure 9. Setting the Device Access Options Note: Selection of the ‘Advanced SPI Flash Programming’ option allows the user to specify a data file other than the ispVM System default. This is necessary for the LatticeEC Advanced Evaluation Board. Figure 10. SPI Flash Programmer 8. Choose the ‘CPLD or FPGA Device’ page, as shown in Figure 11. 21 LatticeEC Advanced Evaluation Board – Revision C User’s Guide Lattice Semiconductor Figure 11. FPGA Device Setup 9. Click the ‘Browse’ button to select an alternate Application Specific Data File. Choose the ‘ec20_adv_revc_spi_loader.bit’ file. Note: This file is available in the Design Files section of the LatticeEC Advanced Evaluation Board on the Lattice web site (www.latticesemi.com). 10. Select the ‘Configuration Data Setup’ page, as shown in Figure 12. Figure 12. Configuration Data Setup 11. Browse to the desired data file to program into the Flash device. 12. Choose the ‘Flash Device’ page and press the ‘Select’ button. 13. Select the ‘SPI Serial Flash’ family and choose the device SPI-M25P80, as shown in Figure 13. Press OK. Note: It may be necessary to select an alternate SPI Flash device, as the part number is subject to change. 22 LatticeEC Advanced Evaluation Board – Revision C User’s Guide Lattice Semiconductor Figure 13. SPI Device Selection 14. Press OK to exit the FPGA Loader setup. 15. Click the green ‘GO’ button. This will begin the download process into the Flash device. 16. Remove the jumper at JP7. 17. Cycle the board power. The data should automatically transfer from the Flash to the FPGA. Ordering Information Description Ordering Part Number LatticeEC20 Evaluation Board - Advanced LFEC20E-H-EV LatticeECP20 Evaluation Board - Advanced LFECP20E-H-EV China RoHS Environment-Friendly Use Period (EFUP) 10 Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: [email protected] Internet: www.latticesemi.com Revision History Date Version Change Summary — — December 2006 02.2 Updated PCI Connections – Solder Side table. Correction for PCI_AD24: connects to ball AE15. March 2007 02.3 Added Ordering Information section. April 2007 02.4 Added important information for proper connection of ispDOWNLOAD (Programming) Cables. Previous Lattice releases. © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 23 24 A B C D 5 (Sheet 6) P r o totyping S u p port 5 4 4 3 (Sheet 2) 3 2 - Bit PCI B ank 4 B ank 3 B ank 2 B ank 1 D DR S D R AM FPGA B ank 5 B ank 6 B ank 7 B ank 0 F C R AM (Sheet 3) 3 L a t t i c e S e m i c o n d uctor Corporation (Sheet 4) 1 Date: Size A 2 W e d n e s d a y , N o v e m b e r 2 4 , 2 0 0 4 S heet D o cum ent Num ber 1 1 of 8 C Rev LatticeEC Advanced Evaluation Board 672 fpBGA Title S P I 4.2 Tx S P I 4.2 Rx 2 A B C D Lattice Semiconductor LatticeEC Advanced Evaluation Board – Revision C User’s Guide Appendix A. Schematics Figure 14. Evaluation Board Block Diagram A B C S [ 6] O S C_ P CL K 5 O S C_ P CL K J1 0 S M A Con n ector A E P 9 6 5 0 -1 1 1 3 -0 0 5 N ( A F 4) 1 J9 S M A Con n ector A E P 9 6 5 0 -1 1 1 3 -0 0 5 P ( A E 4) 1 [ 6] [ 6] TP _ A E 1 1 TP _ A F1 1 [ 6] [ 6] TP _ A F1 2 TP _ A E 1 2 [ 6] [ 6] TP _ A D1 2 TP _ A C1 2 [ 6] [ 6] TP _ A E 5 TP _ A A 9 [ 6] [ 6] TP _ A F5 TP _ Y1 0 [ 6] [ 6] TP _ A D6 TP _ A C1 0 [ 6] [ 6] TP _ A F6 TP _ A E 6 [ 6] [ 6] TP _ A F7 TP _ A B 1 0 [ 6] [ 6] TP _ A E 7 TP _ A D1 0 [ 6] T P _ A D7 [ 6] TP _ A A 1 0 [ 6] [ 6] TP _ A F8 TP _ A F9 [ 6] [ 6] TP _ A D1 1 TP _ Y1 1 [ 6] [ 6] TP _ A E 8 TP _ A C1 1 [ 6] [ 6] TP _ A F1 0 TP _ A B 1 1 [ 6] [ 6] TP _ A E 1 0 TP _ A E 9 [ 6] TP _ A A 1 1 [ 7] P C I _ A D3 1 2 10uF 0805 1 C1 4 6 V C C IO _ 5 P C I _ P R S NT2 _ N P C I _ R S T_ N P C I _ P R S NT1 _ N P C I _ I N TD _ N P C I _ I N TB _ N P C I _ I N TA _ N P C I _ I N TC _ N SMA_ A E 4 S MA _ A F4 0 .1 u F V10 V11 V12 W 12 V13 W 13 A F1 4 AE14 A D1 3 A C1 3 AE13 A F1 3 AA12 AB12 A D1 2 A C1 2 A F1 2 AE12 AE11 A F1 1 AA11 Y1 2 AE10 AE9 A F1 0 AB11 AE8 A C1 1 A D1 1 Y1 1 A F8 A F9 A D7 AA10 AE7 A D1 0 A F7 AB10 A F6 AE6 A D6 A C1 0 A F5 Y1 0 AE5 AA9 AE4 A F4 A F3 A D9 AE3 AB9 A D8 A C9 A D5 A D4 A F2 Y9 AE2 AA8 AB8 A C8 A C6 A C5 AB7 AA7 A C7 Y8 BANK4 0 .1 u F 4 0 .1 u F L F E C2 0 E C-6 7 2 V CCO 5 V CCO 5 V CCO 5 V CCO 5 V CCO 5 V CCO 5 P B 3 3 A / P CL K T5 _ 0 P B 3 3 B / P CL K C5 _ 0 P B 3 2 A / V RE F2 _ 5 P B 3 2 B / V RE F1 _ 5 PB31A PB31B P B 3 0 A / B DQ S 3 0 PB30B PB29A PB29B PB28A PB28B PB27A PB27B PB26A PB26B PB25A PB25B PB24A PB24B PB23A PB23B P B 2 2 A / B DQ S 2 2 PB22B PB21A PB21B PB20A PB20B C7 3 C7 8 0 .1 u F PB50A PB50B C7 4 0 .1 u F C6 7 P C I _ A D2 9 P C I _ A D2 8 P C I _ A D3 V14 W 14 V15 W 15 V16 V17 C7 7 A F2 4 AE23 A C1 8 AB18 A F2 3 AA20 AA19 Y1 8 AE19 AE20 AE22 AA18 P C I _ S TOP _ N P C I _ P E R R_ N P C I _ A CK 6 4 _ N P C I _ R EQ64_N 0 .1 u F 2 C1 4 5 0 .1 u F 10uF 0805 C8 1 1 [ 7] V C C I O_4 P C I _ A D1 3 P C I _ A D1 2 P C I _ A D0 P C I _ A D5 P C I _ C BE0_N P C I _ A D1 0 P C I _ A D8 P C I _ A D6 P C I _ A D1 P C I _ A D1 1 P C I _ A D2 AE21 A C1 7 P C I _ S E R R_ N P C I _ PAR P C I _ A D9 P C I _ C BE2_N P C I _ A D1 8 P C I _ A D1 6 P C I _ A D4 P C I _ A D7 A F2 2 AB17 P C I _ DE V S E L _ N P C I _ F R A ME _ N P C I _ I R D Y_ N P C I _ TR D Y _ N P C I _ A D1 5 P C I _ C BE1_N P C I _ A D1 4 P C I _ A D1 7 A F2 1 A F2 0 AA17 Y1 7 A F1 9 AA16 A D1 6 AB16 AE18 A F1 8 A D1 8 A C1 6 A D1 7 Y1 6 Y1 5 AA15 P C I _ A D2 1 P C I _ A D2 2 P C I _ A D1 9 P C I _ A D2 3 AE16 AB15 A F1 7 AE17 P C I _ R EQ_N P C I _ G NT_ N P C I _ C BE3_N P C I _ I DS E L P C I _ A D2 0 P C I _ A D2 6 A F1 6 Y1 4 A D1 5 A C1 5 P C I _ A D2 5 P C I _ A D2 4 A C1 4 AB14 A F1 5 AE15 P C I _ A D3 0 P C I _ A D2 7 A D1 4 AA14 0 .1 u F V CCO 4 V CCO 4 V CCO 4 V CCO 4 V CCO 4 V CCO 4 PB57A PB57B PB56A PB56B PB55A PB55B B DQ S 5 4 / P B 5 4 A PB54B PB53A PB53B PB52A PB52B PB51A PB51B PB18A PB18B PB19A PB19B PB49A PB49B PB48A PB48B PB47A PB47B B DQ S 4 6 / P B 4 6 A PB46B PB45A PB45B PB44A PB44B PB43A PB43B PB42A PB42B PB17A PB17B PB16A PB16B PB15A PB15B (2 of 5) LFEC20E(fpBGA672) P B 1 4 A / B DQ S 1 4 PB14B PB13A PB13B PB12A PB12B PB11A PB11B PB10A PB10B PB41A D1 / P B 4 1 B PB40A D2 / P B 4 0 B PB8A PB8B PB9A PB9B PB39A D3 / P B 3 9 B B DQ S 3 8 / P B 3 8 A D4 / P B 3 8 B PB7A PB7B P B 6 A / B DQ S 6 PB6B D5 / P B 3 7 A D6 / P B 3 7 B V RE F2 _ 4 / P B 3 6 A D7 / P B 3 6 B PB4A PB4B PB5A PB5B V RE F1 _ 4 / P B 3 5 A CS N / P B 3 5 B PB3A PB3B AA13 AB13 3 C8 5 0 .1 u F P C I _ 3 .3 V P CI_ TMS [ 5] [ 5] P C I _ TDO P C I _ TCK [ 7] [ 5] C9 9 C9 6 0 .1 u F C1 0 2C8 4 0 .1 u F C8 8 0 .1 u F P C I _ TDO P C I _ TCK P C I _ 3 .3 V P CI_ TMS P C I _ TDI P C I _ TDI PCI_INTA_N PC I_INTC_N [ 6] P C I _ CL K PCI_RST_N P C I _ CL K J2 3 P C I E D G E C O N N S o ld er S id e [ 5] J6 P C I E D G E C O N N C o m p o n en t S id e 2 PC I_CLK W RITE N / P B 3 4 A CS 1 N / P B 3 4 B PC I_REQ_N BANK5 P CI_AD30 P CI_AD31 P CI_AD29 PB2A PB2B P CI_AD28 P CI_AD26 P CI_AD27 P CI_AD25 AB6 AA6 PC I_IDSEL PC I_CBE3_N P CI_AD23 S [ 6] [ 6] TP _ A B 6 TP _ A A 6 [ 6] [ 6] TP _ A C7 TP _ Y8 [ 6] [ 6] TP _ A B 7 TP _ A A 7 [ 6] [ 6] TP _ A C6 TP _ A C5 [ 6] [ 6] TP _ A B 8 TP _ A C8 [ 6] [ 6] TP _ A E 2 TP _ A A 8 [ 6] [ 6] TP _ A F2 TP _ Y9 [ 6] [ 6] TP _ A D5 TP _ A D4 [ 6] [ 6] TP _ A D8 TP _ A C9 [ 6] [ 6] TP _ A E 3 TP _ A B 9 [ 6] [ 6] TP _ A F3 TP _ A D9 P CI_AD22 P CI_AD20 P CI_AD21 P CI_AD19 U3 B PCI_IRD Y_N 2 P CI_DEVSEL_N 3 PCI_PRSNT2_N P CI_AD18 P CI_AD16 P CI_AD17 PC I_CBE2_N 4 PCI _PERR_N D 1 2 1 2 PCI _SERR_N 1 2 3 4 5 6 7 8 9 10 11 PCI_INTB_N PC I_INTD_N PCI_PRSNT1_N P CI_AD15 PC I_PAR [ 7] PC I_AD9 P CI_AD13 P CI_AD11 J3 1 CO N3 P C I _ G ND_ 5 7 PC I_CBE1_N P CI_AD14 5 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 R7 3 0 PCI_ TRDY_N PCI_STOP_N PC I_REQ64_N P C I _ V IO C1 4 9 0 .0 1 R7 4 5K P C I _ V IO 1 W e d n e s d a y, N o ve m b e r 2 4 , 2 0 0 4 3 2-Bit PCI D o c u m e n t N u m b er S h eet 2 of 8 C Rev L a t t i c e Semiconductor Corporation D at e: Size C Ti tle 1 PC I_AD1 P CI_FRAME_N P CI_AD24 PCI_GNT_N 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 3.3VAUX RST# +VIO_16 GNT# Ground_18 PME# AD[30] +3.3V_21 AD[28] AD[26] Ground_24 AD[24] IDSEL +3.3V_27 AD[22] AD[20] Ground_30 AD[18] AD[16] +3.3V_33 FRAME# Ground_35 TRDY# Ground_37 STOP# +3.3V_39 Reserved_40 Reserved_41 Ground_42 PAR AD[15] +3.3V_45 AD[13] AD[11] Ground_48 AD[09] PC I_AD6 PC I_AD4 PC I_AD5 PC I_AD3 TRST# +12V TMS TDI +5V_5 INTA# INTC# +5V_8 Reserved_9 +VIO_10 Reserved_11 1 2 3 4 5 6 7 8 9 10 11 -12V TCK Ground_3 TDO +5V_5 +5V_7 INTB# INTD# PRSNT1# Reserved_10 PRSNT2# 1 2 PC I_CBE0_N PC I_AD8 PC I_AD7 1 2 3 P CI_AD12 P CI_AD10 PCI_M66EN 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Reserved_14 Ground_15 CLK Ground_17 REQ# +VIO_19 AD[31] AD[29] Ground_22 AD[27] AD[25] +3.3V_25 C/BE#[3] AD[23] Ground_28 AD[21] AD[19] +3.3V_31 AD[17] C/BE#[2] Ground_34 IRDY# +3.3V_36 DEVSEL# Ground_38 LOCK# PERR# +3.3V_41 SERR# +3.3V_43 C/BE#[1] AD[14] Ground_46 AD[12] AD[10] M66EN PC I_AD2 PC I_AD0 52 53 54 55 56 57 58 59 60 61 62 C/BE#[0] +3.3V_53 AD[06] AD[04] Ground_56 AD[02] AD[00] +VIO_59 REQ64# +5V_61 +5V_62 P CI_ACK64_N 52 53 54 55 56 57 58 59 60 61 62 25 AD[08] AD[07] +3.3V_54 AD[05] AD[03] Ground_57 AD[01] +VIO_59 ACK64# +5V_61 +5V_62 A B C D Lattice Semiconductor LatticeEC Advanced Evaluation Board – Revision C User’s Guide Figure 15. 32-Bit PCI Interface A B C D S O DIMM_ A 1 0 S O DIMM_ B A 0 S O DIMM_ W E _ N S O DIMM_ S 0 _ N S O DIMM_ A 7 S O DIMM_ A 5 S O DIMM_ A 3 S O DIMM_ A 1 S O DIMM_ A 1 2 S O DIMM_ A 9 S O DIMM_ CK E 1 S O DIMM_ CK 0 S O D IMM_ CK 0 _ N S O DIMM_ DQ 1 0 S O DIMM_ DQ 9 S O DIMM_ DQ 8 S O DIMM_ DQ S 1 S O DIMM_ DQ 2 S O DIMM_ DQ 1 1 S O DIMM_ DQ S 0 S O DIMM_ DQ 3 S O DIMM_ DQ 7 S O DIMM_ DQ 6 V C C _ 2 .5 V V RE F VSS DQ 0 DQ 1 V DD DQ S 0 DQ 2 VSS DQ 3 DQ 8 V DD DQ 9 DQ S 1 VSS DQ 1 0 DQ 1 1 V DD CK 0 CK 0 # VSS V RE F VSS DQ 4 DQ 5 V DD DM0 DQ 6 VSS DQ 7 DQ 1 2 V DD DQ 1 3 DM1 VSS DQ 1 4 DQ 1 5 V DD V DD VSS VSS 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 DQ 1 6 DQ 1 7 V DD DQ S 2 DQ 1 8 VSS DQ 1 9 DQ 2 4 V DD DQ 2 5 DQ S 3 VSS DQ 2 6 DQ 2 7 V DD (CB 0 ) (CB 1 ) VSS (DQ S 8 ) (CB 2 ) V DD (CB 3 ) NC_ 8 5 VSS (CK 2 ) (CK 2 # ) V DD (CK E 1 ) NC_ 9 7 A12 A9 VSS A7 A5 A3 A1 V DD A10 BA0 W E# S0# NC_ 1 2 3 VSS DQ 3 2 DQ 3 3 V DD DQ S 4 DQ 3 4 VSS DQ 3 5 DQ 4 0 V DD DQ 4 1 DQ S 5 VSS DQ 4 2 DQ 4 3 V DD V DD VSS VSS DQ 4 8 DQ 4 9 V DD DQ S 6 DQ 5 0 VSS DQ 5 1 DQ 5 6 V DD DQ 5 7 DQ S 7 VSS DQ 5 8 DQ 5 9 V DD S DA S CL V DDS P D NC_ 1 9 9 DQ 2 0 DQ 2 1 V DD DM2 DQ 2 2 VSS DQ 2 3 DQ 2 8 V DD DQ 2 9 DM3 VSS DQ 3 0 DQ 3 1 V DD (CB 4 ) (CB 5 ) VSS (DM8 ) (CB 6 ) V DD (CB 7 ) NC_ 8 6 VSS VSS V DD V DD CK E 0 NC_ 9 8 A11 A8 VSS A6 A4 A2 A0 V DD BA1 RA S # CA S # (S 1 # ) NC_ 1 2 4 VSS DQ 3 6 DQ 3 7 V DD DM4 DQ 3 8 VSS DQ 3 9 DQ 4 4 V DD DQ 4 5 DM5 VSS DQ 4 6 DQ 4 7 V DD (CK 1 # ) (CK 1 ) VSS DQ 5 2 DQ 5 3 V DD DM6 DQ 5 4 VSS DQ 5 5 DQ 6 0 V DD DQ 6 1 DM7 VSS DQ 6 2 DQ 6 3 V DD SA0 SA1 SA2 (V S S ) 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 5 2 . 5 V D D R 2 0 0 - p i n S O -DIMM S ocket 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 J1 1 B 2 . 5 V D D R 2 0 0 - p i n S O -DIMM S ocket 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 1 J1 1 A C3 3 0 .1 u F 1 2 7 6 5 U2 L P 2 9 9 5 NS P S O P -8 P V IN A V IN V DDQ C1 4 7 u F S ize D V S E NS E V TT V RE F 3 8 4 S O DIMM_ B A 0 S O DIMM_ W E _ N S O DIMM_ S 0 _ N C1 3 1 2 2 0 u F S ize D ( R i g h t end of V T T i s land) V TT V RE F V TT RN1 9 3 3 CTS 7 4 1 X 1 6 3 S O DIMM_ CK 0 S O D IMM_ CK 0 _ N RN2 1 33 CTS 7 4 1 X 0 8 3 S O D IMM_ RA S _ N S O D IMM_ CA S _ N S O DIMM_ S 1 _ N S O DIMM_ CK E 0 S O DIMM_ A 1 1 S O DIMM_ A 8 S O DIMM_ A 6 S O DIMM_ A 4 S O DIMM_ A 2 S O DIMM_ A 0 S O DIMM_ B A 1 R N7 33 CTS 7 4 1 X 0 8 3 S O DIMM_ CK E 1 S O DIMM_ A 1 2 S O DIMM_ A 9 S O DIMM_ A 7 S O DIMM_ A 5 S O DIMM_ A 3 S O DIMM_ A 1 S O DIMM_ A 1 0 S O DIMM_ DQ 1 4 S O DIMM_ DQ 1 2 S O DIMM_ DQ 1 3 S O DIMM_ DM1 S O DIMM_ DQ 1 5 S O DIMM_ DQ 9 S O DIMM_ DQ 1 1 S O DIMM_ DQ 8 S O DIMM_ DQ S 1 S O DIMM_ DQ 1 0 S O DIMM_ DQ 5 S O DIMM_ DQ 0 S O DIMM_ DQ 1 S O DIMM_ DM0 S O DIMM_ DQ 4 S O DIMM_ DQ 2 S O DIMM_ DQ 7 S O DIMM_ DQ 6 S O DIMM_ DQ S 0 S O DIMM_ DQ 3 C2 5 2 2 0 u F S ize D ( L e f t e nd of V T T i s land) S O DIMM_ B A 1 S O D IMM_ RA S _ N S O D IMM_ CA S _ N S O DIMM_ S 1 _ N S O DIMM_ A 6 S O DIMM_ A 4 S O DIMM_ A 2 S O DIMM_ A 0 S O DIMM_ A 1 1 S O DIMM_ A 8 S O DIMM_ CK E 0 S O DIMM_ DQ 1 5 S O DIMM_ DQ 1 4 S O DIMM_ DQ 1 3 S O DIMM_ DM1 S O DIMM_ DQ 5 S O DIMM_ DQ 1 2 S O DIMM_ DM0 S O DIMM_ DQ 4 S O DIMM_ DQ 0 S O DIMM_ DQ 1 C3 2 0 .1 u F 1 2 GND 2 4 V TT DDR_ DQ 2 DDR_ DQ 5 DDR_ DQ 9 RN1 0 8 7 6 5 22 CTS 7 4 1 X 0 8 3 D D R _ BA0 1 D D R _ W E _N 2 D D R _ S 0 _N 3 4 22 CTS 7 4 1 X 0 8 3 DDR_ RA S _ N 8 DDR_ CA S _ N 7 D D R _ S 1 _N 6 5 RN2 2 1 2 3 4 V TT 22 CTS 7 4 1 X 1 6 3 D D R _ C K E0 16 D D R _ A11 15 D D R _ A8 14 D D R _ A6 13 D D R _ A4 12 D D R _ A2 11 D D R _ A0 10 D D R _ BA1 9 RN2 0 1 2 3 4 5 6 7 8 R N9 33 CTS 7 4 1 X 1 6 3 22 CTS 7 4 1 X 1 6 3 D D R _ C K E1 1 D D R _ A12 2 D D R _ A9 3 D D R _ A7 4 D D R _ A5 5 D D R _ A3 6 D D R _ A1 7 D D R _ A10 8 DDR_ CK 0 DDR_ CK 0 _ N 22 22 R1 7 R1 6 R N8 16 15 14 13 12 11 10 9 D D R _ D Q 14 22 CTS 7 4 1 X 0 8 3 D D R _ D Q 12 8 D D R _ D Q 13 7 D D R _ D M1 6 D D R _ D Q 15 5 22 22 CTS 7 4 1 X 0 8 3 D D R _ D Q 11 5 DDR_ DQ 8 6 D D R _ D Q S1 7 D D R _ D Q 10 8 22 22 V TT 22 22 CTS 7 4 1 X 0 8 3 DDR_ DQ 0 8 DDR_ DQ 1 7 D D R _ D M0 6 DDR_ DQ 4 5 Te s t P oin t 1 E20 F1 7 D1 7 C1 7 D D R _ A10 D D R _ D Q 11 D D R _ D Q 14 D D R _ D Q 15 2 V TT 10uF 0805 1 C1 4 2 V C C I O_1 D D R _ S 0 _N D D R _ S 1 _N C2 0 .1 u F C9 1 0 .1 u F H1 4 H1 5 J1 4 J1 5 J1 6 J1 7 A23 A24 D1 9 E18 B22 F1 9 D D R _ W E _N D D R _ A5 D D R _ A12 D D R _ A9 C1 8 D1 8 B21 G19 DDR_ CA S _ N D D R _ A7 D D R _ A4 D D R _ A6 A22 F1 8 DDR_ RA S _ N D D R _ A3 D D R _ BA0 D D R _ A1 B17 E17 A21 G18 D D R _ C K E0 D D R _ C K E1 3 A20 E16 B20 G17 D D R _ BA1 D D R _ D Q 10 B19 A19 D D R _ D Q S1 D D R _ D M1 D D R _ A0 D D R _ A2 C1 6 D1 6 A18 F1 6 D D R _ A11 DDR_ DQ 9 D D R _ D Q 13 D D R _ D Q 12 B18 G16 D D R _ A8 DDR_ DQ 8 A16 A17 B16 D1 5 DDR_ DQ 6 DDR_ DQ 3 TP _ A 1 6 TP _ A 1 7 C1 5 E15 DDR_ DQ 7 DDR_ DQ 2 A15 B15 G15 F1 5 G14 E14 E13 D1 4 C1 4 F1 4 DDR_ CK 0 DDR_ CK 0 _ N DDR_ DQ 0 DDR_ DQ 4 DDR_ DQ 5 DDR_ DQ 1 3 D D R _ D Q S0 D D R _ D M0 V RE F V RE F [ 7] Te s t P oin t P IN 1 TP 5 P IN TP 2 C1 3 5 0 .1 u F 22 CTS 7 4 1 X 0 8 3 DDR_ DQ 7 5 DDR_ DQ 6 6 D D R _ D Q S0 7 DDR_ DQ 3 8 C1 3 4 0 .1 u F R4 7 RN1 8 1 2 3 4 R1 5 R N6 4 3 2 1 R4 5 RN1 6 1 2 3 4 R1 3 R N4 4 3 2 1 C2 1 0 .1 u F 1 2 4 8 7 6 5 1 2 3 4 5 1 2 1 2 33 CTS 741X083 1 2 3 4 RN15 8 7 6 5 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 2 1 2 33 R12 33 CTS 741X083 4 3 2 1 33 R41 33 R44 33 R14 33 CTS 741X083 1 2 3 4 RN17 8 7 6 5 33 CTS 741X083 4 3 2 1 RN3 5 6 7 8 1 2 3 4 C5 4 0 .1 u F C9 0 0 .1 u F L F E C2 0 E C-6 7 2 V CCO 1 V CCO 1 V CCO 1 V CCO 1 V CCO 1 V CCO 1 P T5 7 A P T5 7 B P T5 6 A P T5 6 B P T5 5 A P T5 5 B P T5 4 A / TDQ S 5 4 P T5 4 B P T5 3 A P T5 3 B P T5 2 A P T5 2 B P T5 1 A P T5 1 B P T5 0 A P T5 0 B P T4 9 A P T4 9 B P T4 8 A P T4 8 B P T4 7 A P T4 7 B C6 5 0 .1 u F C9 8 0 .1 u F C1 0 9 0 .1 u F C8 7 0 .1 u F (4 of 5) C3 0 .1 u F C7 9 0 .1 u F E6 D7 H1 2 H1 3 J1 0 J1 1 J1 2 J1 3 A14 B14 C1 3 D1 3 B13 A13 F1 2 F1 3 B12 A12 B11 A11 C1 2 D1 2 C4 0 .1 u F FC_ B A 0 FC_ B A 1 2 C6 6 0 .1 u F C6 3 0 .1 u F 1 10uF 0805 2 C1 4 1 [ 7] V RE F V RE F V C C I O_0 F C _ D Q0 F C _ D Q1 F C _ D Q3 F C _ D Q2 FC_ DQ S FC_ P D_ N F C _ D Q6 F C _ D Q7 FC_ A 1 3 FC_ A 1 4 R4 3 R4 6 F C _ FN FC_ CS _ N F C _ D Q5 F C _ D Q4 FC_ A 1 FC_ A 1 1 A9 G12 FC_ A 8 FC_ A 9 FC_ A 7 FC_ A 4 FC_ A 0 FC_ A 1 0 FC_ A 5 FC_ A 3 FC_ A 6 FC_ A 2 FC_ A 1 2 A10 B10 2 F C _ C LK F C _ C L K _N B9 E12 A8 F1 1 C1 1 D1 1 B7 B8 A7 E11 C7 G11 C6 G10 D1 0 C1 0 A6 F1 0 C9 E10 D9 G9 A4 A5 B6 F9 C8 E9 B5 G8 A2 A3 B4 F8 B3 E8 G7 D8 C5 C4 D4 E7 D6 F7 C8 3 0 .1 u F V CCO 0 V CCO 0 V CCO 0 V CCO 0 V CCO 0 V CCO 0 P CL K T0 _ 0 / P T3 3 A P CL K C0 _ 0 / P T3 3 B V RE F2 _ 0 / P T3 2 A V RE F1 _ 0 / P T3 2 B P T3 1 A P T3 1 B TDQ S 3 0 / P T3 0 A P T3 0 B P T2 9 A P T2 9 B P T2 8 A P T2 8 B P T2 7 A P T2 7 B P T2 6 A P T2 6 B P T2 5 A P T2 5 B P T2 4 A P T2 4 B P T2 3 A P T2 3 B TDQ S 2 2 / P T2 2 A P T2 2 B P T2 1 A P T2 1 B P T2 0 A P T2 0 B P T1 9 A P T1 9 B P T1 8 A P T1 8 B P T1 7 A P T1 7 B P T1 6 A P T1 6 B P T1 5 A P T1 5 B TDQ S 1 4 / P T1 4 A P T1 4 B P T1 3 A P T1 3 B P T1 2 A P T1 2 B P T1 1 A P T1 1 B P T1 0 A P T1 0 B P T9 A P T9 B P T8 A P T8 B P T7 A P T7 B TDQ S 6 / P T6 A P T6 B P T5 A P T5 B P T4 A P T4 B P T3 A P T3 B P T2 A P T2 B BANK0 LFEC20E(fpBGA672) P T4 6 A / TDQ S 4 6 P T4 6 B P T4 5 A P T4 5 B P T4 4 A P T4 4 B P T4 3 A P T4 3 B P T4 2 A P T4 2 B P T4 1 A P T4 1 B P T4 0 A P T4 0 B P T3 9 A P T3 9 B P T3 8 A / TDQ S 3 8 P T3 8 B P T3 7 A P T3 7 B P T3 6 A P T3 6 B P T3 5 A / V RE F1 _ 1 P T3 5 B / V RE F2 _ 1 P T3 4 A P T3 4 B BANK1 U3D C8 0 0 .1 u F C6 8 0 .1 u F 120 120 [ 6] [ 6] [ 6] [ 6] F C R A M _ DQ 3 F C R A M _ DQ 2 F C R A M _ DQ 1 F C R A M _ DQ 0 F C R A M_ B A 0 F C R A M_ B A 1 FCRA M_ A 1 0 F C R A M_ A 0 F C R A M_ A 1 F C R A M_ A 2 F C R A M_ A 3 FCRA M_ A 1 4 FCRA M_ A 1 3 FCRA M_ FN F C R A M _ C S_N [ 6] C7 6 0 .1 u F C6 9 0 .1 u F TP _ A 8 [ 6] TP _ B 7 [ 6] TP _ B 8 TP _ A 7 TP _ C7 TP _ C6 TP _ A 6 [ 6] TP _ B 5 [ 6] TP _ G 8 [ 6] TP _ C8 [ 6] TP _ E 9 [ 6] TP _ B 6 [ 6] TP _ F9 [ 6] TP _ A 4 [ 6] TP _ A 5 [ 6] TP _ D9 [ 6] TP _ G 9 F C R A M _ CL K F C R A M _ CL K _ N [ 6] TP _ E 6 [ 6] TP _ D7 [ 6] TP _ D6 [ 6] TP _ F7 [ 6] TP _ D4 [ 6] TP _ E 7 [ 6] TP _ C5 [ 6] TP _ C4 [ 6] TP _ G 7 [ 6] TP _ D8 [ 6] TP _ B 3 [ 6] TP _ E 8 [ 6] TP _ B 4 [ 6] TP _ F8 F C R A M _ DQ S VSS_66 DQ 7 VSSQ_64 NC_ 6 3 DQ 6 V DDQ _ 6 1 NC_ 6 0 DQ 5 VSSQ_58 NC_ 5 7 DQ 4 V DDQ _ 5 5 NC_ 5 4 NC_ 5 3 VSSQ_52 DQ S NC_ 5 0 V RE F VSS_48 NC_ 4 7 /CL K CL K /P D NC_ 4 3 A12 A11 A9 A8 A7 A6 A5 A4 VSS_34 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 C2 4 0 .1 u F C1 7 0 .1 u F V C C _ 2 .5 V C1 6 0 .1 u F C1 9 0 .1 u F C2 3 0 .1 u F C1 3 6 0 .1 u F V RE F FCRA M_ A 1 2 FCRA M_ A 1 1 F C R A M_ A 9 F C R A M_ A 8 F C R A M_ A 7 F C R A M_ A 6 F C R A M_ A 5 F C R A M_ A 4 C2 2 0 .1 u F F C R A M _ CL K C1 8 0 .1 u F C2 0 0 .1 u F R9 10K F C R A M _ CL K _ N F C R A M _ DQ S [ 3 ], [ 7 ] F C R A M _ P D_ N R1 0 120 F C R A M _ DQ 4 F C R A M _ DQ 5 F C R A M _ DQ 6 F C R A M _ DQ 7 F C R A M _ P D_ N 25 CTS 7 4 1 X 1 6 3 F C R A M_ B A 0 16 F C R A M_ B A 1 15 FCRA M_ A 1 0 14 F C R A M_ A 0 13 F C R A M_ A 1 12 F C R A M_ A 2 11 F C R A M_ A 3 10 9 25 CTS 7 4 1 X 0 8 3 FCRA M_ A 1 4 8 FCRA M_ A 1 3 7 FCRA M_ FN 6 F C R A M _ C S_N 5 25 CTS 7 4 1 X 1 6 3 FCRA M_ A 1 2 16 FCRA M_ A 1 1 15 F C R A M_ A 9 14 F C R A M_ A 8 13 F C R A M_ A 7 12 F C R A M_ A 6 11 F C R A M_ A 5 10 F C R A M_ A 4 9 25 25 CTS 7 4 1 X 0 8 3 F C R A M _ DQ 4 8 F C R A M _ DQ 5 7 F C R A M _ DQ 6 6 F C R A M _ DQ 7 5 25 CTS 7 4 1 X 0 8 3 F C R A M _ DQ 3 8 F C R A M _ DQ 2 7 F C R A M _ DQ 1 6 F C R A M _ DQ 0 5 1 W e d n e s d a y, N o ve m b e r 2 4 , 2 0 0 4 S h eet 3 of DDR SDRAM and FCRAM D o c u m e n t N u m b er 8 C Rev L a t t i c e Semiconductor Corporation D at e: Size C Ti tle V DD_ 1 DQ 0 V DDQ _ 3 NC_ 4 DQ 1 VSSQ_6 NC_ 7 DQ 2 V DDQ _ 9 NC_ 1 0 DQ 3 VSSQ_12 NC_ 1 3 NC_ 1 4 V DDQ _ 1 5 NC_ 1 6 NC_ 1 7 V DD_ 1 8 NC_ 1 9 NC_ 2 0 A14 A13 FN /CS NC_ 2 5 BA0 BA1 A10 A0 A1 A2 A3 V DD_ 3 3 U1 RN1 3 1 2 3 4 5 6 7 8 RN1 2 1 2 3 4 RN1 4 1 2 3 4 5 6 7 8 R1 1 R N1 1 2 3 4 R N2 1 2 3 4 F C R A M To s h ib a TC5 9 L M8 0 6 CFT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 FC_ P D_ N FC_ B A 0 FC_ B A 1 FC_ A 1 0 FC_ A 0 FC_ A 1 FC_ A 2 FC_ A 3 FC_ A 1 4 FC_ A 1 3 F C _ FN FC_ CS _ N FC_ A 1 2 FC_ A 1 1 FC_ A 9 FC_ A 8 FC_ A 7 FC_ A 6 FC_ A 5 FC_ A 4 FC_ DQ S F C _ D Q4 F C _ D Q5 F C _ D Q6 F C _ D Q7 F C _ D Q3 F C _ D Q2 F C _ D Q1 F C _ D Q0 1 1 2 RN5 5 6 7 8 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 8 7 6 5 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 2 1 1 2 2 1 2 1 2 1 1 2 1 2 1 1 2 2 1 2 2 1 2 1 26 2 A B C D Lattice Semiconductor LatticeEC Advanced Evaluation Board – Revision C User’s Guide Figure 16. DDR SDRAM and FCRAM A B C D G ND_ L 1 G ND_ L 2 G ND_ L 3 G ND_ L 4 G ND_ L 5 G ND_ L 6 G ND_ L 7 G ND_ L 8 G ND_ L 9 G ND_ L 1 0 G ND_ K 1 G ND_ K 2 G ND_ K 3 G ND_ K 4 G ND_ K 5 G ND_ K 6 G ND_ K 7 G ND_ K 8 G ND_ K 9 G ND_ K 1 0 G ND_ J1 G ND_ J2 G ND_ J3 G ND_ J4 G ND_ J5 G ND_ J6 G ND_ J7 G ND_ J8 G ND_ J9 G ND_ J1 0 G ND_ H1 G ND_ H2 G ND_ H3 G ND_ H4 G ND_ H5 G ND_ H6 G ND_ H7 G ND_ H8 G ND_ H9 G ND_ H1 0 G ND_ G 1 G ND_ G 2 G ND_ G 3 G ND_ G 4 G ND_ G 5 G ND_ G 6 G ND_ G 7 G ND_ G 8 G ND_ G 9 G ND_ G 1 0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F1 0 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D1 0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C1 0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 F1 F2 F3 F4 F5 F6 F7 F8 F9 F1 0 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D1 0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C1 0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 S P I4 _ TDA T_ N6 S P I4 _ TDA T_ N4 S P I4 _ TDA T_ N2 S P I4 _ TDA T_ N0 R D A T_ N6 R D A T_ N4 R D A T_ N2 R D A T_ N0 S P I4 _ TDA T_ N1 5 S P I4 _ TDA T_ N1 3 S P I4 _ TDA T_ N1 1 S P I4 _ TDA T_ N9 S 1 RDCL K _ N S P I 4 _ TDCL K _ N R D A T_ N7 S P I4 _ TDA T_ N7 R D A T_ N5 S P I4 _ TDA T_ N5 R D A T_ N3 S P I4 _ TDA T_ N3 R D A T_ N1 S P I4 _ TDA T_ N1 R D A T_ N1 5 R D A T_ N1 3 R D A T_ N1 1 R D A T_ N9 R D C L K_P S P I4 _ TDCL K _ P RDA T_ P 7 S P I4 _ TDA T_ P 7 S P I4 _ TDA T_ P 5 RDA T_ P 5 RDA T_ P 3 S P I4 _ TDA T_ P 3 RDA T_ P 1 S P I4 _ TDA T_ P 1 S P I4 _ TDA T_ P 1 5 S P I4 _ TDA T_ P 1 3 S P I4 _ TDA T_ P 1 1 S P I4 _ TDA T_ P 9 S P I4 _ TS TA T1 RS TA T1 RDA T_ P 1 5 RDA T_ P 1 3 RDA T_ P 1 1 RDA T_ P 9 S P I4 _ TCTL _ N S P I4 _ TS TA T0 S P I4 _ TS CL K R C TL _ N RS TA T0 R S C LK S 1 J1 3 S M A Con n ector A E P 9 6 5 0 -1 1 1 3 -0 0 5 N ( W 2 3) 5 S P I4 _ TDA T_ N1 4 S P I4 _ TDA T_ N1 2 S P I4 _ TDA T_ N1 0 S P I4 _ TDA T_ N8 R D A T_ N1 4 R D A T_ N1 2 R D A T_ N1 0 R D A T_ N8 S P I4 _ TCTL _ P S P I4 _ TDA T_ P 6 S P I4 _ TDA T_ P 4 S P I4 _ TDA T_ P 2 S P I4 _ TDA T_ P 0 RDA T_ P 6 RDA T_ P 4 RDA T_ P 2 RDA T_ P 0 RCTL _ P S P I4 _ TDA T_ P 1 4 S P I4 _ TDA T_ P 1 2 S P I4 _ TDA T_ P 1 0 S P I4 _ TDA T_ P 8 RDA T_ P 1 4 RDA T_ P 1 2 RDA T_ P 1 0 RDA T_ P 8 J1 2 S M A Con n ector A E P 9 6 5 0 -1 1 1 3 -0 0 5 P ( W 2 4) MOLE X V HDM 7 4 0 5 7 -1 0 0 2 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 J1 J2 J3 J4 J5 J6 J7 J8 J9 J1 0 H1 H2 H3 H4 H5 H6 H7 H8 H9 H1 0 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 J1 5 From LatticeEC FPGA 5 F 10 G 10 H 10 J 10 K 10 L 10 F9 A9 B9 C9 D9 E9 G9 H9 J9 K9 L9 A8 B8 C8 D8 E8 F8 G8 H8 J8 K8 L8 A7 B7 C7 D7 E7 F7 G7 H7 J7 K7 L7 A6 B6 C6 D6 E6 F6 G6 H6 J6 K6 L6 A5 B5 C5 D5 E5 F5 G5 H5 J5 K5 L5 A4 B4 C4 D4 E4 F4 G4 H4 J4 K4 L4 A3 B3 C3 D3 E3 F3 G3 H3 J3 K3 L3 F2 A2 B2 C2 D2 E2 G2 H2 J2 K2 L2 A1 B1 C1 D1 E1 F1 P IN TP 4 TP 6 Te s t P oin t 1 4 SMA_ W 2 3 SMA_ W 2 4 Te s t P oin t 1 Te s t P oin t P IN 1 P IN TP 3 [ 5] TP _ Y2 6 S IS P I S P ID0 [ 5] CS S P IN [ 5] [ 5] TP _ W 2 1 TP _ W 2 2 S P I4 _ TDCL K _ P S P I 4 _ TDCL K _ N 2 10uF 0805 1 C1 4 4 V C C I O_3 S P I4 _ TS CL K TP _ A C2 3 S P I4 _ TDA T_ P 0 S P I4 _ TDA T_ N0 Y2 6 Y2 5 W 21 W 22 TP _ Y2 6 C S S P IN C9 4 0 .1 u F P18 P19 R1 8 R1 9 T1 8 U1 8 A C2 4 A C2 3 A C2 6 A C2 5 AA25 AB25 AA26 AB26 W 24 W 23 W 26 W 25 U2 6 V26 U2 5 U2 4 U2 2 U2 3 T2 1 U2 1 T2 6 T2 5 T2 3 T2 2 R2 3 T2 4 R2 4 R2 5 S P ID0 S IS P I S P I4 _ TDA T_ P 3 S P I4 _ TDA T_ N3 S P I4 _ TDA T_ P 2 S P I4 _ TDA T_ N2 S P I4 _ TDA T_ P 1 S P I4 _ TDA T_ N1 S P I4 _ TDA T_ P 6 S P I4 _ TDA T_ N6 S P I4 _ TDA T_ P 4 S P I4 _ TDA T_ N4 S P I4 _ TDA T_ P 5 S P I4 _ TDA T_ N5 S P I4 _ TDA T_ P 8 S P I4 _ TDA T_ N8 S P I4 _ TDA T_ P 9 S P I4 _ TDA T_ N9 P26 R2 6 S P I4 _ TDA T_ P 1 0 S P I4 _ TDA T_ N1 0 P24 P25 R2 2 R2 1 S P I4 _ TDA T_ P 7 S P I4 _ TDA T_ N7 S P I4 _ TDA T_ P 1 1 S P I4 _ TDA T_ N1 1 M2 6 N2 6 P21 N2 1 P22 P23 S P I4 _ TS TA T0 S P I4 _ TS TA T1 [ 7] N2 4 N2 5 N2 2 N2 3 S P I4 _ TDA T_ P 1 2 S P I4 _ TDA T_ N1 2 S P I4 _ TDA T_ P 1 5 S P I4 _ TDA T_ N1 5 S P I4 _ TDA T_ P 1 3 S P I4 _ TDA T_ N1 3 S P I4 _ TDA T_ P 1 4 S P I4 _ TDA T_ N1 4 S P I4 _ TCTL _ P S P I4 _ TCTL _ N G1 H1 J1 K1 L1 P R4 5 A / RDQ S 4 5 P R4 5 B C1 2 4 0 .1 u F L F E C2 0 E C-6 7 2 V CCO 3 V CCO 3 V CCO 3 V CCO 3 V CCO 3 V CCO 3 P R4 8 A / V RE F1 _ 3 P R4 8 B / V RE F2 _ 3 P R4 7 A P R4 7 B C1 2 5 0 .1 u F P R4 4 A / RL M0 _ P L L T_ IN_ A P R4 4 B / RL M0 _ P L L C_ IN_ A P R4 6 A P R4 6 B F 10 G 10 H 10 J 10 K 10 L 10 G9 H9 J9 K9 L9 P R7 A P R7 B RDQ S 6 / P R6 A P R6 B P R5 A P R5 B P R4 A P R4 B P R3 A P R3 B V RE F2 _ 2 / P R2 A V RE F1 _ 2 / P R2 B BANK2 RUM0 _ P L L T_ IN_ A / P R8 A RUM0 _ P L L C_ IN_ A / P R8 B C1 2 6 0 .1 u F 3 A9 B9 C9 D9 E9 F9 F8 A8 B8 C8 D8 E8 G8 H8 J8 K8 L8 F7 A7 B7 C7 D7 E7 G7 H7 J7 K7 L7 F6 A6 B6 C6 D6 E6 G6 H6 J6 K6 L6 A5 B5 C5 D5 E5 F5 G5 H5 J5 K5 L5 F4 A4 B4 C4 D4 E4 G4 H4 J4 K4 L4 A3 B3 C3 D3 E3 F3 G3 H3 J3 K3 L3 A2 B2 C2 D2 E2 F2 G2 H2 J2 K2 L2 2 A1 B1 C1 D1 E1 F1 C1 1 1 0 .1 u F R4 9 S P I4 _ RDA T_ P 3 S P I 4 _ RDA T_ N3 R1 9 R5 2 S P I4 _ RDA T_ P 5 S P I 4 _ RDA T_ N5 S P I4 _ RDA T_ P 4 S P I 4 _ RDA T_ N4 J2 4 H2 5 H2 6 J2 6 R5 3 R6 1 S P I4 _ RDA T_ P 1 4 S P I 4 _ RDA T_ N1 4 S P I4 _ RDA T_ P 1 5 S P I 4 _ RDA T_ N1 5 L23 L22 L21 M2 1 M2 4 M2 5 K17 K18 L18 M1 8 N1 8 N1 9 K26 L26 C9 2 0 .1 u F 1 R2 1 [ 7] C9 3 0 .1 u F 10uF 0805 2 C1 4 3 V C C I O_2 S P I4 _ RDA T_ P 8 S P I 4 _ RDA T_ N8 S P I4 _ RCTL _ P S P I 4 _ RCTL _ N R5 9 S P I4 _ RDA T_ P 1 3 S P I 4 _ RDA T_ N1 3 L24 L25 M2 3 M2 2 R6 0 R5 8 S P I4 _ RDA T_ P 7 S P I 4 _ RDA T_ N7 S P I4 _ RDA T_ P 1 2 S P I 4 _ RDA T_ N1 2 J2 5 K25 R2 0 R5 6 R4 8 S P I4 _ RDA T_ P 1 1 S P I 4 _ RDA T_ N1 1 S P I4 _ RDA T_ P 1 0 S P I 4 _ RDA T_ N1 0 J2 0 K20 R5 0 S P I4 _ RDA T_ P 9 S P I 4 _ RDA T_ N9 S P I4 _ RDA T_ P 6 S P I 4 _ RDA T_ N6 S P I 4 _ RDCL K _ P S P I 4 _ R DCL K _ N R1 8 R5 1 S P I4 _ RDA T_ P 0 S P I 4 _ RDA T_ N0 S P I4 _ RDA T_ P 2 S P I 4 _ RDA T_ N2 R5 5 S P I4 _ RS TA T0 S P I4 _ RS TA T1 S P I4 _ RDA T_ P 1 S P I 4 _ RDA T_ N1 TP _ E 2 3 K22 K21 K24 K23 C1 1 2 0 .1 u F V CCO 2 V CCO 2 V CCO 2 V CCO 2 V CCO 2 V CCO 2 P CL K T2 _ 0 / P R2 2 A P CL K C2 _ 0 / P R2 2 B P R2 1 A P R2 1 B P R2 0 A P R2 0 B RDQ S 1 9 / P R1 9 A P R1 9 B P R1 8 A P R1 8 B P R1 7 A P R1 7 B P R1 6 A P R1 6 B P R1 5 A P R1 5 B P R1 4 A P R1 4 B P R1 3 A P R1 3 B P R1 2 A P R1 2 B P R1 1 A P R1 1 B G25 F2 5 H2 4 H2 3 G21 H2 1 D2 5 D2 6 G22 F2 1 G23 G24 C2 5 C2 6 D2 3 E23 S P I 4 _ RS CL K C1 2 0 0 .1 u F 100 R5 4 100 100 100 100 100 100 100 100 100 100 100 R5 7 100 100 100 100 G S RN 2 C1 2 1 0 .1 u F 100 100 G S RN J 1 4 F o o t P r i n t o n Solder Side A 10 B 10 C 10 D 10 E 10 RUM0 _ P L L T_ FB _ A / P R9 A RUM0 _ P L L C_ FB _ A / P R9 B (3 of 5) P R4 3 A / RL M0 _ P L L T_ FB _ A P R4 3 B / RL M0 _ P L L C_ FB _ A P R4 2 A / DO UT / CS O B P R4 2 B / DI / CS S P IN P R4 1 A / D7 / S P ID0 P R4 1 B / B US Y / S IS P I P R3 9 A P R3 9 B P R3 8 A P R3 8 B P R3 7 A P R3 7 B 3 LFEC20E(fpBGA672) P R3 6 A / RDQ S 3 6 P R3 6 B P R3 5 A P R3 5 B P R3 4 A P R3 4 B P R3 3 A P R3 3 B P R3 2 A P R3 2 B P R3 1 A P R3 1 B P R3 0 A P R3 0 B P R2 9 A P R2 9 B P R2 8 A / RDQ S 2 8 P R2 8 B P R2 7 A P R2 7 B P R2 6 A P R2 6 B P R2 5 A P R2 5 B P R2 4 A P R2 4 B BANK3 U3C J 1 5 F o o t P r i n t o n Solder Side A 10 B 10 C 10 D 10 E 10 4 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 27 L1 C1 2 2 0 .1 u F [ 5] G1 H1 J1 K1 1 2 TS TA T1 TCTL _ N TDA T_ P 1 TDA T_ P 3 TDA T_ P 5 TDA T_ P 7 TDCL K _ P S P I4 _ RS TA T1 S P I 4 _ RCTL _ N S P I4 _ RDA T_ P 1 S P I4 _ RDA T_ P 3 S P I4 _ RDA T_ P 5 S P I4 _ RDA T_ P 7 S P I 4 _ RDCL K _ P C1 2 3 0 .1 u F S P I 4 _ RDA T_ N9 S P I 4 _ RDA T_ N1 1 S P I 4 _ RDA T_ N1 3 S P I 4 _ RDA T_ N1 5 S P I 4 _ RDA T_ N1 S P I 4 _ RDA T_ N3 S P I 4 _ RDA T_ N5 S P I 4 _ RDA T_ N7 S P I 4 _ R DCL K _ N F1 F2 F3 F4 F5 F6 F7 F8 F9 F1 0 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D1 0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C1 0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 J1 4 G ND_ L 1 G ND_ L 2 G ND_ L 3 G ND_ L 4 G ND_ L 5 G ND_ L 6 G ND_ L 7 G ND_ L 8 G ND_ L 9 G ND_ L 1 0 G ND_ K 1 G ND_ K 2 G ND_ K 3 G ND_ K 4 G ND_ K 5 G ND_ K 6 G ND_ K 7 G ND_ K 8 G ND_ K 9 G ND_ K 1 0 G ND_ J1 G ND_ J2 G ND_ J3 G ND_ J4 G ND_ J5 G ND_ J6 G ND_ J7 G ND_ J8 G ND_ J9 G ND_ J1 0 G ND_ H1 G ND_ H2 G ND_ H3 G ND_ H4 G ND_ H5 G ND_ H6 G ND_ H7 G ND_ H8 G ND_ H9 G ND_ H1 0 G ND_ G 1 G ND_ G 2 G ND_ G 3 G ND_ G 4 G ND_ G 5 G ND_ G 6 G ND_ G 7 G ND_ G 8 G ND_ G 9 G ND_ G 1 0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 J1 J2 J3 J4 J5 J6 J7 J8 J9 J1 0 H1 H2 H3 H4 H5 H6 H7 H8 H9 H1 0 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 MOLEX V HDM 7 4 0 5 7 -1 0 0 2 F1 F2 F3 F4 F5 F6 F7 F8 F9 F1 0 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D1 0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C1 0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 1 W e d n e s d a y, N o ve m b e r 2 4 , 2 0 0 4 SPI4.2 D o c u m e n t N u m b er S h eet 4 of 8 C Rev L a t t i c e Semiconductor Corporation D at e: Size C Ti tle TDA T_ N9 TDA T_ N1 1 TDA T_ N1 3 TDA T_ N1 5 TDA T_ N1 TDA T_ N3 TDA T_ N5 TDA T_ N7 TD C L K _ N TDA T_ P 9 TDA T_ P 1 1 TDA T_ P 1 3 TDA T_ P 1 5 TCTL _ P S P I4 _ RCTL _ P S P I4 _ RDA T_ P 9 S P I4 _ RDA T_ P 1 1 S P I4 _ RDA T_ P 1 3 S P I4 _ RDA T_ P 1 5 TS CL K TS TA T0 TDA T_ N8 TDA T_ N1 0 TDA T_ N1 2 TDA T_ N1 4 TDA T_ N0 TDA T_ N2 TDA T_ N4 TDA T_ N6 TDA T_ P 8 TDA T_ P 1 0 TDA T_ P 1 2 TDA T_ P 1 4 TDA T_ P 0 TDA T_ P 2 TDA T_ P 4 TDA T_ P 6 S P I 4 _ RS CL K S P I4 _ RS TA T0 S P I 4 _ RDA T_ N8 S P I 4 _ RDA T_ N1 0 S P I 4 _ RDA T_ N1 2 S P I 4 _ RDA T_ N1 4 S P I 4 _ RDA T_ N0 S P I 4 _ RDA T_ N2 S P I 4 _ RDA T_ N4 S P I 4 _ RDA T_ N6 S P I4 _ RDA T_ P 8 S P I4 _ RDA T_ P 1 0 S P I4 _ RDA T_ P 1 2 S P I4 _ RDA T_ P 1 4 S P I4 _ RDA T_ P 0 S P I4 _ RDA T_ P 2 S P I4 _ RDA T_ P 4 S P I4 _ RDA T_ P 6 To LatticeEC FPGA 1 A B C D Lattice Semiconductor LatticeEC Advanced Evaluation Board – Revision C User’s Guide Figure 17. SPI 4.2 A B V C C _ 3 .3 V V C C _ 3 .3 V 1 V C C _ 1 .2 V V C C _ 3 .3 V C1 3 2 0 .1 u F 10K R2 2 TCK TMS T DI TDO 2 4 6 8 10 HE A DE R 5 X 2 1 3 5 7 9 JP 8 C1 3 3 0 .1 u F C1 1 9 0 .1 u F C6 1 0 .1 u F C1 2 8 0 .1 u F C4 9 0 .1 u F 5 1 2 3 4 1 2 3 4 U4 V CC /HO L D C D 8 7 6 5 S F L A S H_ C S F L A S H_ D V C C _ 3 .3 V V C C _ 3 .3 V V CC /HO L D C D S P I S e r i al FL A S H /S Q /W VSS U9 8 7 6 5 S F L A S H_ C S F L A S H_ D V C C _ 3 .3 V S FL A S H_ Q C7 5 0 .1 u F C5 9 0 .1 u F C3 1 0 .1 u F C5 0 0 .1 u F C8 2 0 .1 u F C5 7 0 .1 u F C3 0 0 .1 u F C5 1 0 .1 u F C9 5 0 .1 u F C5 8 0 .1 u F C2 9 0 .1 u F C5 2 0 .1 u F C1 0 6 0 .1 u F C5 5 0 .1 u F C2 8 0 .1 u F C5 3 0 .1 u F for different size or vender C8 6 0 .1 u F C1 1 3 0 .1 u F C1 3 0 0 .1 u F C3 9 0 .1 u F 10K R2 4 P r e s s U p a n d H o l d (as shown) P r e s s D o w n and Hold S P I S e rial FL A S H S TMicro M2 5 P 8 0 -V MW 6 T /W VSS /S Q 2 1 C1 0 4 0 .1 u F 4 C1 0 0 0 .1 u F C1 2 9 0 .1 u F C3 8 0 .1 u F C1 0 3 0 .1 u F C1 0 1 0 .1 u F C1 2 7 0 .1 u F C3 7 0 .1 u F S F 0 _ H L D_ N S F L A S H_ S _ N S FL A S H_ Q S F L A S H_ D C9 7 0 .1 u F C1 0 5 0 .1 u F C2 6 0 .1 u F C3 6 0 .1 u F [ 4] S P ID0 10K R2 3 C6 0 0 .1 u F C1 0 7 0 .1 u F C2 7 0 .1 u F C3 5 0 .1 u F S P ID0 V C C _ 3 .3 V I S P E N_ N TDO T DI SW 4 S W 4 P D T E -S witch TL 4 2 0 1 E E YA TCK S F L A S H_ C S P I S e r i a l F l a s h i s connected to F P G A f o r S P I 3 F l a s h p rogramming mode S P I S e r i a l F l a s h i s connected to d o w n l o a d c a b l e h e a d e rs JP6 and JP8 Positions of SW4 (Slide Switch 4PDT) Optional SPI Serial FLASH S F L A S H_ S _ N S FL A S H_ Q _ 2 S FL A S H_ Q _ 2 CO N3 J3 0 S FL A S H_ Q _ 1 S F L A S H_ S _ N S FL A S H_ Q _ 1 1 2 3 V C CJ I N I TN I S P E N_ N D o w n l o a d C a b le Header T DO i n p ut o u t put T DI I S P E N_N o u t put D O NE i n p ut T MS o u t put T CK o u t put I N I TN i n p ut S F0 _ W _ N 1 2 C I N I TN TCK TMS V C C _ 3 .3 V V C CJ TDO T DI I S P E N_ N 2x5 Download Cable Header H E A D E R 10 1 2 1 2 3 4 5 6 7 8 9 10 1 2 1 2 1 2 2 1 2 1 2 1 D 1 1 2 2 1 2 1 2 1 2 2 1 2 1 1 2 1 2 1 JP 6 1 1 2 2 1 2 1 2 1 2 2 1 2 1 2 1 1x10 Download Cable Header 1 1 2 2 1 2 1 2 1 2 2 1 2 1 2 1 2 1 S h o r t J P 7 w h e n p r o g r a m ming SPI Serial F L A S H t h r o u g h t h e Soft IP". 1 1 2 2 1 2 1 2 1 2 2 1 2 2 HE A DE R 2 C1 0 8 0 .1 u F TP _ Y2 6 [ 4] C6 2 0 .1 u F 1 CCL K TP _ Y2 6 C1 1 0 0 .1 u F C S S P IN S IS P I CCL K C6 4 0 .1 u F 1 1 2 2 1 2 2 1 2 C5 6 0 .1 u F C1 1 5 0 .1 u F 3 [ 6 ],[ 7] [ 7] RN1 1 1 2 3 4 V C C _ 3 .3 V C8 9 0 .1 u F C1 1 8 0 .1 u F N3 U6 V3 V4 V5 U7 C1 1 4 0 .1 u F C1 1 7 0 .1 u F G13 H7 H2 0 J8 J1 9 K7 L20 M7 M2 0 N2 0 P7 P20 T7 T8 T2 0 V7 V19 W 20 Y7 Y1 3 H8 H9 H1 0 H1 1 H1 6 H1 7 H1 8 H1 9 J9 J1 8 K8 K19 L8 L19 M1 9 N7 R7 R2 0 T1 9 U8 U1 9 V8 V9 V18 W8 W9 W 10 W 11 W 16 W 17 W 18 W 19 R4 2 1 0 K 1 % YA G E O 0 4 0 2 X RE S V C CJ 33 CTS 7 4 1 X 0 8 3 8 7 6 5 V C C _ 1 .2 V TDO T DI TMS TCK [ 4] [ 4] 3 C S S P IN S IS P I C1 1 6 0 .1 u F R7 1 1K C3 4 0 .1 u F 1 JP 7 1 1 2 2 1 2 2 P C I _ TDO [ 2] [ 2] [ 2] [ 2] V C C _ 3 .3 V V C C _ 3 .3 V V C C _ 3 .3 V (5 of 5) CFG 2 CFG 1 CFG 0 10K 10K 10K 2 G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND P RO G RA MN DO NE INITN CCL K R6 8 R6 7 R6 6 LFEC20E(fpBGA672) P C I _ TCK P CI_ TMS P C I _ TDI P C I _ TDO L F E C2 0 E C-6 7 2 V CCA UX V CCA UX V CCA UX V CCA UX V CCA UX V CCA UX V CCA UX V CCA UX V CCA UX V CCA UX V CCA UX V CCA UX V CCA UX V CCA UX V CCA UX V CCA UX V CCA UX V CCA UX V CCA UX V CCA UX V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC X RE S V CCJ TDO TDI TMS TCK U3 E P C I _ TCK P CI_ TMS P C I _ TDI 2 K10 K11 K12 K13 K14 K15 K16 L10 L11 L12 L13 L14 L15 L16 L17 M1 0 M1 1 M1 2 M1 3 M1 4 M1 5 M1 6 M1 7 N1 0 N1 1 N1 2 N1 3 N1 4 N1 5 N1 6 N1 7 P10 P11 P12 P13 P14 P15 P16 P17 R1 0 R1 1 R1 2 R1 3 R1 4 R1 5 R1 6 R1 7 T1 0 T1 1 T1 2 T1 3 T1 4 T1 5 T1 6 T1 7 U1 0 U1 1 U1 2 U1 3 U1 4 U1 5 U1 6 U1 7 V22 U2 0 V25 V20 V24 V21 V23 CFG 0 CFG 1 CFG 2 ON 6 5 4 [ 4] G S RN X D9 L E D 0 6 0 3 Red R7 2 100 R2 5 220 V C C _ 3 .3 V SPIX Flash SPI3 Flash ispJTAG S l a v e P a r a l l el M a s t e r P a r a l l el Slave Serial M a s t e r S e r i al C1 5 0 1 .0 u F GSRN ( E 2 3) SW 2 S W P U S H B U TTO N P an ason ic E V Q P 2 H0 2 B D1 1 L E D 0 6 0 3 G reen R2 7 220 V C C _ 3 .3 V P R O G RAM SW 3 S W P U S H B U TTO N P an ason ic E V Q P 2 H0 2 B X 1 (OFF) 0 (ON) 1 (OFF) 0 (ON) C o n f i g u r a t i o n M o de 1 W e d n e s d a y, N o ve m b e r 2 4 , 2 0 0 4 S h eet 5 of 8 JTAG and FPGA Programming D o c u m e n t N u m b er C Rev L a t t i c e Semiconductor Corporation D at e: Size C Ti tle G S RN I N I TN DO NE R2 8 10K V C C _ 3 .3 V D1 0 L E D 0 6 0 3 Yellow R2 6 220 X 1 (OFF) 1 (OFF) 1 (OFF) 0 (ON) 1 (OFF) 1 (OFF) 0 (ON) 1 (OFF) 0 (ON) 1 (OFF) 0 (ON) 0 (ON) 0 (ON) 0 (ON) 1 C FG0 C FG1 C FG2 V C C _ 3 .3 V SW 5 S W D I P -3 CTS 1 9 4 -3 MS T P R O G RA MN DO NE I N I TN CCL K 1 2 3 4 1 1 5 1 1 2 2 1 2 2 28 2 A B C D Lattice Semiconductor LatticeEC Advanced Evaluation Board – Revision C User’s Guide Figure 18. JTAG and FPGA Programming A B C 22 R7 5 L E D ( F1) L E D ( H1) S W D I P -8 CTS 1 9 4 -8 MS T SW 1 R4 0 10K R3 9 10K R3 8 10K R3 7 10K TP _ P 1 TP_M1 R3 5 10K [ 2] TP _ A E 2 [ 2] TP _ A F2 R3 6 10K L E D ( J1) L E D 0 6 0 3 G reen D8 L E D 0 6 0 3 G reen D7 L E D 0 6 0 3 G reen L E D ( G1) L E D 0 6 0 3 G reen D6 AE2 A F2 TP _ P 2 TP _ R2 TP _ T2 TP _ U2 TP _ V 2 TP _ W 2 TP _ K 2 TP _ L 2 TP_M2 K2 L2 M2 P2 R2 T2 U2 V2 W2 TP _ D2 TP _ E 2 TP _ F2 TP _ G 2 D2 E2 F2 G2 F P G A P IN AE2 A F2 P2 R2 T2 U2 V2 W2 K2 L2 M2 D2 E2 F2 G2 TP 1 B B3 AE3 A F3 P3 R3 T3 U3 K3 L3 M3 E3 F3 G3 B3 TP _ V 1 TP _ U1 TP _ T1 TP _ R1 TP _ K 1 R3 3 10K 22 22 22 22 V C C _ 2 .5 V TP _ L 1 R3 4 10K R4 R3 R2 R1 F P G A P IN AE3 A F3 P3 R3 T3 U3 K3 L3 M3 E3 F3 G3 TP 1 C 5 5 1 4 6 7 8 2 3 ( K 1 )( L 1 )( M 1 )( P 1 )( R 1 )( T 1 )( U 1 )( V 1 ) ON V C C _ 2 .5 V 22 22 R6 R8 22 R5 D5 TP _ P 1 TP _ R1 TP _ T1 TP _ U1 TP _ V 1 P1 R1 T1 U1 V1 F P G A P IN P1 R1 T1 U1 V1 TP _ B 1 TP _ C1 TP _ D1 TP _ E 1 TP _ F1 TP _ G 1 TP _ H1 TP _ J1 TP _ K 1 TP _ L 1 TP_M1 B1 C1 D1 E1 F1 G1 H1 J1 K1 L1 M1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 D B1 C1 D1 E1 F1 G1 H1 J1 K1 L1 M1 TP 1 A TP _ B 3 L E D ( C1) L E D ( D1) 1 2 3 4 5 6 7 8 4 16 15 14 13 12 11 10 9 V C C _ 3 .3 V TP _ A D4 TP _ A B 4 TP _ A C4 A5 B5 C5 A C5 A D5 AE5 A F5 J5 K5 L5 M5 N5 P5 R5 T5 U5 A5 B5 C5 F P G A P IN A C5 A D5 AE5 A F5 J5 K5 L5 M5 N5 P5 R5 T5 U5 TP 1 E O S C_ P CL K O S C_ P CL K 1 S 1 G6 A6 B6 C6 D6 E6 2 H1 J1 K2 K1 K3 L3 L2 L1 M3 M4 M1 M2 L4 L5 TP _ H1 TP _ J1 TP _ K 2 TP _ K 1 TP _ K 3 TP _ L 3 TP _ L 2 TP _ L 1 TP_M3 TP_M4 TP_M1 TP_M2 TP _ L 4 TP _ L 5 1 10uF 0805 C4 2 0 .1 u F K9 L9 M8 M9 N8 N9 N2 N1 J6 K6 F1 G1 TP _ J6 TP _ K 6 K4 K5 TP _ K 4 TP _ K 5 TP _ F1 TP _ G 1 J4 J5 S MA _ N2 S MA _ N1 C1 4 8 F6 G6 H4 G4 TP _ J4 TP _ J5 TP _ H4 TP _ G 4 TP _ G 6 D1 E1 F2 G2 TP _ D1 TP _ E 1 D2 E2 TP _ F2 TP _ G 2 F3 G3 TP _ D2 TP _ E 2 B1 C1 E3 E4 C4 1 0 .1 u F L F E C2 0 E C-6 7 2 V CCO 7 V CCO 7 V CCO 7 V CCO 7 V CCO 7 V CCO 7 P L 2 2 A / P CL K T7 _ 0 P L 2 2 B / P CL K C7 _ 0 PL21A PL21B PL20A PL20B Y8 AA8 AB8 A C8 A D8 AE8 A F8 A8 B8 C8 D8 E8 F8 G8 3 C7 0 0 .1 u F L L M0 _ P L L T_ IN_ A / P L 4 1 A L L M0 _ P L L C_ IN_ A / P L 4 1 B PL39A PL39B PL38A PL38B PL37A PL37B L DQ S 3 6 / P L 3 6 A PL36B PL35A PL35B PL34A PL34B C7 1 0 .1 u F C4 3 0 .1 u F D9 E9 F9 G9 TP _ P 1 TP _ P 2 TP _ R6 TP _ T5 TP _ T6 TP _ U5 TP _ U3 TP _ U4 TP _ V 1 TP _ V 2 TP _ W 2 R6 T5 T6 U5 U3 U4 V1 V2 W1 W2 P8 P9 R8 R9 T9 U9 AB4 A C4 A C1 AB2 Y4 Y3 AA1 AB1 W3 W4 Y1 Y2 1 P C I _ CL K 2 C7 2 0 .1 u F 10uF 0805 2 Y1 0 AA10 AB10 A C1 0 A D1 0 AE10 A F1 0 2 C4 7 0 .1 u F C4 6 0 .1 u F R J -45 1 3 5 7 J1 Y1 1 AA11 AB11 A C1 1 A D1 1 AE11 A F1 1 R J 4 5 _ P IN2 R J 4 5 _ P IN4 R J 4 5 _ P IN6 R J 4 5 _ P IN8 F P G A P IN Y1 1 AA11 AB11 A C1 1 A D1 1 AE11 A F1 1 TP 1 K C4 5 0 .1 u F ( A B 1) (Y3) (W3) ( A C 1) 2 4 6 8 [ 2] TP _ Y1 0 [ 2] TP_A A 1 0 [ 2] TP_A B 1 0 [ 2] TP _ A C1 0[ 2] TP _ A D1 0[ 2] TP_A E 1 0 [ 2] TP _ A F1 0 ( A A 1) (Y4) (W4) ( A B 2) R J 4 5 _ P IN1 R J 4 5 _ P IN3 R J 4 5 _ P IN5 R J 4 5 _ P IN7 [ 2] P C I _ CL K F P G A P IN Y1 0 AA10 AB10 A C1 0 A D1 0 AE10 A F1 0 TP 1 J C4 4 0 .1 u F [ 2] TP _ Y9 [ 2] TP _ A A 9 [ 2] TP _ A B 9 [ 2] TP _ A C9 [ 2] TP _ A D9 [ 2] TP _ A E 9 [ 2] TP _ A F9 [ 3] TP _ D9 [ 3] TP _ E 9 [ 3] TP _ F9 [ 3] TP _ G 9 [ 7] C1 4 7 V C C IO _ 6 C4 8 0 .1 u F TP _ A B 4 TP _ A C4 R J 4 5 _ P IN8 R J 4 5 _ P IN7 R J 4 5 _ P IN3 R J 4 5 _ P IN4 R J 4 5 _ P IN1 R J 4 5 _ P IN2 R J 4 5 _ P IN6 R J 4 5 _ P IN5 S MA _ Y1 S MA _ Y2 SMA_ V 6 S MA _ W 6 TP _ U1 TP _ U2 TP _ T3 TP _ T4 U1 U2 T3 T4 TP _ P 6 TP _ R5 P6 R5 TP _ R4 TP _ R3 TP _ T1 TP _ T2 TP_M5 TP_M6 TP _ P 4 TP _ P 3 TP _ R1 TP _ R2 TP _ N4 TP _ N5 TP _ L 7 TP _ L 6 TP _ N6 TP _ P 5 V6 W6 Y9 AA9 AB9 A C9 A D9 AE9 A F9 D9 E9 F9 G9 F P G A P IN Y9 AA9 AB9 A C9 A D9 AE9 A F9 TP 1 I N6 P5 R4 R3 T1 T2 M5 M6 P4 P3 R1 R2 N4 N5 L7 L6 C4 0 0 .1 u F V CCO 6 V CCO 6 V CCO 6 V CCO 6 V CCO 6 V CCO 6 V RE F1 _ 6 / P L 4 8 A V RE F2 _ 6 / P L 4 8 B PL47A PL47B PL46A PL46B L DQ S 4 5 / P L 4 5 A PL45B PL44A PL44B PL43A PL43B L L M0 _ P L L T_ FB _ A / P L 4 2 A L L M0 _ P L L C_ FB _ A / P L 4 2 B (1 of 5) PL33A PL33B PL32A PL32B PL31A PL31B PL30A PL30B PL29A PL29B L DQ S 2 8 / P L 2 8 A PL28B PL27A PL27B PL26A PL26B PL25A PL25B P1 P2 [ 2] TP _ Y8 [ 2] TP _ A A 8 [ 2] TP _ A B 8 [ 2] TP _ A C8 [ 2] TP _ A D8 [ 2] TP _ A E 8 [ 2] TP _ A F8 [ 3] TP _ A 8 [ 3] TP _ B 8 [ 3] TP _ C8 [ 3] TP _ D8 [ 3] TP _ E 8 [ 3] TP _ F8 [ 3] TP _ G 8 PL24A PL24B BANK6 F P G A P IN Y8 AA8 AB8 A C8 A D8 AE8 A F8 A8 B8 C8 D8 E8 F8 G8 TP 1 H LFEC20E(fpBGA672) P L 1 9 A / L DQ S 1 9 PL19B PL18A PL18B PL17A PL17B PL16A PL16B PL15A PL15B PL14A PL14B PL13A PL13B PL12A PL12B PL11A PL11B P L 9 A / L UM0 _ P L L T_ FB _ A P L 9 B / L UM0 _ P L L C_ FB _ A TP _ A A 7 TP _ A B 7 TP _ A C7 TP _ A D7 TP _ A E 7 TP _ A F7 [ 2] [ 2] [ 2] [ 2] [ 2] [ 2] [ 3] TP _ A 7 [ 3] TP _ B 7 [ 3] TP _ C7 [ 3] TP _ D7 [ 3] TP _ E 7 [ 3] TP _ F7 [ 3] TP _ G 7 TP _ L 7 P L 8 A / L UM0 _ P L L T_ IN_ A P L 8 B / L UM0 _ P L L C_ IN_ A PL7A PL7B P L 6 A / L DQ S 6 PL6B PL5A PL5B PL4A PL4B PL3A PL3B 3 AA7 AB7 A C7 A D7 AE7 A F7 L7 A7 B7 C7 D7 E7 F7 G7 F P G A P IN AA7 AB7 A C7 A D7 AE7 A F7 BANK7 U3 A [ 2] [ 2] [ 2] [ 2] [ 2] [ 2] L7 A7 B7 C7 D7 E7 F7 G7 TP 1 G P L 2 A / V RE F2 _ 7 P L 2 B / V RE F1 _ 7 TP _ A A 6 TP _ A B 6 TP _ A C6 TP _ A D6 TP _ A E 6 TP _ A F6 TP _ J6 TP _ K 6 TP _ L 6 TP_M6 TP _ N6 TP _ P 6 TP _ R6 TP _ T6 TP _ G 6 [ 3] TP _ A 6 [ 3] TP _ B 6 [ 3] TP _ C6 [ 3] TP _ D6 [ 3] TP _ E 6 TP _ F3 TP _ G 3 TP _ B 1 TP _ C1 TP _ E 3 TP _ E 4 AA6 AB6 A C6 A D6 AE6 A F6 J6 K6 L6 M6 N6 P6 R6 T6 G6 A6 B6 C6 D6 E6 F P G A P IN AA6 AB6 A C6 A D6 AE6 A F6 J6 K6 L6 M6 N6 P6 R6 T6 TP 1 F [ 7] V C C IO _ 7 J8 S M A Con n ector A E P 9 6 5 0 -1 1 1 3 -0 0 5 N ( N 1) 4 S J7 S M A Con n ector A E P 9 6 5 0 -1 1 1 3 -0 0 5 P ( N 2) (33.33 MHz OSC Installed) O s c i l l a t o r Socket O S C_ P L L CL K O S C 1 ( F6) [ 2] [ 2] TP _ A C5 [ 2] TP _ A D5 [ 2] TP _ A E 5 [ 2] TP _ A F5 TP _ J5 TP _ K 5 TP _ L 5 TP_M5 TP _ N5 TP _ P 5 TP _ R5 TP _ T5 TP _ U5 [ 3] TP _ A 5 [ 3] TP _ B 5 [ 3] TP _ C5 O S C 2 ( A F14) [ 2] [ 3] TP _ A 4 [ 3] TP _ B 4 [ 3] TP _ C4 [ 3] TP _ D4 TP _ E 4 TP _ G 4 TP _ H4 TP _ J4 TP _ K 4 TP _ L 4 TP_M4 TP _ N4 TP _ P 4 TP _ R4 TP _ T4 TP _ U4 D I P S O C - 8 x2 Y1 L E D ( E1) L E D 0 6 0 3 G reen D4 L E D 0 6 0 3 G reen D3 L E D 0 6 0 3 G reen D2 [ 3 ],[ 7] L E D ( B1) V C C _ 2 .5 V AB4 A C4 A D4 G4 H4 J4 K4 L4 M4 N4 P4 R4 T4 U4 A4 B4 C4 D4 E4 F P G A P IN AB4 A C4 A D4 G4 H4 J4 K4 L4 M4 N4 P4 R4 T4 U4 A4 B4 C4 D4 E4 TP 1 D L E D 0 6 0 3 G reen D1 [ 2] TP _ A E 3 [ 2] TP _ A F3 TP _ P 3 TP _ R3 TP _ T3 TP _ U3 TP _ K 3 TP _ L 3 TP_M3 TP _ E 3 TP _ F3 TP _ G 3 [ 3] 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 29 2 A C1 2 A D1 2 AE12 A F1 2 F P G A P IN A C1 2 A D1 2 AE12 A F1 2 1 1 1 1 JP 1 2 4 6 8 P ( V 6) HE A DE R 4 X 2 1 3 5 7 N ( W 6) P ( Y 1) N ( Y 2) J3 S M A Con n ector A E P 9 6 5 0 -1 1 1 3 -0 0 5 S J2 S M A Con n ector A E P 9 6 5 0 -1 1 1 3 -0 0 5 S J5 S M A Con n ector A E P 9 6 5 0 -1 1 1 3 -0 0 5 S J4 S M A Con n ector A E P 9 6 5 0 -1 1 1 3 -0 0 5 S [ 2] TP _ A C1 2[ 2] TP _ A D1 2[ 2] TP_A E 1 2 [ 2] TP _ A F1 2 V C C _ 3 .3 V [ 5 ],[ 7] V C C _ 2 .5 V 1 1 W e d n e s d a y, N o ve m b e r 2 4 , 2 0 0 4 S h eet Prototyping Support D o c u m e n t N u m b er 6 of 8 C Rev L a t t i c e Semiconductor Corporation D at e: Size C Ti tle [ 2] TP _ Y1 1 [ 2] TP_A A 1 1 [ 2] TP_A B 1 1 [ 2] TP _ A C1 1[ 2] TP _ A D1 1[ 2] TP_A E 1 1 [ 2] TP _ A F1 1 TP 1 L A B C D Lattice Semiconductor LatticeEC Advanced Evaluation Board – Revision C User’s Guide Figure 19. Prototyping Support A B C J22 1 2 3 PW R JACK Switchcraft RAPC722 +5VDC 5 D13 1N5820 D12 1N5820 J20 BANANA JACK D14 1N5820 J21 BANANA JACK V CC_IN V CC_IN S 1 1 S 10uF Size C C15 V CC_IN PCI_3.3V C14 10uF Size C SW VIN ISENSE TPS64203DVB /EN GND FB U8 [2] 6 5 4 6 5 4 R70 R69 Q1 Si2323DS Vishay Siliconix SOT23 51 DRAIN_1.2 GATE_1.2 Q2 Si2323DS Vishay Siliconix SOT23 [3] [3] [4] [4] [2] [2] [6] [6] VCCIO_0 VCCIO_1 VCCIO_2 VCCIO_3 VCCIO_4 VCCIO_5 VCCIO_6 VCCIO_7 4 VCCIO_0 VCCIO_1 VCCIO_2 VCCIO_3 VCCIO_4 VCCIO_5 VCCIO_6 VCCIO_7 2 4 6 8 10 12 14 16 HEADER 8X2 1 3 5 7 9 11 13 15 JP2 VCC_3.3V VCCIO_0 VCCIO_1 VCCIO_2 VCCIO_3 VCCIO_4 VCCIO_5 VCCIO_6 VCCIO_7 D16 B320A Diodes Inc. [5] 2 4 6 8 10 12 14 16 HEADER 8X2 1 3 5 7 9 11 13 15 JP3 VCC_1.2V 2 6.2uH Sumida CDRH6D38-6R2 L2 Q4 Si5475DC Vishay Siliconix 1206-8 1 J32 CON3 C5 100uF Size D VCC_1.2V 3 C7 1uF Size A J17 BANANA JACK VCCIO_0 VCCIO_1 VCCIO_2 VCCIO_3 VCCIO_4 VCCIO_5 VCCIO_6 VCCIO_7 C6 100uF Size D PWR_1.2V VCC_1.2V C137 10uF 0805 2 4 6 8 10 12 14 16 HEADER 8X2 1 3 5 7 9 11 13 15 JP4 VCC_2.5V C8 1uF Size A F2 3A FUSE Littelfuse 154003 C138 10uF 0805 F1 3A FUSE Littelfuse 154003 R75 36K 1% YAGEO 0402 2.5V / 2.6V Voltage Selection R62 39K 1% YAGEO 0402 C9 4.7pF VCC_2.5V PWR_2.5V VCC_2.5V R63 42.2K 1% YAGEO 0402 [3],[6] 2 6.2uH Sumida CDRH6D38-6R2 L1 D15 B320A Diodes Inc. 1 Q3 Si5475DC Vishay Siliconix 1206-8 Another P-Channel MOSFET option in SOT23 package DRAIN_1.2 G DRAIN_2.5 GATE_2.5 GATE_1.2 V CC_IN 51 VCCIO Voltage Selection 1 2 3 SW VIN ISENSE TPS64203DVB /EN GND FB PCI_3.3V 1 2 3 U7 G S Another P-Channel MOSFET option in SOT23 package DRAIN_2.5 1 GATE_2.5 1 2 1 2 1 2 1 2 3 D S D S 1 2 1 1 2 2 1 2 S 1 2 1 1 2 1 2 1 2 VCCIO_0 VCCIO_1 VCCIO_2 VCCIO_3 VCCIO_4 VCCIO_5 VCCIO_6 VCCIO_7 [2] V CC_IN V CC_IN 1 2 1 2 4 6 8 10 12 14 16 HEADER 8X2 1 3 5 7 9 11 13 15 JP5 VCC_ADJ 2 C11 4.7uF Size B C13 4.7uF Size B PCI_GND_57 2 R29 10K R31 10K 1 2 1 2 EN VIN U5 EN VIN U6 5 4 FB VOUT VCC_3.3V R30 30.1K 1% YAGEO 0402 R65 30.1K 1% YAGEO 0402 R64 51K 1% YAGEO 0402 PCI_3.3V VCC_3.3V R32 50K POT Murata PVG5H503A01 PWR_3.3V [5],[6] 2 PW R_ADJ J24 J25 J26 J27 J28 J29 CON1 CON1 CON1 CON1 CON1 CON1 J19 BANANA JACK C12 2.2uF Size B J18 BANANA JACK + + C10 2.2uF Size B F3 1.5A FUSE Littelfuse 15401.5 C139 10uF 0805 F4 1.5A FUSE Littelfuse 15401.5 C140 10uF 0805 1 Monday, February 07, 2005 Power Document Number heet 7 of 8 C ev Lattice Semiconductor Corporation Date Size C Title 1 VCC_ADJ GND Pins for Signal Probing 5 4 TPS78601KTT FB VOUT TPS78601KTT GND 3 J16 BANANA JACK 1 GND 3 3 1 V CC_IN 1 2 1 3 1 4 1 S 1 2 D 5 1 S 1 2 1 1 2 1 2 30 1 A B C D Lattice Semiconductor LatticeEC Advanced Evaluation Board – Revision C User’s Guide Figure 20. Power 31 4 3 2 D at e: Size C F r i d a y, J a n u a r y 2 1 , 2 0 0 5 1 S h eet Mechanical Drawing D o c u m e n t N u m b er 8 of 8 C Rev A A L a t t i c e Semiconductor Corporation B B 5 Ti tle 1 C 2 C 3 D 4 D 5 Lattice Semiconductor LatticeEC Advanced Evaluation Board – Revision C User’s Guide Figure 21. Mechanical Drawing