VS-12TTS08S-M3 Series www.vishay.com Vishay Semiconductors Thyristor Surface Mount, Phase Control SCR, 8 A FEATURES Anode 2, 4 4 • Meets MSL level 1, per LF maximum peak of 260 °C • Designed and JEDEC®-JESD 47 2 1 1 Cathode according • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 3 TO-263AB (D2PAK) qualified J-STD-020, 3 Gate APPLICATIONS • Input rectification and crow-bar (soft start) PRODUCT SUMMARY Package TO-263AB (D2PAK) Diode variation Single SCR IT(AV) 8A VDRM/VRRM 800 V VTM 1.2 V IGT 15 mA TJ -40 to +125 °C • Vishay input diodes, switches and output rectifiers which are available in identical package outlines DESCRIPTION The VS-12TTS08S-M3 High Voltage Series of silicon controlled rectifiers are specifically designed for medium power switching and phase control applications. The glass passivation technology used has reliable operation up to 125 °C junction temperature. OUTPUT CURRENT IN TYPICAL APPLICATIONS APPLICATIONS SINGLE-PHASE BRIDGE THREE-PHASE BRIDGE UNITS 13.5 17 A Capacitive input filter TA = 55 °C, TJ = 125 °C, common heatsink of 1 °C/W MAJOR RATINGS AND CHARACTERISTICS PARAMETER IT(AV) TEST CONDITIONS Sinusoidal waveform VALUES UNITS 8 A IT(RMS) 12.5 VRRM/VDRM 800 V ITSM 110 A 1.2 V dV/dt 150 V/μs dI/dt 100 A/μs -40 to +125 °C VRRM, MAXIMUM PEAK REVERSE VOLTAGE V VDRM, MAXIMUM PEAK DIRECT VOLTAGE V IRRM/IDRM AT 125 °C mA 800 800 1.0 VT TJ 8 A, TJ = 25 °C Range VOLTAGE RATINGS PART NUMBER VS-12TTS08S-M3 Revision: 09-Jul-15 Document Number: 94892 1 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VS-12TTS08S-M3 Series www.vishay.com Vishay Semiconductors ABSOLUTE MAXIMUM RATINGS PARAMETER Maximum average on-state current Maximum RMS on-state current Maximum peak one-cycle non-repetitive surge current Maximum I2t for fusing SYMBOL IT(AV) IT(RMS) ITSM I2t TEST CONDITIONS VALUES UNITS 8 TC = 108 °C, 180° conduction, half sine wave 12.5 A 10 ms sine pulse, rated VRRM applied, TJ = 125 °C 95 10 ms sine pulse, no voltage reapplied, TJ = 125 °C 110 10 ms sine pulse, rated VRRM applied, TJ = 125 °C 45 10 ms sine pulse, no voltage reapplied, TJ = 125 °C 64 A2s Maximum I2t for fusing I2t t = 0.1 ms to 10 ms, no voltage reapplied, TJ = 125 °C 640 A2s Maximum on-state voltage drop VTM 8 A, TJ = 25 °C 1.2 V 16.2 m 0.87 V On-state slope resistance Threshold voltage Maximum reverse and direct leakage current rt VT(TO) IRM/IDM TJ = 125 °C TJ = 25 °C TJ = 125 °C 0.05 VR = Rated VRRM/VDRM 1.0 Typical holding current IH Anode supply = 6 V, resistive load, initial IT = 1 A, TJ = 25 °C 30 Maximum latching current IL Anode supply = 6 V, resistive load, TJ = 25 °C 50 TJ = TJ max., linear to 80 %, VDRM = Rg - k = Open 150 V/μs 100 A/μs VALUES UNITS Maximum rate of rise of off-state voltage dV/dt Maximum rate of rise of turned-on current dI/dt mA TRIGGERING PARAMETER SYMBOL TEST CONDITIONS PGM 8.0 PG(AV) 2.0 Maximum peak positive gate current + IGM 1.5 A Maximum peak negative gate voltage - VGM 10 V Maximum peak gate power Maximum average gate power Maximum required DC gate current to trigger Maximum required DC gate voltage to trigger Maximum DC gate voltage not to trigger Maximum DC gate current not to trigger IGT VGT VGD IGD W Anode supply = 6 V, resistive load, TJ = - 65 °C 20 Anode supply = 6 V, resistive load, TJ = 25 °C 15 Anode supply = 6 V, resistive load, TJ = 125 °C 10 Anode supply = 6 V, resistive load, TJ = - 65 °C 1.2 Anode supply = 6 V, resistive load, TJ = 25 °C 1 Anode supply = 6 V, resistive load, TJ = 125 °C 0.7 mA V 0.2 TJ = 125 °C, VDRM = Rated value 0.1 mA VALUES UNITS SWITCHING PARAMETER SYMBOL Typical turn-on time tgt Typical reverse recovery time trr Typical turn-off time tq TEST CONDITIONS TJ = 25 °C 0.8 3 TJ = 125 °C μs 100 Revision: 09-Jul-15 Document Number: 94892 2 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VS-12TTS08S-M3 Series www.vishay.com Vishay Semiconductors THERMAL AND MECHANICAL SPECIFICATIONS PARAMETER SYMBOL Maximum junction and storage temperature range TEST CONDITIONS TJ, TStg Maximum thermal resistance, junction to case RthJC Maximum thermal resistance, junction to ambient RthJA Typical thermal resistance, case to heatsink RthCS VALUES UNITS -40 to +125 °C DC operation 1.5 62 Mounting surface, smooth and greased °C/W 0.5 2 g Approximate weight 0.07 oz. minimum 6 (5) maximum 12 (10) kgf cm (lbf in) Mounting torque 12TTS08 R thJC (DC) = 1.5 K/ W 120 115 Conduc tion Angle 110 30° 60° 105 90° 120° 180° 100 0 2 4 6 8 10 12TTS08S 10 180° 120° 90° 60° 30° 9 8 7 6 RMSLimit 5 4 Conduction Angle 3 2 12TTS08 TJ= 125°C 1 0 0 1 2 3 4 5 6 7 8 9 Average On-state Current (A) Average On-state Current (A) Fig. 1 - Current Rating Characteristics Fig. 3 - On-State Power Loss Characteristics 125 12TTS08 R thJC(DC) = 1.5 K/ W 120 115 Conduction Period 110 30° 60° 90° 120° 105 180° DC 100 0 2 4 6 8 10 12 14 Maximum Average On-state Power Loss (W) Maximum Allowable Case Temperature (°C) Maximum Allowable Case Temperature (°C) 125 Maximum Average On-state Power Loss (W) Case style D2PAK (SMD-220) Marking device 14 DC 180° 120° 90° 60° 30° 12 10 8 RMS Limit 6 4 Conduction Period 2 12TTS08 TJ = 125°C 0 0 2 4 6 8 10 12 14 Average On-state Current (A) Average On-state Current (A) Fig. 2 - Current Rating Characteristics Fig. 4 - On-State Power Loss Characteristics Revision: 09-Jul-15 Document Number: 94892 3 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VS-12TTS08S-M3 Series www.vishay.com Vishay Semiconductors 120 110 At any rated load condition and with rated Vrrm applied following surge. Initial Tj = 150°C at 60 Hz 0.0083s at 50 Hz 0.0100s 90 110 100 Peak Half Sine Wave Forward Current (A) Peak Half Sine Wave Forward Current (A) 100 80 70 60 90 80 70 60 VS-12TTS08 50 50 VS-12TTS08 40 0.01 40 1 Maximum non-repetitive surge current versus pulse train duration. Initial Tj = Tj max. No voltage reapplied Rated Vrrm reapplied 10 100 Number of Equal Amplitude Half Cycle Current Pulses (N) Fig. 5 - Maximum Non-Repetitive Surge Current 0.1 1 Pulse Train Duration (s) 10 Fig. 6 - Maximum Non-Repetitive Surge Current Instantaneous On-state Current (A) 1000 12TTS08 100 TJ= 25°C 10 TJ= 125°C 1 0.5 1 1.5 2 2.5 3 3.5 Instantaneous On-state Voltage (V) Transient Thermal Impedance Z thJC (°C/W) Fig. 7 - On-State Voltage Drop Characteristics 10 Steady State Value (DC Operation) 1 0.1 D = 0.50 D = 0.33 D = 0.25 D = 0.17 D = 0.08 Single Pulse 12TTS08 0.01 0.0001 0.001 0.01 0.1 1 Square Wave Pulse Duration (s) Fig. 8 - Thermal Impedance ZthJC Characteristics Revision: 09-Jul-15 Document Number: 94892 4 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VS-12TTS08S-M3 Series www.vishay.com Vishay Semiconductors ORDERING INFORMATION TABLE Device code VS- 12 T T S 08 S 1 2 3 4 5 6 7 1 - Vishay Semiconductors product 2 - Current rating (12.5 A) 3 - Circuit configuration: TRL -M3 8 9 T = Single thyristor 4 - Package: T = D2PAK 5 - Type of silicon: S = Standard recovery rectifier 6 - Voltage rating (08 = 800 V) 7 - S = Surface mountable 8 - None = Tube TRL = Tape and reel (left oriented) TRR = Tape and reel (right oriented) 9 - -M3 = Halogen-free, RoHS-compliant, and terminations lead (Pb)-free ORDERING INFORMATION (Example) PREFERRED P/N QUANTITY PER T/R MINIMUM ORDER QUANTITY PACKAGING DESCRIPTION VS-12TTS08S-M3 50 1000 Antistatic plastic tubes VS-12TTS08STRR-M3 800 800 13" diameter reel VS-12TTS08STRL-M3 800 800 13" diameter reel LINKS TO RELATED DOCUMENTS Dimensions www.vishay.com/doc?95046 Part marking information www.vishay.com/doc?95444 Packaging information www.vishay.com/doc?95032 Revision: 09-Jul-15 Document Number: 94892 5 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Outline Dimensions www.vishay.com Vishay Semiconductors D2PAK DIMENSIONS in millimeters and inches Conforms to JEDEC® outline D2 PAK (SMD-220) (2)(3) E B Pad layout A A (E) c2 11.00 MIN. (0.43) A (3) L1 4 9.65 MIN. (0.38) (D1) (3) Detail A D H 1 2 17.90 (0.70) 15.00 (0.625) (2) 3 3.81 MIN. (0.15) L2 B B 2.32 MIN. (0.08) A 2 x b2 c 2.64 (0.103) 2.41 (0.096) (3) E1 C View A - A 2xb ± 0.004 M B 0.010 M A M B Plating Base Metal (4) b1, b3 H 2x e Gauge plane c1 (4) (c) B 0° to 8° Seating plane L3 Lead tip A1 L (b, b2) L4 Section B - B and C - C Scale: None Detail “A” Rotated 90 °CW Scale: 8:1 SYMBOL MILLIMETERS MIN. MAX. INCHES MIN. MAX. NOTES SYMBOL MILLIMETERS MIN. MAX. INCHES MIN. MAX. NOTES A 4.06 4.83 0.160 0.190 D1 6.86 8.00 0.270 0.315 3 A1 0.00 0.254 0.000 0.010 E 9.65 10.67 0.380 0.420 2, 3 E1 7.90 8.80 0.311 0.346 3 b 0.51 0.99 0.020 0.039 b1 0.51 0.89 0.020 0.035 b2 1.14 1.78 0.045 0.070 b3 1.14 1.73 0.045 0.068 c 0.38 0.74 0.015 0.029 c1 0.38 0.58 0.015 0.023 c2 1.14 1.65 0.045 0.065 D 8.51 9.65 0.335 0.380 4 e 2.54 BSC 0.100 BSC H 14.61 15.88 0.575 0.625 4 L 1.78 2.79 0.070 0.110 L1 - 1.65 - 0.066 4 L2 1.27 1.78 0.050 0.070 2 L4 L3 0.25 BSC 4.78 5.28 3 0.010 BSC 0.188 0.208 Notes (1) Dimensioning and tolerancing per ASME Y14.5 M-1994 (2) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body (3) Thermal pad contour optional within dimension E, L1, D1 and E1 (4) Dimension b1 and c1 apply to base metal only (5) Datum A and B to be determined at datum plane H (6) Controlling dimension: inch (7) Outline conforms to JEDEC® outline TO-263AB Revision: 08-Jul-15 Document Number: 95046 1 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000