DISCRETE SEMICONDUCTORS DATA SHEET BF1101; BF1101R; BF1101WR N-channel dual-gate MOS-FETs Product specification Supersedes data of 1999 Feb 01 1999 May 14 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR PINNING FEATURES • Short channel transistor with high forward transfer admittance to input capacitance ratio PIN DESCRIPTION 1 source • Low noise gain controlled amplifier up to 1 GHz 2 drain 3 gate 2 • Partly internal self-biasing circuit to ensure good cross-modulation performance during AGC and good DC stabilization. 4 gate 1 handbook, 2 columns 3 4 2 1 Top view MSB035 BF1101R marking code: NCp. Fig.2 APPLICATIONS Simplified outline (SOT143R). • VHF and UHF applications with 3 to 7 V supply voltage, such as television tuners and professional communications equipment. handbook, 2 columns 4 3 3 fpage 4 DESCRIPTION Enhancement type N-channel field-effect transistor with source and substrate interconnected. Integrated diodes between gates and source protect against excessive input voltage surges. The BF1101, BF1101R and BF1101WR are encapsulated in the SOT143B, SOT143R and SOT343R plastic packages respectively. 1 2 Top view 2 MSB014 BF1101 marking code: NDp. Fig.1 1 Top view MSB842 BF1101WR marking code: NC. Simplified outline (SOT143B). Fig.3 Simplified outline (SOT343R). QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDS drain-source voltage − − 7 V ID drain current − − 30 mA Ptot total power dissipation − − 200 mW yfs forward transfer admittance 25 30 − mS Cig1-ss input capacitance at gate 1 − 2.2 2.7 pF Crss reverse transfer capacitance f = 1 MHz − 25 35 fF F noise figure f = 800 MHz − 1.7 2.5 dB Xmod cross-modulation input level for k = 1% at 40 dB AGC 100 − − dBµV Tj operating junction temperature − − 150 °C CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B. 1999 May 14 2 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS drain-source voltage − 7 V ID drain current − 30 mA IG1 gate 1 current − ±10 mA IG2 gate 2 current Ptot total power dissipation Tstg Tj − ±10 mA − 200 mW storage temperature −65 +150 °C operating junction temperature − +150 °C Ts ≤ 110 °C; note 1 Note 1. Ts is the temperature of the soldering point of the source lead. THERMAL CHARACTERISTICS SYMBOL Rth j-s PARAMETER thermal resistance from junction to soldering point MGL615 250 handbook, halfpage Ptot (mW) 200 150 100 50 0 0 50 100 150 200 Ts (°C) Fig.4 Power derating curve. 1999 May 14 3 VALUE UNIT 200 K/W Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR STATIC CHARACTERISTICS Tj = 25 °C unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VG1-S = VG2-S = 0; ID = 10 µA 7 − V V(BR)G1-SS gate 1-source breakdown voltage VG2-S = VDS = 0; IG1-S = 10 mA 7 16 V V(BR)G2-SS gate 2-source breakdown voltage VG1-S = VDS = 0; IG2-S = 10 mA 7 16 V VG2-S = VDS = 0; IS-G1 = 10 mA 0.5 1.5 V V(BR)DSS drain-source breakdown voltage V(F)S-G1 forward source-gate 1 voltage V(F)S-G2 forward source-gate 2 voltage VG1-S = VDS = 0; IS-G2 = 10 mA 0.5 1.5 V VG1-S (th) gate 1-source threshold voltage VG2-S = 4 V; VDS = 5 V; ID = 100 µA 0.3 1.0 V VG2-S (th) gate 2-source threshold voltage VG1-S = 5 V; VDS = 5 V; ID = 100 µA 0.3 1.2 V IDSX drain-source current VG2-S = 4 V; VDS = 5 V; RG1 = 120 kΩ; note 1 8 16 mA IG1-SS gate 1 cut-off current VG2-S = VDS = 0; VG1-S = 5 V − 50 nA IG2-SS gate 2 cut-off current VG1-S = VDS = 0; VG2-S = 4 V − 20 nA Note 1. RG1 connects G1 to VGG = 5 V; see Fig.21. DYNAMIC CHARACTERISTICS Common source; Tamb = 25 °C; VG2-S = 4 V; VDS = 5 V; ID = 12 mA; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT yfs forward transfer admittance pulsed; Tj = 25 °C 25 30 40 mS Cig1-ss input capacitance at gate 1 f = 1 MHz − 2.2 2.7 pF Cig2-ss input capacitance at gate 2 f = 1 MHz − 1.6 − pF Coss output capacitance f = 1 MHz − 1.2 − pF Crss reverse transfer capacitance f = 1 MHz − 25 35 fF F noise figure f = 800 MHz; YS = YS opt − 1.7 2.5 dB Xmod cross-modulation input level for k = 1% at 0 dB AGC; fw = 50 MHz; funw = 60 MHz; note 1 85 − − dBµV input level for k = 1% at 40 dB AGC; fw = 50 MHz; funw = 60 MHz; note 1 100 − − dBµV Note 1. Measured in test circuit of Fig.21. 1999 May 14 4 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR MGS299 20 handbook, halfpage ID (mA) MGS300 20 handbook, halfpage 3V VG2-S = 4 V ID (mA) 3.5 V 16 VG1-S = 1.6 V 16 2.5 V 1.5 V 12 12 2V 1.4 V 8 8 1.3 V 1.2 V 1.5 V 4 4 1.1 V 1V 1V 0 0 0 0.4 0.8 1.2 1.6 2 0 2 4 6 VG1-S (V) VDS (V) 8 VG2-S = 4 V. Tj = 25 °C. VDS = 5 V. Tj = 25 °C. Fig.5 Transfer characteristics; typical values. Fig.6 Output characteristics; typical values. MGS301 100 MGS302 40 handbook, halfpage handbook, halfpage VG2-S = 4 V 3.5 V I G1 (µA) y fs (mS) 3V 80 VG2-S = 4 V 3.5 V 30 3V 60 2.5 V 20 40 2.5 V 2V 10 20 0 2V 0 0 0.5 1 1.5 2 VG1-S (V) 2.5 0 VDS = 5 V. Tj = 25 °C. Fig.7 1999 May 14 4 8 12 16 20 I D (mA) VDS = 5 V. Tj = 25 °C. Gate 1 current as a function of gate 1 voltage; typical values. Fig.8 5 Forward transfer admittance as a function of drain current; typical values. Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR MGS303 20 MGS304 15 handbook, halfpage handbook, halfpage ID (mA) ID (mA) 16 10 12 8 5 4 0 0 0 10 20 30 40 50 I G1 (µA) 0 Drain current as a function of gate 1 current; typical values. ID (mA) 3 4 5 VGG (V) Fig.10 Drain current as a function of gate 1 supply voltage (= VGG); typical values. MGS305 20 handbook, halfpage 2 VDS = 5 V; VG2-S = 4 V; Tj = 25 °C. RG1 = 120 kΩ (connected to VGG); see Fig.21. VDS = 5 V. VG2-S = 4 V. Tj = 25 °C. Fig.9 1 R G1 = 47 kΩ 68 kΩ MGS306 16 handbook, halfpage 82 kΩ VGG = 5 V ID (mA) 100 kΩ 120 kΩ 16 4.5 V 12 150 kΩ 4V 3.5 V 180 kΩ 12 3V 220 kΩ 8 8 4 4 0 0 0 2 4 6 VGG = VDS (V) 8 0 4 VG2-S (V) 6 VDS = 5 V; Tj = 25 °C. RG1 = 120 kΩ (connected to VGG); see Fig.21. VG2-S = 4 V; Tj = 25 °C. RG1 connected to VGG; see Fig.21. Fig.11 Drain current as a function of gate 1 (= VGG) and drain supply voltage; typical values. 1999 May 14 2 Fig.12 Drain current as a function of gate 2 voltage; typical values. 6 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR MGS308 MGS307 40 0 gain reduction (dB) −10 handbook, halfpage handbook, halfpage I G1 (µA) VGG = 5 V 30 4.5 V (3) (2) (1) −20 4V 20 3.5 V −30 3V 10 −40 −50 0 0 2 4 VG2-S (V) 6 0 1 2 3 VAGC (V) 4 VDS = 5 V; VGG = 5 V; f = 50 MHz; Tamb = 25 °C. VDS = 5 V; Tj = 25 °C. RG1 = 120 kΩ (connected to VGG); see Fig.21. (1) RG1 = 68 kΩ. Fig.13 Gate 1 current as a function of gate 2 voltage; typical values. (2) RG1 = 120 kΩ. (3) RG1 = 180 kΩ. Fig.14 Typical gain reduction as a function of the AGC voltage; see Fig.21. MGS309 MGS310 120 25 handbook, halfpage handbook, halfpage ID (mA) Vunw (dBµV) 20 110 (1) 15 (2) 100 (1) (2) (3) (3) 10 90 5 80 0 0 10 20 30 40 50 gain reduction (dB) 0 VDS = 5 V; VGG = 5 V; f = 50 MHz; funw = 60 MHz; Tamb = 25 °C. (1) RG1 = 68 kΩ. (2) RG1 = 120 kΩ. 20 30 40 50 gain reduction (dB) VDS = 5 V; VGG = 5 V; f = 50 MHz; Tamb = 25 °C. (3) RG1 = 180 kΩ. (1) RG1 = 68 kΩ. Fig.15 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; see Fig.21. 1999 May 14 10 (2) RG1 = 120 kΩ. (3) RG1 = 180 kΩ. Fig.16 Drain current as a function of gain reduction; typical values; see Fig.21. 7 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR MGS311 102 handbook, halfpage MGS312 102 handbook, halfpage yis (mS) ϕ rs −102 ϕ rs (deg) |yrs | (mS) |yrs| 10 −10 10 bis 1 g is 10 −1 10 102 f (MHz) 1 10 103 VDS = 5 V; VG2 = 4 V. ID = 12 mA; Tamb = 25 °C. 102 f (MHz) −1 103 VDS = 5 V; VG2 = 4 V. ID = 12 mA; Tamb = 25 °C. Fig.18 Reverse transfer admittance and phase as a function of frequency; typical values. Fig.17 Input admittance as a function of frequency; typical values. MGS313 102 handbook, halfpage |yfs | (mS) |y fs| ϕ fs 10 −102 MGS314 10 handbook, halfpage ϕ fs (deg) yos (mS) bos −10 1 g os 1 10 −1 102 f (MHz) 10 −1 10 103 VDS = 5 V; VG2 = 4 V. ID = 12 mA; Tamb = 25 °C. f (MHz) 103 VDS = 5 V; VG2 = 4 V. ID = 12 mA; Tamb = 25 °C. Fig.19 Forward transfer admittance and phase as a function of frequency; typical values. 1999 May 14 102 Fig.20 Output admittance as a function of frequency; typical values. 8 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR VAGC handbook, full pagewidth R1 10 kΩ C1 4.7 nF C3 4.7 nF C2 RGEN 50 Ω R2 50 Ω RL 50 Ω L1 ≈ 2.2 µH DUT C4 4.7 nF RG1 4.7 nF VGG VI VDS MGS315 Fig.21 Cross-modulation test set-up. Table 1 f (MHz) Scattering parameters: VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb = 25 °C S11 S21 S12 S22 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) 50 0.987 −4.1 2.922 175.0 0.001 87.6 0.990 −2.2 100 0.985 −8.1 2.908 170.3 0.001 86.1 0.989 −4.3 200 0.976 −16.1 2.875 160.8 0.003 83.3 0.985 −8.5 300 0.963 −23.9 2.820 157.6 0.004 80.4 0.982 −12.6 400 0.949 −31.6 2.762 142.6 0.005 78.2 0.977 −16.8 500 0.933 −38.8 2.665 134.1 0.005 77.8 0.972 −20.8 600 0.916 −45.7 2.591 125.7 0.005 78.9 0.967 −24.7 700 0.897 −52.2 2.498 117.7 0.006 81.8 0.961 −28.5 800 0.877 −58.4 2.410 109.6 0.005 89.1 0.957 −32.2 900 0.856 −64.5 2.318 101.6 0.006 97.1 0.950 −35.8 1000 0.832 −70.3 2.214 94.2 0.006 110.4 0.946 −39.6 Table 2 Noise data: VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb = 25 °C Γopt f (MHz) Fmin (dB) (ratio) (deg) Rn (Ω) 800 1.5 0.715 58.3 37.85 1999 May 14 9 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR PACKAGE OUTLINES Plastic surface mounted package; 4 leads SOT143B D B E A X y HE v M A e bp w M B 4 3 Q A A1 c 1 2 Lp b1 e1 detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp b1 c D E e e1 HE Lp Q v w y mm 1.1 0.9 0.1 0.48 0.38 0.88 0.78 0.15 0.09 3.0 2.8 1.4 1.2 1.9 1.7 2.5 2.1 0.45 0.15 0.55 0.45 0.2 0.1 0.1 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 97-02-28 SOT143B 1999 May 14 EUROPEAN PROJECTION 10 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR Plastic surface mounted package; reverse pinning; 4 leads D SOT143R B E A X y HE v M A e bp w M B 3 4 Q A A1 c 2 1 Lp b1 e1 detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp b1 c D E e e1 HE Lp Q v w y mm 1.1 0.9 0.1 0.48 0.38 0.88 0.78 0.15 0.09 3.0 2.8 1.4 1.2 1.9 1.7 2.5 2.1 0.55 0.25 0.45 0.25 0.2 0.1 0.1 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 97-03-10 SOT143R 1999 May 14 EUROPEAN PROJECTION 11 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR Plastic surface mounted package; reverse pinning; 4 leads D SOT343R E B A X HE y v M A e 3 4 Q A A1 c 2 w M B 1 bp Lp b1 e1 detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp b1 c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.4 0.3 0.7 0.5 0.25 0.10 2.2 1.8 1.35 1.15 1.3 1.15 2.2 2.0 0.45 0.15 0.23 0.13 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 97-05-21 SOT343R 1999 May 14 EUROPEAN PROJECTION 12 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR DEFINITIONS Data Sheet Status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 May 14 13 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR NOTES 1999 May 14 14 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1101; BF1101R; BF1101WR NOTES 1999 May 14 15 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 125004/00/02/pp16 Date of release: 1999 May 14 Document order number: 9397 750 05993