PHILIPS BF1203

DISCRETE SEMICONDUCTORS
DATA SHEET
andbook, halfpage
MBD128
BF1203
Dual N-channel dual gate
MOS-FET
Product specification
Supersedes data of 2000 Dec 04
2001 Apr 25
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
FEATURES
BF1203
PINNING - SOT363
• Two low noise gain controlled amplifiers in a single
package
PIN
• Superior cross-modulation performance during AGC
• High forward transfer admittance
• High forward transfer admittance to input capacitance
ratio.
APPLICATIONS
DESCRIPTION
1
gate 1 (a)
2
gate 2
3
drain (a)
4
drain (b)
5
source
6
gate 1 (b)
• Gain controlled low noise amplifiers for VHF and UHF
applications with 3 to 9 V supply voltage, such as digital
and analog television tuners and professional
communications equipment.
g1 (b)
handbook, halfpage
6
5
s
d (b)
4
DESCRIPTION
The BF1203 is a combination of two different dual gate
MOS-FET amplifiers with shared source and gate 2 leads.
The source and substrate are interconnected.
Internal bias circuits enable DC stabilization and a very
good cross-modulation performance during AGC.
Integrated diodes between the gates and source protect
against excessive input voltage surges. The transistor is
encapsulated in a SOT363 micro-miniature plastic
package.
AMP
a
1
2
AMP
b
3
Top view
g1 (a)
g2
d (a)
MBL254
Marking code: L2-
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
Per MOS-FET unless otherwise specified
VDS
drain-source voltage
−
−
10
V
ID
drain current (DC)
−
−
30
mA
yfs
forward transfer admittance
amp. a: ID = 15 mA
23
28
35
mS
amp. b: ID = 12 mA
25
30
40
mS
Cig1-s
input capacitance at gate 1
amp. a: ID = 15 mA; f = 1 MHz
−
2.6
3.1
pF
amp. b: ID = 12 mA; f = 1 MHz
−
1.7
2.2
pF
Crss
reverse transfer capacitance f = 1 MHz
−
15
−
fF
NF
noise figure
amp. a: f = 400 MHz; ID = 15 mA
−
1
1.8
dB
amp. b: f = 800 MHz; ID = 12 mA
−
1.1
1.8
dB
amp. a: input level for k = 1% at 40 dB AGC
105
−
−
dBµV
amp. b: input level for k = 1% at 40 dB AGC
100
105
−
dBµV
Xmod
cross-modulation
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.
2001 Apr 25
2
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1203
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Per MOS-FET unless otherwise specified
VDS
drain-source voltage
−
10
ID
drain current (DC)
−
30
mA
IG1
gate 1 current
−
±10
mA
IG2
gate 2 current
−
±10
mA
Ts ≤ 102 °C; note 1
V
Ptot
total power dissipation
−
200
mW
Tstg
storage temperature
−65
+150
°C
Tj
operating junction temperature
−
150
°C
Note
1. Ts is the temperature at the soldering point of the source lead.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
thermal resistance from junction to soldering point
Rth j-s
MGS359
250
Ptot
handbook, halfpage
(mW)
200
150
100
50
0
0
50
100
150
Ts (°C)
200
Fig.2 Power derating curve.
2001 Apr 25
3
VALUE
UNIT
240
K/W
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1203
STATIC CHARACTERISTICS
Tj = 25 °C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Per MOS-FET unless otherwise specified
V(BR)DSS
drain-source breakdown voltage
VG1-S = VG2-S = 0; ID = 10 µA
10
−
V
V(BR)G1-SS
gate-source breakdown voltage
VGS = VDS = 0; IG1-S = 10 mA
6
10
V
V(BR)G2-SS
gate-source breakdown voltage
VGS = VDS = 0; IG2-S = 10 mA
6
10
V
V(F)S-G1
forward source-gate voltage
VG2-S = VDS = 0; IS-G1 = 10 mA
0.5
1.5
V
V(F)S-G2
forward source-gate voltage
VG1-S = VDS = 0; IS-G2 = 10 mA
0.5
1.5
V
VG1-S(th)
gate-source threshold voltage
VDS = 5 V; VG2-S = 4 V; ID = 100 µA
0.3
1
V
VG2-S(th)
gate-source threshold voltage
VDS = 5 V; VG1-S = 4 V; ID = 100 µA
0.3
1.2
V
IDSX
drain-source current
amp. a:
VG2-S = 4 V; VDS = 5 V; RG = 62 kΩ; note 1
11
19
mA
amp. b:
8
VG2-S = 4 V; VDS = 5 V; RG = 120 kΩ; note 1
16
mA
IG1-S
gate cut-off current
VG1-S = 5 V; VG2-S = VDS = 0
−
50
nA
IG2-S
gate cut-off current
VG2-S = 5 V; VG1-S = VDS = 0
−
20
nA
Note
1. RG1 connects gate 1 to VGG = 5 V.
2001 Apr 25
4
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1203
DYNAMIC CHARACTERISTICS AMPLIFIER a
Common source; Tamb = 25 °C; VG2-S = 4 V; VDS = 5 V; ID = 15 mA; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
yfs
forward transfer admittance
pulsed; Tj = 25 °C
23
28
35
mS
Cig1-ss
input capacitance at gate 1
f = 1 MHz
−
2.6
3.1
pF
Cig2-ss
input capacitance at gate 2
f = 1 MHz
−
3
−
pF
Coss
output capacitance
f = 1 MHz
−
0.9
−
pF
Crss
reverse transfer capacitance f = 1 MHz
−
15
30
fF
F
noise figure
f = 10.7 MHz; GS = 20 mS; BS = 0
−
5
7
dB
f = 400 MHz; YS = YS opt
−
1
1.8
dB
f = 800 MHz; YS = YS opt
−
1.9
2.5
dB
f = 200 MHz; GS = 2 mS; BS = BS opt;
GL = 0.5 mS; BL = BL opt; note 1
−
32.5
−
dB
f = 400 MHz; GS = 2 mS; BS = BS opt;
GL = 1 mS; BL = BL opt; note 1
−
27
−
dB
f = 800 MHz; GS = 3.3 mS; BS = BS opt;
GL = 1 mS; BL = BL opt; note 1
−
21
−
dB
Gtr
Xmod
power gain
cross-modulation
input level for k = 1%; fw = 50 MHz;
funw = 60 MHz; note 2
at 0 dB AGC
90
−
−
dBµV
at 10 dB AGC
−
95
−
dBµV
at 40 dB AGC
105
−
−
dBµV
Notes
1. Calculated from measured s-parameters.
2. Measured in Fig.35 test circuit.
2001 Apr 25
5
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1203
MCD935
25
handbook, halfpage
VG2-S = 4 V
ID
(mA)
MCD936
24
handbook, halfpage
3.5 V
3V
VG1-S = 1.8 V
ID
(mA)
20
2.5 V
1.7 V
16
1.6 V
15
1.5 V
2V
1.4 V
10
8
1.3 V
1.2 V
1.5 V
5
1V
0
0
0.5
0
1
1.5
0
2
2.5
VG1-S (V)
Amplifier a
VDS = 5 V.
Tj = 25 °C.
2
4
6
8
10
VDS (V)
Amplifier a
VG2-S = 4 V.
Tj = 25 °C.
Fig.3 Transfer characteristics; typical values.
Fig.4 Output characteristics; typical values.
MCD937
100
handbook, halfpage
VG2-S = 4 V
IG1
(µA)
MCD938
40
handbook, halfpage
3.5 V
yfs
(mS)
80
VG2-S = 4 V
30
3V
3.5 V
60
2.5 V
20
2V
10
3V
40
2.5 V
20
2V
1.5 V
0
0
0.5
0
1
1.5
0
2
2.5
VG1-S (V)
5
Amplifier a
VDS = 5 V.
Tj = 25 °C.
Amplifier a
VDS = 5 V.
Tj = 25 °C.
Fig.5
Fig.6
Gate 1 current as a function of gate 1
voltage; typical values.
2001 Apr 25
6
10
15
20
25
ID (mA)
Forward transfer admittance as a function
of drain current; typical values.
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1203
MCD939
16
MCD940
20
ID
handbook, halfpage
handbook, halfpage
ID
(mA)
(mA)
16
12
12
8
8
4
4
0
0
0
10
20
30
40
50
IG1 (µA)
1
0
2
3
4
Amplifier a
VDS = 5 V; VG2-S = 4 V.
Tj = 25 °C.
Amplifier a
VDS = 5 V; VG2-S = 4 V; Tj = 25 °C.
RG1 = 62 kΩ (connected to VGG); see Fig.35.
Fig.7
Fig.8
Drain current as a function of gate 1 current;
typical values.
MCD941
25
handbook, halfpage
47 kΩ
56 kΩ
20
Drain current as a function of gate 1 supply
voltage (= VGG); typical values.
MCD942
20
handbook, halfpage
68 kΩ
RG1 = 39 kΩ
ID
(mA)
ID
(mA)
82 kΩ
VGG = 5 V
16
62 kΩ
5
VGG (V)
100 kΩ
4.5 V
4V
12
15
3.5 V
10
8
5
4
3V
0
0
2
0
4
6
0
8
10
VGG = VDS (V)
2
4
VG2-S (V)
Amplifier a
VG2-S = 4 V; Tj = 25 °C.
RG1 connected to VGG; see Fig.35.
Amplifier a
VDS = 5 V; Tj = 25 °C.
RG1 = 62 kΩ (connected to VGG); see Fig.35.
Fig.9
Fig.10 Drain current as a function of gate 2
voltage; typical values.
Drain current as a function of gate 1 (= VGG)
and drain supply voltage; typical values.
2001 Apr 25
7
6
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1203
MCD943
60
IG1
(µA)
MCD944
0
VGG = 5 V
handbook, halfpage
handbook,
gain halfpage
reduction
(dB)
−10
4.5 V
4V
40
−20
3.5 V
3V
−30
20
−40
−50
0
0
2
4
VG2-S (V)
6
0
1
2
3
VAGC (V)
4
Amplifier a
VDS = 5 V; Tj = 25 °C.
RG1 = 62 kΩ (connected to VGG); see Fig.35.
Amplifier a
VDS = 5 V; VGG = 5 V; RG1 = 62 kΩ;
f = 50 MHz; Tamb = 25 °C.
Fig.11 Gate 1 current as a function of gate 2
voltage; typical values.
Fig.12 Typical gain reduction as a function of the
AGC voltage; see Fig.35.
MCD945
120
MCD946
20
handbook, halfpage
handbook, halfpage
ID
(mA)
Vunw
(dBµV)
16
110
12
100
8
90
4
80
0
0
10
20
30
40
50
gain reduction (dB)
0
10
20
30
40
50
gain reduction (dB)
Amplifier a
VDS = 5 V; VGG = 5 V; RG1 = 62 kΩ; f = 50 MHz;
funw = 60 MHz; Tamb = 25 °C.
Amplifier a
VDS = 5 V; VGG = 5 V; RG1 = 62 kΩ;
f = 50 MHz; Tamb = 25 °C.
Fig.13 Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical
values; see Fig.35.
Fig.14 Drain current as a function of gain
reduction; typical values; see Fig.35.
2001 Apr 25
8
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1203
MGT588
102
handbook, halfpage
MGT589
103
handbook, halfpage
−103
ϕ rs
(deg)
yis
(mS)
| yrs |
10
102
ϕrs
10
| yrs |
(µS)
−102
bis
g is
1
10−1
10
102
f (MHz)
1
10
103
102
−10
−1
103
f (MHz)
Amplifier a
VDS = 5 V; VG2 = 4 V.
ID = 15 mA; Tamb = 25 °C.
Amplifier a
VDS = 5 V; VG2 = 4 V.
ID = 15 mA; Tamb = 25 °C.
Fig.15 Input admittance as a function of frequency;
typical values.
Fig.16 Reverse transfer admittance and phase as
a function of frequency; typical values.
MGT590
102
handbook, halfpage
| yfs |
(mS)
MGT591
−102
10
handbook, halfpage
yos
(mS)
ϕ fs
| yfs |
(deg)
bos
1
ϕ fs
10
−10
10−1
1
10
102
f (MHz)
10−2
10
−1
103
gos
102
f (MHz)
Amplifier a
VDS = 5 V; VG2 = 4 V.
ID = 15 mA; Tamb = 25 °C.
Amplifier a
VDS = 5 V; VG2 = 4 V.
ID = 15 mA; Tamb = 25 °C.
Fig.17 Forward transfer admittance and phase as
a function of frequency; typical values.
Fig.18 Output admittance as a function of
frequency; typical values.
2001 Apr 25
9
103
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1203
Amplifier a scattering parameters
VDS = 5 V; VG2-S = 4 V; ID = 15 mA; Tamb = 25 °C
f
(MHz)
s11
s21
s12
s22
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
50
0.987
−5.12
2.67
174.07
0.0006
85.79
0.997
−1.72
100
0.983
−10.24
2.66
168.16
0.0012
83.27
0.996
−3.42
200
0.976
−20.37
2.61
156.64
0.0023
78.22
0.992
−6.77
300
0.946
−30.36
2.54
145.05
0.0030
73.26
0.986
−10.12
400
0.919
−40.15
2.47
134.13
0.0032
71.40
0.980
−13.33
500
0.885
−49.55
2.37
132.32
0.0029
74.34
0.972
−16.56
600
0.851
−58.50
2.26
113.25
0.0024
90.33
0.965
−19.74
700
0.815
−67.28
2.15
103.20
0.0023
129.94
0.960
−22.90
800
0.778
−75.03
2.02
93.78
0.0035
172.18
0.950
−26.05
900
0.747
−83.30
1.95
84.84
0.0070
171.55
0.951
−29.10
1000
0.710
−90.47
1.83
75.92
0.0104
172.88
0.947
−32.25
2001 Apr 25
10
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1203
DYNAMIC CHARACTERISTICS AMPLIFIER b
Common source; Tamb = 25 °C; VG2-S = 4 V; VDS = 5 V; ID = 12 mA; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
yfs
forward transfer admittance
pulsed; Tj = 25 °C
25
30
40
mS
Cig1-ss
input capacitance at gate 1
f = 1 MHz
−
1.7
2.2
pF
Cig2-ss
input capacitance at gate 2
f = 1 MHz
−
4
−
pF
Coss
output capacitance
f = 1 MHz
−
0.85
−
pF
Crss
reverse transfer capacitance f = 1 MHz
−
15
30
fF
F
noise figure
f = 10.7 MHz; GS = 20 mS; BS = 0
−
9
11
dB
f = 400 MHz; YS = YS opt
−
0.9
1.5
dB
f = 800 MHz; YS = YS opt
−
1.1
1.8
dB
f = 200 MHz; GS = 2 mS; BS = BS opt;
GL = 0.5 mS; BL = BL opt; note 1
−
34
−
dB
f = 400 MHz; GS = 2 mS; BS = BS opt;
GL = 1 mS; BL = BL opt; note 1
−
30
−
dB
f = 800 MHz; GS = 3.3 mS; BS = BS opt;
GL = 1 mS; BL = BL opt; note 1
−
25
−
dB
Gtr
Xmod
power gain
cross-modulation
input level for k = 1%; fw = 50 MHz;
funw = 60 MHz; note 2
at 0 dB AGC
90
−
−
dBµV
at 10 dB AGC
−
92
−
dBµV
at 40 dB AGC
100
105
−
dBµV
Notes
1. Calculated from measured s-parameters.
2. Measured in Fig.35 test circuit.
2001 Apr 25
11
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1203
MCD952
20
handbook, halfpage
VG2-S = 4 V
ID
(mA)
2.5 V
2V
3V
VG1-S = 1.5 V
ID
(mA)
3.5 V
16
MCD953
24
handbook, halfpage
1.4 V
16
12
1.3 V
1.2 V
1.5 V
8
1.1 V
8
1V
4
0.9 V
1V
0
0
0
0.4
0.8
1.2
0
1.6
2
VG1-S (V)
Amplifier b
VDS = 5 V.
Tj = 25 °C.
2
4
6
8
10
VDS (V)
Amplifier b
VG2-S = 4 V.
Tj = 25 °C.
Fig.19 Transfer characteristics; typical values.
Fig.20 Output characteristics; typical values.
MCD954
100
handbook, halfpage
VG2-S = 4 V
IG1
(µA)
MCD955
40
handbook, halfpage
3.5 V
3.5 V
yfs
(mS)
3V
80
VG2-S = 4 V
30
3V
60
2.5 V
20
2.5 V
40
2V
10
20
2V
1.5 V
1V
0
0
0.5
1
1.5
0
0
2
2.5
VG1-S (V)
4
8
12
16
20
ID (mA)
Amplifier b
VDS
DS = 5 V.
Tjj = 25 °C.
Amplifier b
VDS = 5 V.
Tj = 25 °C.
Fig.21 Gate 1 current as a function of gate 1
voltage; typical values.
Fig.22 Forward transfer admittance as a function
of drain current; typical values.
2001 Apr 25
12
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1203
MCD956
20
MCD957
16
handbook, halfpage
handbook, halfpage
(mA)
ID
(mA)
ID
16
12
12
8
8
4
4
0
0
0
10
20
30
40
50
IG1 (µA)
0
1
2
3
4
5
VGG (V)
Amplifier b
VDS = 5 V; VG2-S = 4 V.
Tj = 25 °C.
Amplifier b
VDS = 5 V; VG2-S = 4 V; Tj = 25 °C.
RG1 = 120 kΩ (connected to VGG); see Fig.35.
Fig.23 Drain current as a function of gate 1 current;
typical values.
Fig.24 Drain current as a function of gate 1 supply
voltage (= VGG); typical values.
MCD958
20
handbook, halfpage
RG1 = 68 kΩ
ID
(mA)
16
MCD959
16
handbook, halfpage
ID
(mA)
82 kΩ
VGG = 5 V
4.5 V
12
4V
100 kΩ
12
120 kΩ
3.5 V
150 kΩ
3V
8
180 kΩ
8
220 kΩ
4
4
0
0
0
2
4
6
VGG = VDS (V)
0
2
4
VG2-S (V)
Amplifier b
VG2-S = 4 V; Tj = 25 °C.
RG1 connected to VGG; see Fig.35.
Amplifier b
VDS = 5 V; Tj = 25 °C.
RG1 = 120 kΩ (connected to VGG); see Fig.35.
Fig.25 Drain current as a function of gate 1 (= VGG)
and drain supply voltage; typical values.
Fig.26 Drain current as a function of gate 2
voltage; typical values.
2001 Apr 25
13
6
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1203
MCD960
40
MCD961
0
handbook,
gain halfpage
handbook, halfpage
IG1
(µA)
reduction
(dB)
−10
VGG = 5 V
30
4.5 V
−20
4V
20
3.5 V
−30
3V
10
−40
−50
0
0
2
4
VG2-S (V)
6
0
1
2
3
VAGC (V)
4
Amplifier b
VDS = 5 V; Tj = 25 °C.
RG1 = 120 kΩ (connected to VGG); see Fig.35.
Amplifier b
VDS = 5 V; VGG = 5 V; RG1 = 120 kΩ;
f = 50 MHz; Tamb = 25 °C.
Fig.27 Gate 1 current as a function of gate 2
voltage; typical values.
Fig.28 Typical gain reduction as a function of the
AGC voltage; see Fig.35.
MCD962
120
MCD963
16
handbook, halfpage
handbook, halfpage
Vunw
(dBµV)
ID
(mA)
110
12
100
8
90
4
80
0
0
10
20
30
40
50
gain reduction (dB)
0
10
20
30
40
50
gain reduction (dB)
Amplifier b
VDS = 5 V; VGG = 5 V; RG1 = 120 kΩ;
f= 50 MHz; funw = 60 MHz; Tamb = 25 °C.
Amplifier b
VDS = 5 V; VGG = 5 V; RG1 = 120 kΩ;
f = 50 MHz; Tamb = 25 °C.
Fig.29 Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical
values; see Fig.35.
Fig.30 Drain current as a function of gain
reduction; typical values; see Fig.35.
2001 Apr 25
14
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1203
MGT592
102
handbook, halfpage
MGT593
103
handbook, halfpage
−103
ϕ rs
(deg)
yis
(mS)
| yrs|
10
102
ϕrs
10
| yrs|
(µS)
−102
bis
1
−10
g is
10−1
10
102
f (MHz)
1
10
103
102
−1
103
f (MHz)
Amplifier b
VDS = 5 V; VG2 = 4 V.
ID = 12 mA; Tamb = 25 °C.
Amplifier b
VDS = 5 V; VG2 = 4 V.
ID = 12 mA; Tamb = 25 °C.
Fig.31 Input admittance as a function of frequency;
typical values.
Fig.32 Reverse transfer admittance and phase as
a function of frequency; typical values.
MGT594
102
handbook, halfpage
| yfs |
MGT595
−102
10
handbook, halfpage
yos
(mS)
ϕ fs
| yfs |
(deg)
(mS)
bos
1
−10
10
ϕ fs
1
10
102
10−1
f (MHz)
10−2
10
−1
103
gos
102
f (MHz)
Amplifier b
VDS = 5 V; VG2 = 4 V.
ID = 12 mA; Tamb = 25 °C.
Amplifier b
VDS = 5 V; VG2 = 4 V.
ID = 12 mA; Tamb = 25 °C.
Fig.33 Forward transfer admittance and phase as
a function of frequency; typical values.
Fig.34 Output admittance as a function of
frequency; typical values.
2001 Apr 25
15
103
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1203
VAGC
handbook, full pagewidth
R1
10 kΩ
C1
4.7 nF
C3
4.7 nF
L1
C2
RGEN
50 Ω
R2
50 Ω
DUT
≈ 2.2 µH
RL
50 Ω
C4
4.7 nF
RG1
4.7 nF
VGG
VI
VDS
MGS315
Fig.35 Cross-modulation test set-up (for one MOS-FET).
Amplifier b scattering parameters
VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb = 25 °C
f
(MHz)
s21
s11
s12
s22
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
50
0.988
−3.30
2.93
166.05
0.0006
87.62
0.994
−1.45
100
0.987
−6.60
2.92
172.11
0.0013
86.02
0.993
−2.92
200
0.981
−13.19
2.90
164.49
0.0025
82.03
0.990
−5.72
300
0.969
−19.81
2.87
156.59
0.0036
76.76
0.986
−8.57
400
0.957
−26.42
2.84
149.17
0.0045
73.59
0.981
−11.32
500
0.941
−33.04
2.79
141.47
0.0051
71.13
0.975
−14.22
600
0.925
−39.44
2.73
134.25
0.0054
69.07
0.971
−17.04
700
0.907
−45.89
2.67
126.81
0.0055
68.03
0.966
−19.92
800
0.889
−51.93
2.60
119.56
0.0055
68.55
0.958
−22.77
900
0.827
−57.82
2.54
112.70
0.0048
69.87
0.957
−25.54
1000
0.853
−63.24
2.46
105.72
0.0042
78.19
0.954
−28.41
2001 Apr 25
16
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1203
PACKAGE OUTLINE
Plastic surface mounted package; 6 leads
SOT363
D
E
B
y
X
A
HE
6
v M A
4
5
Q
pin 1
index
A
A1
1
2
e1
3
bp
c
Lp
w M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
max
bp
c
D
E
e
e1
HE
Lp
Q
v
w
y
mm
1.1
0.8
0.1
0.30
0.20
0.25
0.10
2.2
1.8
1.35
1.15
1.3
0.65
2.2
2.0
0.45
0.15
0.25
0.15
0.2
0.2
0.1
OUTLINE
VERSION
SOT363
2001 Apr 25
REFERENCES
IEC
JEDEC
EIAJ
SC-88
17
EUROPEAN
PROJECTION
ISSUE DATE
97-02-28
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1203
DATA SHEET STATUS
DATA SHEET STATUS(1)
PRODUCT
STATUS(2)
DEFINITIONS
Objective data
Development
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data
Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
DEFINITIONS
DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2001 Apr 25
18
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1203
NOTES
2001 Apr 25
19
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SCA 72
© Philips Electronics N.V. 2001
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Printed in The Netherlands
613512/03/pp20
Date of release: 2001
Apr 25
Document order number:
9397 750 08296