DISCRETE SEMICONDUCTORS DATA SHEET BF1212; BF1212R; BF1212WR N-channel dual-gate MOS-FETs Product specification 2003 Nov 14 NXP Semiconductors Product specification BF1212; BF1212R; BF1212WR N-channel dual-gate MOS-FETs FEATURES PINNING Short channel transistor with high forward transfer admittance to input capacitance ratio PIN Low noise gain controlled amplifier Excellent low frequency noise performance Partly internal self-biasing circuit to ensure good cross-modulation performance during AGC and good DC stabilization. APPLICATIONS DESCRIPTION 1 source 2 drain 3 gate 2 4 gate 1 handbook, 2 columns 4 3 Gain controlled low noise VHF and UHF amplifiers for 5 V digital and analog television tuner applications. 1 DESCRIPTION Top view Enhancement type N-channel field-effect transistor with source and substrate interconnected. Integrated diodes between gates and source protect against excessive input voltage surges. The BF1212, BF1212R and BF1212WR are encapsulated in the SOT143B, SOT143R and SOT343R plastic packages respectively. handbook, 2 columns 3 MSB014 BF1212; marking code: LGp Fig.1 Simplified outline (SOT143B). 4 2 2 handbook, halfpage 3 4 2 1 1 Top view Top view MSB035 BF1212R; marking code: LKp MSB842 BF1212WR; marking code: ML Fig.2 Simplified outline (SOT143R). Fig.3 Simplified outline (SOT343R). QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDS drain-source voltage 6 ID drain current 30 mA Ptot total power dissipation 180 mW yfs forward transfer admittance 28 33 43 mS Cig1-ss input capacitance at gate 1 1.7 2.2 pF V Crss reverse transfer capacitance f = 1 MHz 15 30 fF F noise figure f = 800 MHz 1.1 1.8 dB Xmod cross-modulation input level for k = 1 % at 40 dB AGC 100 104 dBV Tj junction temperature 150 C 2003 Nov 14 2 NXP Semiconductors Product specification N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION BF1212 plastic surface mounted package; 4 leads SOT143B BF1212R plastic surface mounted package; reverse pinning; 4 leads SOT143R BF1212WR plastic surface mounted package; reverse pinning; 4 leads SOT343R LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS MIN. VDS drain-source voltage ID drain current (DC) IG1 gate 1 current IG2 gate 2 current Ptot total power dissipation MAX. UNIT 6 V 30 mA 10 mA 10 mA BF1212; BF1212R Ts 116 C; note 1 180 mW BF1212WR Ts 122 C; note 1 180 mW Tstg storage temperature 65 +150 C Tj junction temperature 150 C Note 1. Ts is the temperature of the soldering point of the source lead. THERMAL CHARACTERISTICS SYMBOL Rth j-s 2003 Nov 14 PARAMETER VALUE UNIT thermal resistance from junction to soldering point BF1212; BF1212R 185 K/W BF1212WR 155 K/W 3 NXP Semiconductors Product specification N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR MDB828 250 handbook, halfpage Ptot (mW) 200 (2) 150 (1) 100 50 0 0 50 100 150 Ts (°C) 200 (1) BF1212WR. (2) BF1212; BF1212R. Fig.4 Power derating curve. STATIC CHARACTERISTICS Tj = 25 C unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VG1-S = VG2-S = 0 V; ID = 10 A 6 V V(BR)G1-SS gate 1-source breakdown voltage VG2-S = VDS = 0 V; IG1-S = 10 mA 6 10 V V(BR)G2-SS gate 2-source breakdown voltage VG1-S = VDS = 0 V; IG2-S = 10 mA 6 10 V V(BR)DSS drain-source breakdown voltage V(F)S-G1 forward source-gate 1 voltage VG2-S = VDS = 0 V; IS-G1 = 10 mA 0.5 1.5 V V(F)S-G2 forward source-gate 2 voltage VG1-S = VDS = 0 V; IS-G2 = 10 mA 0.5 1.5 V VG1-S(th) gate 1-source threshold voltage VG2-S = 4 V; VDS = 5 V; ID = 100 A 0.3 1.0 V VG2-S(th) gate 2-source threshold voltage VG1-S = 5 V; VDS = 5 V; ID = 100 A 0.35 1.0 V IDSX drain-source current VG2-S = 4 V; VDS = 5 V; RG1 = 150 k; note 1 8 16 mA IG1-S gate 1 cut-off current VG2-S = VDS = 0 V; VG1-S = 5 V 50 nA IG2-S gate 2 cut-off current VG1-S = VDS = 0 V; VG2-S = 4 V 20 nA Note 1. RG1 connects G1 to VGG = 5 V. 2003 Nov 14 4 NXP Semiconductors Product specification N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR DYNAMIC CHARACTERISTICS Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 12 mA; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT yfs forward transfer admittance pulsed; Tj = 25 C 28 33 43 mS Cig1-ss input capacitance at gate 1 f = 1 MHz 1.7 2.2 pF Cig2-ss input capacitance at gate 2 f = 1 MHz 1.1 pF Coss output capacitance f = 1 MHz 0.9 pF Crss reverse transfer capacitance f = 1 MHz 15 30 fF F noise figure f = 11 MHz; GS = 20 mS; BS = 0 4 dB f = 400 MHz; YS = YS (opt) 0.9 1.6 dB f = 800 MHz; YS = YS (opt) 1.1 1.8 dB f = 200 MHz; GS = 2 mS; BS = BS (opt); GL = 0.5 mS; BL = BL (opt) 35 dB f = 400 MHz; GS = 2 mS; BS = BS (opt); GL = 1 mS; BL = BL (opt) 30 dB f = 800 MHz; GS = 3.3 mS; BS = BS (opt); GL = 1 mS; BL = BL (opt) 25 dB at 0 dB AGC 90 dBV at 10 dB AGC 89 dBV at 40 dB AGC 100 104 dBV Gtr Xmod power gain cross-modulation input level for k = 1%; fw = 50 MHz; funw = 60 MHz; note 1 Note 1. Measured in test circuit Fig.21. 2003 Nov 14 5 NXP Semiconductors Product specification N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR MLE233 30 handbook, halfpage (4) ID (2) (mA) (3) MLE234 32 (1) handbook, halfpage (1) ID (mA) (2) 24 (3) (5) 20 (4) (5) 16 (6) (6) 10 (7) 8 (8) (7) (9) 0 0 0.5 1 1.5 2 0 2.5 0 2 4 VG1-S (V) (1) VG2-S = 4 V. (2) VG2-S = 3.5 V. (3) VG2-S = 3 V. (4) VG2-S = 2.5 V. (5) VG2-S = 2 V. (6) VG2-S = 1.5 V. (7) VG2-S = 1 V. (1) VG1-S = 1.6 V. VDS = 5 V. Tj = 25 C. (2) (3) (4) (5) Fig.5 Transfer characteristics; typical values. VG1-S = 1.5 V. VG1-S = 1.4 V. VG1-S = 1.3 V. VG1-S = 1.2 V. (6) (7) (8) (9) VG1-S = 1.1 V. VG1-S = 1.0 V. VG1-S = 0.9 V. VG1-S = 0.8 V. VG2-S = 4 V. Tj = 25 C. Fig.6 Output characteristics; typical values. MLE235 100 IG1 handbook, halfpage (1) (μA) 6 VDS (V) MLE236 40 (3) handbook, halfpage (2) (2) (1) yfs (3) (mS) 80 (4) 30 (4) (5) 60 20 (5) 40 (6) 10 (6) 20 (7) (7) 0 0.5 0 1 (1) VG2-S = 4 V. (2) VG2-S = 3.5 V. (5) VG2-S = 2 V. (6) VG2-S = 1.5 V. (3) VG2-S = 3 V. (4) VG2-S = 2.5 V. (7) VG2-S = 1 V. Fig.7 0 2 1.5 VG1-S (V) 0 VDS = 5 V. Tj = 25 C. Gate 1 current as a function of gate 1 voltage; typical values. 2003 Nov 14 8 12 (1) VG2-S = 4 V. (2) VG2-S = 3.5 V. (5) VG2-S = 2 V. (6) VG2-S = 1.5 V. (3) VG2-S = 3 V. (4) VG2-S = 2.5 V. (7) VG2-S = 1 V. Fig.8 6 4 16 20 ID (mA) VDS = 5 V. Tj = 25 C. Forward transfer admittance as a function of drain current; typical values. NXP Semiconductors Product specification N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR MLE237 24 MLE238 16 handbook, halfpage handbook, halfpage ID ID (mA) (mA) 12 16 8 8 4 0 0 10 20 30 0 40 50 IG1 (μA) 0 1 2 3 4 5 VGG (V) VDS = 5 V; VG2-S = 4 V. Tj = 25 C. VDS = 5 V; VG2-S = 4 V; Tj = 25 C. RG1 = 150 k (connected to VGG); see Fig.21. Fig.9 Fig.10 Drain current as a function of gate 1 supply voltage; typical values. Drain current as a function of gate 1 current; typical values. MLE239 20 ID (mA) (1) handbook, halfpage 16 MLE240 16 (2) handbook, halfpage (3) ID (mA) (1) (2) (4) 12 (3) (5) 12 (4) (6) (7) (5) 8 (8) 8 4 4 0 0 2 (1) RG1 = 47 k. (5) RG1 = 120 k. (2) RG1 = 56 k. (3) RG1 = 82 k. (4) RG1 = 100 k. (6) RG1 = 150 k. (7) RG1 = 180 k. (8) RG1 = 220 k. 4 0 6 VGG = VDS (V) 0 VG2-S = 4 V; Tj = 25 C. RG1 connected to VGG; see Fig.21. (1) VGG = 5 V. (2) VGG = 4.5 V. (3) VGG = 4 V. Fig.11 Drain current as a function of gate 1 and drain supply voltage; typical values. 2003 Nov 14 2 (4) VGG = 3.5 V. (5) VGG = 3 V. 4 VG2-S (V) VDS = 5 V; Tj = 25 C. RG1 = 150 k (connected to VGG); see Fig.21. Fig.12 Drain current as a function of gate 2 voltage; typical values. 7 6 NXP Semiconductors Product specification N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR MLE241 30 MLE242 0 handbook, halfpage handbook, halfpage IG1 (μA) gain reduction (dB) (1) (2) −20 20 (3) (4) (5) −40 10 −60 0 0 2 (1) VGG = 5 V. (2) VGG = 4.5 V. (3) VGG = 4 V. 4 (4) VGG = 3.5 V. (5) VGG = 3 V. VG2-S (V) 6 0 1 2 VDS = 5 V; Tj = 25 C. RG1 = 150 k (connected to VGG); see Fig.21. VDS = 5 V; VGG = 5 V; RG1 = 150 k(connected to VGG); see Fig.21; f = 50 MHz; Tamb = 25 C. Fig.14 Typical gain reduction as a function of AGC voltage. MLE243 MLE244 16 handbook, halfpage handbook, halfpage Vunw (dBμV) ID (mA) 110 12 100 8 90 4 80 0 4 VAGC (V) Fig.13 Gate 1 current as a function of gate 2 voltage; typical values. 120 3 10 20 0 30 40 50 gain reduction (dB) 0 10 20 30 40 50 gain reduction (dB) VDS = 5 V; VGG = 5 V; RG1 = 150 k (connected to VGG); see Fig.21; f= 50 MHz; funw = 60 MHz; Tamb = 25 C. VDS = 5 V; VGG = 5 V; RG1 = 150 k (connected to VGG); see Fig.21; f= 50 MHz; Tamb = 25 C. Fig.15 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values. Fig.16 Drain current as a function of gain reduction; typical values. 2003 Nov 14 8 NXP Semiconductors Product specification N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR MLE245 102 handbook, halfpage MLE246 103 handbook, halfpage yis (mS) yrs (μS) 10 102 ϕrs (deg) ϕrs bis −102 yrs gis 1 10−1 10 −10 10 102 −103 1 10 103 f (MHz) −1 103 102 f (MHz) VDS = 5 V; VG2 = 4 V. ID = 12 mA; Tamb = 25 C. VDS = 5 V; VG2 = 4 V. ID = 12 mA; Tamb = 25 C. Fig.17 Input admittance as a function of frequency; typical values. Fig.18 Reverse transfer admittance and phase as functions of frequency; typical values. MLE247 102 handbook, halfpage yfs yfs −102 ϕfs (deg) (mS) 10 MLE248 10 handbook, halfpage yos (mS) −10 1 −1 10−1 10 bos ϕfs gos 1 10 102 f (MHz) 103 102 f (MHz) VDS = 5 V; VG2 = 4 V. ID = 12 mA; Tamb = 25 C. VDS = 5 V; VG2 = 4 V. ID = 12 mA; Tamb = 25 C. Fig.19 Forward transfer admittance and phase as functions of frequency; typical values. Fig.20 Output admittance as a function of frequency; typical values. 2003 Nov 14 9 103 NXP Semiconductors Product specification N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR VAGC handbook, full pagewidth R1 10 kΩ C1 4.7 nF C3 4.7 nF RGEN 50 Ω R2 50 Ω RL 50 Ω L1 C2 ≈ 2.2 μH DUT C4 4.7 nF RG1 4.7 nF VGG VI VDS MGS315 Fig.21 Cross-modulation test set-up. Table 1 f (MHz) Scattering parameters: VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb = 25 C s11 s21 s12 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) s22 ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) 50 0.990 3.39 3.288 176.5 0.0005 86.9 0.990 1.66 100 0.988 6.76 3.280 173.0 0.0011 85.6 0.990 3.30 200 0.983 13.40 3.261 166.1 0.0021 81.2 0.991 6.62 300 0.974 19.86 3.218 159.0 0.0030 77.5 0.991 9.92 400 0.969 26.46 3.205 152.6 0.0039 74.6 0.994 13.30 500 0.958 32.73 3.141 145.9 0.0045 72.4 0.994 16.56 600 0.947 38.83 3.086 139.5 0.0049 70.9 0.993 19.77 700 0.936 44.75 3.017 133.1 0.0051 69.5 0.991 22.78 800 0.924 50.51 2.949 126.9 0.0051 69.9 0.981 25.77 900 0.910 56.18 2.870 120.5 0.0049 69.8 0.984 28.72 1000 0.896 61.64 2.785 114.7 0.0045 72.7 0.980 31.77 Table 2 Noise data: VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb = 25 C opt f (MHz) Fmin (dB) (ratio) (deg) Rn () 400 0.9 0.695 13.87 28.5 800 1.1 0.634 30.30 32.85 2003 Nov 14 10 NXP Semiconductors Product specification N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR PACKAGE OUTLINES Plastic surface-mounted package; 4 leads SOT143B D B E A X y HE v M A e bp w M B 4 3 Q A A1 c 1 2 Lp b1 e1 detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp b1 c D E e e1 HE Lp Q v w y mm 1.1 0.9 0.1 0.48 0.38 0.88 0.78 0.15 0.09 3.0 2.8 1.4 1.2 1.9 1.7 2.5 2.1 0.45 0.15 0.55 0.45 0.2 0.1 0.1 OUTLINE VERSION REFERENCES IEC JEDEC JEITA ISSUE DATE 04-11-16 06-03-16 SOT143B 2003 Nov 14 EUROPEAN PROJECTION 11 NXP Semiconductors Product specification N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR Plastic surface-mounted package; reverse pinning; 4 leads D SOT143R B E A X y HE v M A e bp w M B 3 4 Q A A1 c 2 1 Lp b1 e1 detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A mm 1.1 0.9 OUTLINE VERSION SOT143R 2003 Nov 14 A1 max bp b1 c D E 0.1 0.48 0.38 0.88 0.78 0.15 0.09 3.0 2.8 1.4 1.2 e 1.9 e1 HE Lp Q v w y 1.7 2.5 2.1 0.55 0.25 0.45 0.25 0.2 0.1 0.1 REFERENCES IEC JEDEC JEITA SC-61AA 12 EUROPEAN PROJECTION ISSUE DATE 04-11-16 06-03-16 NXP Semiconductors Product specification N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR Plastic surface-mounted package; reverse pinning; 4 leads D SOT343R E B A X HE y v M A e 3 4 Q A A1 c 2 w M B 1 bp Lp b1 e1 detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp b1 c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.4 0.3 0.7 0.5 0.25 0.10 2.2 1.8 1.35 1.15 1.3 1.15 2.2 2.0 0.45 0.15 0.23 0.13 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 97-05-21 06-03-16 SOT343R 2003 Nov 14 EUROPEAN PROJECTION 13 NXP Semiconductors Product specification N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR DATA SHEET STATUS DOCUMENT STATUS(1) PRODUCT STATUS(2) DEFINITION Objective data sheet Development This document contains data from the objective specification for product development. Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the product specification. Notes 1. Please consult the most recently issued document before initiating or completing a design. 2. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. DEFINITIONS Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. DISCLAIMERS Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. 2003 Nov 14 14 NXP Semiconductors Product specification N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Quick reference data The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 2003 Nov 14 15 NXP Semiconductors provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management, Interface, Security and Digital Processing expertise Customer notification This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for package outline drawings which were updated to the latest version. Contact information For additional information please visit: http://www.nxp.com For sales offices addresses send e-mail to: [email protected] © NXP B.V. 2010 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R77/02/pp16 Date of release: 2003 Nov 14