LF PA K 56D BUK9K25-40E Dual N-channel 40 V, 29 mΩ logic level MOSFET 10 December 2013 Product data sheet 1. General description Dual logic level N-channel MOSFET in an LFPAK56D (Dual Power-SO8) package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use in high performance automotive applications. 2. Features and benefits • • • • • Dual MOSFET Q101 Compliant Repetitive avalanche rated Suitable for thermally demanding environments due to 175 °C rating True logic level gate with VGS(th) rating of greater than 0.5 V at 175 °C 3. Applications • • • • 12 V Automotive systems Motors, lamps and solenoid control Transmission control Ultra high performance power switching 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 40 V ID drain current VGS = 5 V; Tmb = 25 °C; Fig. 1 - - 18.2 A Ptot total power dissipation Tmb = 25 °C; Fig. 2 - - 32 W VGS = 5 V; ID = 5 A; Tj = 25 °C; Fig. 11 - 24 29 mΩ - 2.4 - nC Static characteristics FET1 and FET2 RDSon drain-source on-state resistance Dynamic characteristics FET1 and FET2 QGD gate-drain charge ID = 5 A; VDS = 32 V; VGS = 5 V; Tj = 25 °C; Fig. 13; Fig. 14 Scan or click this QR code to view the latest information for this product BUK9K25-40E NXP Semiconductors Dual N-channel 40 V, 29 mΩ logic level MOSFET 5. Pinning information Table 2. Pinning information Pin Symbol Description 1 S1 source1 2 G1 gate1 3 S2 source2 4 G2 gate2 5 D2 drain2 6 D2 drain2 7 D1 drain1 8 D1 drain1 Simplified outline 8 7 6 Graphic symbol 5 D1 D1 S1 D2 D2 G1 S2 G2 mbk725 1 2 3 4 LFPAK56D (SOT1205) 6. Ordering information Table 3. Ordering information Type number Package BUK9K25-40E Name Description Version LFPAK56D Plastic single ended surface mounted package (LFPAK56D); 8 leads SOT1205 7. Marking Table 4. Marking codes Type number Marking code BUK9K25-40E 92540E 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 40 V VDGR drain-gate voltage RGS = 20 kΩ - 40 V VGS gate-source voltage Tj ≤ 175 °C; Pulsed -15 15 V Tj ≤ 175 °C; DC -10 10 V Tmb = 25 °C; VGS = 5 V; Fig. 1 - 18.2 A Tmb = 100 °C; VGS = 5 V; Fig. 1 - 16.6 A Tmb = 25 °C; pulsed; tp ≤ 10 µs; Fig. 4 - 94 A ID IDM drain current peak drain current BUK9K25-40E Product data sheet All information provided in this document is subject to legal disclaimers. 10 December 2013 [1][2] © NXP N.V. 2013. All rights reserved 2 / 13 BUK9K25-40E NXP Semiconductors Dual N-channel 40 V, 29 mΩ logic level MOSFET Symbol Parameter Conditions Min Max Unit Ptot total power dissipation Tmb = 25 °C; Fig. 2 - 32 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Source-drain diode FET1 and FET2 IS source current Tmb = 25 °C - 18.2 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 94 A - 15 mJ Avalanche Ruggedness FET1 and FET2 EDS(AL)S non-repetitive drain-source avalanche energy [1] [2] [3] [4] ID (A) ID = 18.2 A; Vsup ≤ 40 V; VGS = 10 V; [3][4] Tj(init) = 25 °C; Fig. 3 Accumulated Pulse duration up to 50 hours delivers zero defect ppm. Significantly longer life times are achieved by lowering Tj and or VGS. Refer to application note AN10273 for further information Single-pulse avalanche rating limited by maximum junction temperature of 175 °C 003aak328 30 03aa16 120 Pder (%) 25 20 80 15 10 40 5 0 Fig. 1. 0 25 50 75 100 125 150 175 Tmb (°C) 0 200 Continuous drain current as a function of mounting base temperature BUK9K25-40E Product data sheet Fig. 2. 0 100 150 Tmb (°C) 200 Normalized total power dissipation as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. 10 December 2013 50 © NXP N.V. 2013. All rights reserved 3 / 13 BUK9K25-40E NXP Semiconductors Dual N-channel 40 V, 29 mΩ logic level MOSFET IAL (A) 003aak329 102 10 (1) (2) 1 (3) 10-1 10-2 10-3 Fig. 3. ID (A) 10-2 10-1 1 tAL (ms) 10 Avalanche rating; avalanche current as a function of avalanche time 003aak327 103 102 Limit RDSon = VDS / ID tp = 10 us 100 us 10 1 1 ms DC 10-1 10-1 Fig. 4. 1 10 ms 100 ms 10 102 VDS (V) Safe operating area; continuous and peak drain current as a function of drain-source voltage 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base Fig. 5 - - 4.68 K/W BUK9K25-40E Product data sheet All information provided in this document is subject to legal disclaimers. 10 December 2013 © NXP N.V. 2013. All rights reserved 4 / 13 BUK9K25-40E NXP Semiconductors Dual N-channel 40 V, 29 mΩ logic level MOSFET Symbol Parameter Conditions Min Typ Max Unit Rth(j-a) thermal resistance from junction to ambient Minimum footprint; mounted on a printed circuit board - 95 - K/W 003aaj557 10 Zth(j-mb) (K/W) δ = 0.5 0.2 1 0.1 0.05 0.02 10 P -1 single shot tp 10-2 10-6 Fig. 5. 10-5 10-4 10-3 10-2 tp T δ= 10-1 t T 1 tp (s) Transient thermal impedance from junction to mounting base as a function of pulse duration 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = -55 °C 36 - - V ID = 250 µA; VGS = 0 V; Tj = 25 °C 40 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C; 1.4 1.7 2.1 V 0.5 - - V - - 2.45 V VDS = 40 V; VGS = 0 V; Tj = 175 °C - - 500 µA VDS = 40 V; VGS = 0 V; Tj = 25 °C - 0.02 1 µA VGS = -10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 5 V; ID = 5 A; Tj = 25 °C; Fig. 11 - 24 29 mΩ VGS = 5 V; ID = 5 A; Tj = 175 °C; - 48.2 58 mΩ - 19 24 mΩ Static characteristics FET1 and FET2 V(BR)DSS VGS(th) Fig. 9; Fig. 10 ID = 1 mA; VDS = VGS; Tj = 175 °C; Fig. 9; Fig. 10 ID = 1 mA; VDS = VGS; Tj = -55 °C; Fig. 9; Fig. 10 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance Fig. 11; Fig. 12 VGS = 10 V; ID = 5 A; Tj = 25 °C; Fig. 11 BUK9K25-40E Product data sheet All information provided in this document is subject to legal disclaimers. 10 December 2013 © NXP N.V. 2013. All rights reserved 5 / 13 BUK9K25-40E NXP Semiconductors Dual N-channel 40 V, 29 mΩ logic level MOSFET Symbol Parameter Conditions Min Typ Max Unit Dynamic characteristics FET1 and FET2 QG(tot) total gate charge ID = 5 A; VDS = 32 V; VGS = 5 V; - 6.3 - nC QGS gate-source charge Tj = 25 °C; Fig. 13; Fig. 14 - 1.4 - nC QGD gate-drain charge - 2.4 - nC Ciss input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz; - 528 701 pF Coss output capacitance Tj = 25 °C; Fig. 15 - 95 114 pF Crss reverse transfer capacitance - 56 76 pF td(on) turn-on delay time VDS = 32 V; RL = 6.4 Ω; VGS = 5 V; - 6.2 - ns tr rise time RG(ext) = 5 Ω; Tj = 25 °C; ID = 5 A - 9.2 - ns td(off) turn-off delay time - 10.8 - ns tf fall time - 8.9 - ns Source-drain diode FET1 and FET2 VSD source-drain voltage IS = 5 A; VGS = 0 V; Tj = 25 °C; Fig. 16 - 0.83 1.2 V trr reverse recovery time IS = 5 A; dIS/dt = -100 A/µs; VGS = 0 V; - 15.9 - ns recovered charge VDS = 20 V; Tj = 25 °C - 7.6 - nC Qr ID (A) 003aak319 25 20 80 15 60 10 40 5 0 Fig. 6. 175°C 0 0.8 1.6 20 Tj = 25°C 2.4 3.2 VGS (V) Product data sheet 0 4 Transfer characteristics; drain current as a function of gate-source voltage; typical values BUK9K25-40E 003aak320 100 RDSon Fig. 7. 0 8 12 VGS (V) 16 Drain-source on-state resistance as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. 10 December 2013 4 © NXP N.V. 2013. All rights reserved 6 / 13 BUK9K25-40E NXP Semiconductors Dual N-channel 40 V, 29 mΩ logic level MOSFET ID (A) 003aak321 40 10 V 55VV 4.5 V 32 003aah025 3 VGS(th) (V) 2.5 max 2 VGS = 3.5 V 24 typ 1.5 16 2.8 V 8 0.5 2.6 V 0 2.4 V 0 1 2 3 VDS (V) 0 -60 4 Tj = 25 °C; tp = 300 μs Fig. 8. Output characteristics; drain current as a function of drain-source voltage; typical values Fig. 9. 003aah026 10-1 min 1 3V 0 180 Tj (° C) 003aak326 RDSon 10-2 120 Gate-source threshold voltage as a function of junction temperature 150 ID (A) 60 2.8 V 3V 3.5 V 120 min 10-3 typ max 90 10-4 4.5 V 60 5V 10-5 30 VGS = 10 V 10-6 0 1 2 V GS (V) 0 3 Fig. 10. Sub-threshold drain current as a function of gate-source voltage BUK9K25-40E Product data sheet 0 10 20 30 ID (A) 40 Tj = 25 °C; tp = 300 μs Fig. 11. Drain-source on-state resistance as a function of drain current; typical values All information provided in this document is subject to legal disclaimers. 10 December 2013 © NXP N.V. 2013. All rights reserved 7 / 13 BUK9K25-40E NXP Semiconductors Dual N-channel 40 V, 29 mΩ logic level MOSFET 003aaj814 2.4 VGS (V) a 003aak323 10 8 1.6 VDS = 14 V 6 32 V 4 0.8 2 0 -60 0 60 120 Tj ( °C) 0 180 Fig. 12. Normalized drain-source on-state resistance factor as a function of junction temperature 0 2.5 5 7.5 10 15 Fig. 13. Gate-source voltage as a function of gate charge; typical values 003aak324 103 C (pF) VDS 12.5 QG (nC) Ciss ID VGS(pl) VGS(th) Coss 102 VGS QGS1 Crss QGS2 QGS QGD QG(tot) 003aaa508 10 10-1 Fig. 14. Gate charge waveform definitions 1 10 VDS (V) 102 Fig. 15. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values BUK9K25-40E Product data sheet All information provided in this document is subject to legal disclaimers. 10 December 2013 © NXP N.V. 2013. All rights reserved 8 / 13 BUK9K25-40E NXP Semiconductors Dual N-channel 40 V, 29 mΩ logic level MOSFET IS (A) 003aak325 40 32 24 16 8 0 Tj = 25°C 175°C 0 0.2 0.4 0.6 0.8 1 VSD (V) 1.2 Fig. 16. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values BUK9K25-40E Product data sheet All information provided in this document is subject to legal disclaimers. 10 December 2013 © NXP N.V. 2013. All rights reserved 9 / 13 BUK9K25-40E NXP Semiconductors Dual N-channel 40 V, 29 mΩ logic level MOSFET 11. Package outline Plastic single ended surface mounted package (LFPAK56D); 8 leads E A SOT1205 A b1 c1 L1 mounting base D H D1 D2 L 1 2 3 e b (8x) 4 w X c A E1 E2 A1 C θ Lp detail X 0 2.5 A max 1.05 nom min mm 5 mm scale Dimensions Unit y C c c1 D(1) D1(1) A1 b b1 0.1 0.50 4.4 0.25 0.30 4.70 0.0 0.35 4.1 0.19 0.24 4.45 4.8 D2 (ref) 3.5 E(1) E1(1) 5.30 1.8 4.95 1.6 E2 0.85 e 1.27 H L L1 Lp 6.2 1.3 0.55 0.85 5.9 0.8 0.30 0.40 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. Outline version References IEC JEDEC JEITA w y θ 0.25 0.1 8° 0° sot1205_po European projection Issue date 13-02-19 13-02-21 SOT1205 Fig. 17. Package outline LFPAK56D (SOT1205) BUK9K25-40E Product data sheet All information provided in this document is subject to legal disclaimers. 10 December 2013 © NXP N.V. 2013. All rights reserved 10 / 13 BUK9K25-40E NXP Semiconductors Dual N-channel 40 V, 29 mΩ logic level MOSFET In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 12. 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This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. 10 December 2013 © NXP N.V. 2013. All rights reserved 11 / 13 BUK9K25-40E NXP Semiconductors Dual N-channel 40 V, 29 mΩ logic level MOSFET No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 12.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. BUK9K25-40E Product data sheet All information provided in this document is subject to legal disclaimers. 10 December 2013 © NXP N.V. 2013. All rights reserved 12 / 13 BUK9K25-40E NXP Semiconductors Dual N-channel 40 V, 29 mΩ logic level MOSFET 13. Contents 1 General description ............................................... 1 2 Features and benefits ............................................1 3 Applications ........................................................... 1 4 Quick reference data ............................................. 1 5 Pinning information ............................................... 2 6 Ordering information ............................................. 2 7 Marking ................................................................... 2 8 Limiting values .......................................................2 9 Thermal characteristics .........................................4 10 Characteristics ....................................................... 5 11 Package outline ................................................... 10 12 12.1 12.2 12.3 12.4 Legal information .................................................11 Data sheet status ............................................... 11 Definitions ...........................................................11 Disclaimers .........................................................11 Trademarks ........................................................ 12 © NXP N.V. 2013. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 10 December 2013 BUK9K25-40E Product data sheet All information provided in this document is subject to legal disclaimers. 10 December 2013 © NXP N.V. 2013. All rights reserved 13 / 13