LatticeECP2/M sysIO Usage Guide

LatticeECP2/M sysIO
Usage Guide
June 2013
Technical Note TN1102
Introduction
The LatticeECP2™ and LatticeECP2M™ sysIO™ buffers give the designer the ability to easily interface with other
devices using advanced system I/O standards. This technical note describes the sysIO standards available and
how they can be implemented using Lattice’s ispLEVER® design software.
sysIO Buffer Overview
LatticeECP2/M sysIO interface contains multiple Programmable I/O Cells (PIC) blocks. Each PIC contains two Programmable I/Os (PIO), PIOA and PIOB, connected to their respective sysIO Buffers. Two adjacent PIOs can be
joined to provide a differential I/O pair (labeled as “T” and “C”).
Each Programmable I/O (PIO) includes a sysIO Buffer and I/O Logic (IOLOGIC). The LatticeECP2/M sysIO buffers
supports a variety of single-ended and differential signaling standards. The sysIO buffer also supports the DQS
strobe signal that is required for interfacing with the DDR memory. One of every 16/18 PIOs in the LatticeECP2/M
contains a delay element to facilitate the generation of DQS signals. The DQS signal from the bus is used to strobe
the DDR data from the memory into input register blocks. For more information on the architecture of the sysIO buffer please refer to the LatticeECP2/M Family Data Sheet.
The IOLOGIC includes input, output and tristate registers that implement both single data rate (SDR) and double
data rate (DDR) applications along with the necessary clock and data selection logic. Programmable delay lines
and dedicated logic within the IOLOGIC are used to provide the required shift to incoming clock and data signals
and the delay required by DQS inputs in DDR memory. The DDR implementation in the IOLOGIC and the DDR
memory interface support are discussed in more detail in TN1105, LatticeECP2/M High-Speed I/O Interface.
Supported sysIO Standards
The LatticeECP2/M sysIO buffer supports both single-ended and differential standards. Single-ended standards
can be further subdivided into internally ratioed standard such as LVCMOS, LVTTL and PCI; and externally referenced standards such as HSTL and SSTL. The buffers support the LVTTL, LVCMOS 1.2, 1.5, 1.8, 2.5 and 3.3V
standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength,
bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch). Other single-ended standards supported
include SSTL and HSTL. Differential standards supported include LVDS, RSDS, BLVDS, LVPECL, differential
SSTL and differential HSTL. Tables 1 and 2 list the sysIO standards supported in LatticeECP2/M devices.
Table 9-1. Supported Input Standards
VREF (Nom.)
VCCIO1 (Nom.)
LVTTL
—
—
LVCMOS33
—
—
LVCMOS25
—
—
LVCMOS18
—
1.8
LVCMOS15
—
1.5
LVCMOS12
—
—
PCI 33
—
3.3
HSTL18 Class I, II
0.9
—
HSTL15 Class I
0.75
—
SSTL3 Class I, II
1.5
—
Input Standard
Single Ended Interfaces
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9-1
tn1102_02.0
LatticeECP2/M sysIO
Usage Guide
Table 9-1. Supported Input Standards (Continued)
Input Standard
SSTL2 Class I, II
VREF (Nom.)
VCCIO1 (Nom.)
1.25
—
SSTL18 Class I, II
0.9
—
GTL+2
1.0
—
Differential Interfaces
Differential SSTL18 Class I, II
—
—
Differential SSTL2 Class I, II
—
—
Differential SSTL3 Class I, II
—
—
Differential HSTL15 Class I
—
—
Differential HSTL18 Class I, II
—
—
LVDS, MLVDS, LVPECL, BLVDS, RSDS
—
—
1 When not specified, VCCIO can be set anywhere in the valid operating range.
2. GTL+ inputs can be supported using HSTL15 Class I inputs with VREF set to 1.0V and external VTT termination to 1.5V. Please see “sysIO
Buffer Configurations” on page 6 for implementation details.
Table 9-2. Supported Output Standards
Output Standard
Drive
VCCIO (Nom.)
4mA, 8mA, 12mA, 16mA, 20mA
3.3
LVCMOS33
4mA, 8mA, 12mA 16mA, 20mA
3.3
LVCMOS25
4mA, 8mA, 12mA, 16mA, 20mA
2.5
LVCMOS18
4mA, 8mA, 12mA, 16mA
1.8
LVCMOS15
4mA, 8mA
1.5
Single-ended Interfaces
LVTTL
LVCMOS12
2mA, 6mA
1.2
LVCMOS33, Open Drain
4mA, 8mA, 12mA 16mA, 20mA
—
LVCMOS25, Open Drain
4mA, 8mA, 12mA 16mA, 20mA
—
LVCMOS18, Open Drain
4mA, 8mA, 12mA 16mA
—
LVCMOS15, Open Drain
4mA, 8mA
—
LVCMOS12, Open Drain
2mA, 6mA
—
PCI33/PCIX
HSTL18 Class I
N/A
3.3
8mA, 12mA
1.8
HSTL18 Class II
N/A
1.8
HSTL15 Class I
4mA, 8mA
1.5
SSTL3 Class I, II
N/A
3.3
SSTL2 Class I
8mA, 12mA
2.5
SSTL2 Class II
16mA, 20mA
2.5
SSTL18 Class I
N/A
1.8
SSTL18 Class II
8mA, 12mA
1.8
Differential Interfaces
Differential SSTL3, Class I, II
N/A
3.3
Differential SSTL2, Class I
8mA, 12mA
2.5
Differential SSTL2, Class II
16mA, 20mA
2.5
Differential SSTL18, Class I
N/A
1.8
Differential SSTL18, Class II
8mA, 12mA
1.8
Differential HSTL18, Class I
8mA, 12mA
1.8
9-2
LatticeECP2/M sysIO
Usage Guide
Table 9-2. Supported Output Standards (Continued)
Output Standard
Drive
VCCIO (Nom.)
Differential HSTL18, Class II
N/A
1.8
Differential HSTL15, Class I
4mA, 8mA
1.5
LVDS
N/A
2.5
MLVDS1
N/A
2.5
BLVDS1
N/A
2.5
LVPECL1
N/A
3.3
N/A
2.5
RSDS
1
1. Emulated with external resistors.
sysIO Banking Scheme
LatticeECP2/M devices have eight general purpose programmable sysIO banks and a ninth configuration bank.
Each of the eight general purpose sysIO banks has a VCCIO supply voltage, and two reference voltages, VREF1 and
VREF2. Figure 9-1 shows the eight general purpose banks and the configuration bank with associated supplies.
Bank 8 is a bank dedicated to configuration logic and has seven dedicated configuration I/Os and 14 multiplexed
configuration I/Os. Bank 8 does have the power supply pads (VCCIO and VCCAUX) but does not have any independent VREF pads. The I/Os in Bank 8 are connected to VREF from Bank 3.
On the top and bottom banks, the sysIO buffer pair consists of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). The left and right sysIO buffer pair consists of two singleended output drivers and two sets of single-ended input buffers (both ratioed and referenced). The referenced input
buffer can also be configured as a differential input. In 50% of the pairs there is also one differential output driver.
The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive side
of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer.
9-3
LatticeECP2/M sysIO
Usage Guide
Figure 9-1. LatticeECP2M sysIO Banking
ULC SERDES
Only ECP2M70
& ECP2M100
Bank 0
Bank 1
URC
SERDES
Bank 7
Bank 2
Bank 3
Bank 6
Bank 8
(Dedicated &
Shared Config.)
LLC SERDES
Only ECP2M70 &
ECP2M100
Bank 5
Bank 4
LRC SERDES
Only ECP2M50 &
Bigger Devices
Note: URC = upper right corner, LRC = lower right corner,
ULC = upper left corner and LLC = lower left corner.
VCCIO (1.2V/1.5V/1.8V/2.5V/3.3V)
There are a total of eight VCCIO supplies, VCCIO0 - VCCIO7. Each bank has a separate VCCIO supply that powers the
single-ended output drivers and the ratioed input buffers such as LVTTL, LVCMOS, and PCI. LVTTL, LVCMOS3.3,
LVCMOS2.5 and LVCMOS1.2 also have fixed threshold options allowing them to be placed in any bank. The VCCIO
voltage applied to the bank determines the ratioed input standards that can be supported in that bank. It is also
used to power the differential output drivers. In addition, VCCIO8 is used to supply power to the sysCONFIG™ signals.
VCCAUX (3.3V)
In addition to the bank VCCIO supplies, devices have a VCC core logic power supply and a VCCAUX auxiliary supply
that powers the differential and referenced input buffers. VCCAUX is used to supply I/O reference voltage requiring
3.3V to satisfy the common-mode range of the drivers and input buffers.
VCCJ (1.2V/1.5V/1.8V/2.5V/3.3V)
The JTAG pins have a separate VCCJ power supply that is independent of the bank VCCIO supplies. VCCJ determines the electrical characteristics of the LVCMOS JTAG pins, both the output high level and the input threshold.
Table 9-3 shows a summary of all the required power supplies.
9-4
LatticeECP2/M sysIO
Usage Guide
Table 9-3. Power Supplies
Power Supply
Value1
Description
VCC
Core Power Supply
1.2V
VCCIO
Power Supply for the I/O and Configuration Banks
1.2V/1.5V/1.8V/2.5V/3.3V
VCCAUX
Auxiliary Power Supply
3.3V
VCCJ
Power Supply for JTAG Pins
1.2V/1.5V/1.8V/2.5V/3.3V
1. Refer to LatticeECP2/M Family Data Sheet for recommended min. and max. values.
Input Reference Voltage (VREF1, VREF2)
Each bank can support up to two separate VREF input voltages, VREF1 and VREF2, that are used to set the threshold for the referenced input buffers. The locations of these VREF pins are pre-determined within the bank. These
pins can be used as regular I/Os if the bank does not require a VREF voltage.
VREF1 for DDR Memory Interface
When interfacing to DDR memory, the VREF1 input must be used as the reference voltage for the DQS and DQ
input from the memory. A voltage divider between VREF1 and GND is used to generate an on-chip reference voltage that is used by the DQS transition detector circuit. This voltage divider is only present on VREF1 it is not available on VREF2. For more information on the DQS transition detect logic and its implementation, please refer to
TN1105, LatticeECP2/M High-Speed I/O Interface. DDR1 follows the SSTL25_II signaling specification and DDR2
follows the SSTL18_II signaling specification.
Mixed Voltage Support in a Bank
The LatticeECP2/M sysIO buffer is connected to three parallel ratioed input buffers. These three parallel buffers are
connected to VCCIO, VCCAUX and VCC, giving support for thresholds that track with VCCIO as well as fixed thresholds for 3.3V (VCCAUX) and 1.2V (VCC) inputs. This allows the input threshold for ratioed buffers to be assigned on
a pin-by-pin basis rather than tracking with VCCIO. This option is available for all 1.2V, 2.5V and 3.3V ratioed inputs
and is independent of the bank VCCIO voltage. For example, if the bank VCCIO is 1.8V, it is possible to have 1.2V
and 3.3V ratioed input buffers with fixed thresholds, as well as 2.5V ratioed inputs with tracking thresholds.
Prior to device configuration, the ratioed input thresholds always tracks the bank VCCIO. This option only takes
effect after configuration. Output standards within a bank are always set by VCCIO. Table 9-4 shows the sysIO standards that can be mixed in the same bank.
Table 9-4. Mixed Voltage Support
Input sysIO Standards
VCCIO
1.2V
1.2V
Yes
1.5V
Yes
1.8V
Yes
2.5V
Yes
3.3V
Yes
1.5V
1.8V
Yes
Yes
2.5V
Output sysIO Standards
3.3V
1.2V
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
9-5
1.5V
1.8V
2.5V
3.3V
Yes
Yes
Yes
Yes
LatticeECP2/M sysIO
Usage Guide
sysIO Standards Supported by Bank
Table 9-5. I/O Standards Supported by Bank
Description
Top Side
Banks 0-1
Right Side
Banks 2-3
Bottom Side
Banks 4-5
Left Side
Banks 6-7
I/O Buffers
Single-ended
Single-ended and
Differential
Single-ended
Single-ended and
Differential
Output Standards
Supported
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18 Class I, II
SSTL25 Class I, II
SSTL33 Class I, II
SSTL18 Class I, II
SSTL25 Class I, II
SSTL33 Class I, II
SSTL18 Class I, II
SSTL2 Class I, II
SSTL3 Class I, II
SSTL18 Class I, II
SSTL2 Class I, II
SSTL3 Class I, II
HSTL15 Class I
HSTL18_I, II
HSTL15 Class I
HSTL18 Class I, II
HSTL15 Class I
HSTL18 Class I, II
HSTL15 Class I, III
HSTL18 Class I, II, III
SSTL18D Class I, II
SSTL25D Class I, II
SSTL33D Class I, II
SSTL18D Class I, II
SSTL25D Class I, II
SSTL33D Class I, II
SSTL18D Class I, II
SSTL25D Class I, II,
SSTL33D Class I, II
SSTL18D Class I, II
SSTL25D Class I, II,
SSTL33D_I, II
HSTL15D Class I
HSTL18D Class I, II
HSTL15D Class I
HSTL18D Class I, II
HSTL15D Class I
HSTL18D Class I, II
HSTL15D Class I
HSTL18D Class I, II
LVDS25E1
LVPECL1
BLVDS1
RSDS1
LVDS
LVDS25E1
LVPECL1
BLVDS1
RSDS1
Inputs
All Single-ended,
Differential
All Single-ended,
Differential
All Single-ended,
Differential
All Single-ended,
Differential
Clock Inputs
All Single-ended,
Differential
All Single-ended,
Differential
All Single-ended,
Differential
All Single-ended,
Differential
PCI Support
PCI33 without clamp
PCI33 without clamp
PCI33 with clamp
PCI33 without clamp
PCI33 with clamp (ECP2M)
LVDS Output Buffers
PCI33
LVDS25E1
LVPECL1
BLVDS1
RSDS1
LVDS (3.5mA) Buffers2
LVDS
LVDS25E1
LVPECL1
BLVDS1
RSDS1
LVDS (3.5mA) Buffers2
1. These differential standards are implemented by using a complementary LVCMOS driver with external resistor pack.
2. Available only on 50% of the I/Os in the bank.
sysIO Buffer Configurations
All LVCMOS buffer have programmable pull, programmable drive and programmable slew configurations that can
be set in the software.
Bus Maintenance Circuit
Each pad has a weak pull-up, weak pull-down and weak buskeeper capability. The pull-up and pull-down settings
offer a fixed characteristic, which is useful in creating wired logic such as wired ORs. However, current can be
slightly higher than other options, depending on the signal state. The bus-keeper option latches the signal in the
last driven state, holding it at a valid level with minimal power dissipation. Users can also choose to turn off the bus
maintenance circuitry, minimizing power dissipation and input leakage. Note that in this case, it is important to
ensure that inputs are driven to a known state to avoid unnecessary power dissipation in the input buffer.
9-6
LatticeECP2/M sysIO
Usage Guide
Programmable Drive
Each LVCMOS or LVTTL, as well as some of the referenced (SSTL and HSTL) output buffers, has a programmable
drive strength option. This option can be set for each I/O independently. The drive strength settings available are
2mA, 4mA, 6mA, 8mA, 12mA, 16mA and 20mA. Actual options available vary by the I/O voltage. The user must
consider the maximum allowable current per bank and the package thermal limit current when selecting the drive
strength. Table 9-6 shows the available drive settings for each out the output standards.
Table 9-6. Programmable Drive Values for Single-ended Buffers
Single Ended I/O Standards
Programmable Drive (mA)
HSTL15_I/ HSTL15D_I
4, 8
HSTL18_I/ HSTL18D_I
8, 12
SSTL25_I/ SSTL25D_I
8, 12
SSTL25_II/ SSTL25D_II
16, 20
SSTL18_II/SSTL18D_II
8, 12
LVCMOS12
2, 6
LVCMOS15
4, 8
LVCMOS18
4, 8, 12, 16
LVCMOS25
4, 8, 12, 16, 20
LVCMOS33
4, 8, 12, 16, 20
LVTTL
4, 8, 12, 16, 20
Programmable Slew Rate
Each LVCMOS or LVTTL output buffer pin also has a programmable output slew rate control that can be configured
for either low noise or high-speed performance. Each I/O pin has an individual slew rate control. This allows
designers to specify slew rate control on a pin-by-pin basis. This slew rate control affects both the rising and falling
edges.
Open-Drain Control
All LVCMOS and LVTTL output buffers can be configured to function as open drain outputs. The user can implement an open drain output by turning on the OPENDRAIN attribute in the software.
Differential SSTL and HSTL Support
The single-ended driver associated with the complementary ‘C’ pad can optionally be driven by the complement of
the data that drives the single-ended driver associated with the true pad. This allows a pair of single-ended drivers
to be used to drive complementary outputs with the lowest possible skew between the signals. This is used for driving complementary SSTL and HSTL signals (as required by the differential SSTL and HSTL clock inputs on synchronous DRAM and synchronous SRAM devices respectively). This capability is also used in conjunction with offchip resistors to emulate LVPECL, and BLVDS output drivers.
PCI Support with Programmable PCICLAMP
Each sysIO buffer can be configured to support PCI33. The buffers on the bottom of the device (for LatticeECP2) or
on the left and bottom sides of the device (for LatticeECP2M) have an optional PCI clamp diode that may optionally
be specified in the ispLEVER design tools.
Programmable PCICLAMP can be turned ON or OFF. This option is available on each I/O independently on the
bottom side banks (for LatticeECP2) or on the left and bottom side banks (for LatticeECP2M).
9-7
LatticeECP2/M sysIO
Usage Guide
GTL+ Input Support
GTL+ inputs are supported using the HSTL15_I input standard with VREF set to 1.0V and external VTT termination set to 1.5V. GTL+ inputs implemented using this method can support the maximum speed listed for the HSTL
standard in the LatticeECP2/M Family Data Sheet . GTL+ outputs are not supported in the LatticeECP2 device.
Figure 9-2. GTL+ Input Buffer Emulation Using HSTL15 Input
VTT = 1.5V
z0
+
VREF = 1.0V
HSTL15
Programmable Input Delay
Each input can optionally be delayed before it is passed to the core logic or input registers. The primary use for the
input delay is to achieve zero hold time for the input registers when using a direct drive primary clock. To arrive at
zero hold time, the input delay will delay the data by at least as much as the primary clock injection delay. This
option can be turned ON or OFF for each I/O independently in the software using the FIXEDDELAY attribute. This
attribute is described in more detail in the software sysIO attribute section. Appendix A shows how this feature can
be enabled in the software using HDL attributes.
Software sysIO Attributes
sysIO attributes can be specified in the HDL, using the Preference Editor GUI or in the ASCII preference file (.prf)
file directly. Appendices A, B and C list examples of how these can be assigned using each of these methods. This
section describes each of these attributes in detail.
IO_TYPE
This is used to set the sysIO standard for an I/O. The VCCIO required to set these I/O standards are embedded in
the attribute names itself. There is no separate attribute to set the VCCIO requirements. Table 9-7 lists the available
I/O types.
9-8
LatticeECP2/M sysIO
Usage Guide
Table 9-7. IO_TYPE Attribute Values
sysIO Signaling Standard
IO_TYPE
DEFAULT
LVCMOS25
LVDS 2.5V
LVDS25
RSDS
RSDS
Emulated LVDS 2.5V
LVDS25E1
Bus LVDS 2.5V
BLVDS251
LVPECL 3.3V
LVPECL331
HSTL18 Class I and II
HSTL18_I, HTSL18_II
Differential HSTL 18 Class I and II
HSTL18D_I, HSTL18D_II
HSTL 15 Class I
HSTL15_I
Differential HSTL 15 Class I
HSTL15D_I
SSTL 33 Class I and II
SSTL33_I, SSTL33_II
Differential SSTL 33 Class I and II
SSTL33D_I, SSTL3D_II
SSTL 25 Class I and II
SSTL25_I,SSTL25_II
Differential SSTL 25 Class I and II
SSTL25D_I, SSTL25D_II
SSTL 18 Class I and II
SSTL18_I, SSTL18_II
Differential SSTL 18 Class I
SSTL18D_I,SSTL18D_II
LVTTL
LVTTL33
3.3V LVCMOS
LVCMOS33
2.5V LVCMOS
LVCMOS25
1.8V LVCMOS
LVCMOS18
1.5V LVCMOS
LVCMOS15
1.2V LVCMOS
LVCMOS12
3.3V PCI
PCI33
1. These differential standards are implemented by using a complementary 
LVCMOS driver with external resistor pack.
OPENDRAIN
LVCMOS and LVTTL I/O standards can be set to open drain configuration by using the OPENDRAIN attribute.
Values: ON, OFF
Default: OFF
DRIVE
The DRIVE attribute will set the programmable drive strength for the output standards that have programmable
drive capability
9-9
LatticeECP2/M sysIO
Usage Guide
Table 9-8. DRIVE Settings
Output Standard
DRIVE (mA)
Default (mA)
HSTL15_I/ HSTL15D_I
4, 8
8
HSTL18_I/ HSTL18D_I
8, 12
12
SSTL25_I/ SSTL25D_I
8, 12
8
SSTL25_II/ SSTL25D_II
16, 20
16
SSTL18_II/SSTL18D_II
8, 12
12
LVCMOS12
2, 6
6
LVCMOS15
4, 8
8
LVCMOS18
4, 8, 12, 16
12
LVCMOS25
4, 8, 12, 16, 20
12
LVCMOS33
4, 8, 12, 16, 20
12
LVTTL
4, 8, 12, 16, 20
12
PULLMODE
The PULLMODE attribute is available for all the LVTLL and LVCMOS inputs and outputs. This attribute can be
enabled for each I/O independently.
Values: UP, DOWN, NONE, KEEPER
Default: UP
Table 9-9. PULLMODE Values
PULL Options
PULLMODE Value
Pull-up (Default)
UP
Pull-down
DOWN
Bus Keeper
KEEPER
Pull Off
NONE
PCICLAMP
PCI33 inputs on the bottom of the device (for LatticeECP2) or on the left and bottom sides of the device (for
LatticeECP2M) have an optional PCI clamp that is enabled via the PCICLAMP attribute. The PCICLAMP is also
available for all LVCMOS33 and LVTTL inputs.
Values: ON, OFF
Default: OFF
Table 9-10. PCICLAMP Values
Input Type
PCICLAMP Value
PCI33
ON
LVCMOS33
OFF (default), ON
LVTTL
OFF (default), ON
SLEWRATE
The SLEWRATE attribute is available for all LVTTL and LVCMOS output drivers. Each I/O pin has an individual
slew rate control. This allows a designer to specify slew rate control on a pin-by-pin basis.
Values: FAST, SLOW
Default: FAST
9-10
LatticeECP2/M sysIO
Usage Guide
FIXEDDELAY
The FIXEDDELAY attribute is available to each input pin. This attribute, when enabled, is used to achieve zero hold
time for the input registers when using global clock. This attribute can only be assigned in the HDL source.
Values: TRUE, FALSE
Default: FALSE
INBUF
By default, all the unused input buffers are disabled. The INBUF attribute is used to enable the unused input buffers
when performing a boundary scan test. This is a global attribute and can be globally set to ON or OFF.
Values: ON, OFF
Default: OFF
DIN/DOUT
This attribute can be used to assign I/O registers. Using DIN will assert an input register and using the DOUT attribute will assert an output register. By default, the software will try to assign the I/O registers, if applicable. The user
can turn this OFF by using the synthesis attribute or by using the Preference Editor of the ispLEVER software.
These attributes can only be applied to registers.
LOC
This attribute can be used to make pin assignments to the I/O ports in the design. This attributes is only used when
the pin assignments are made in HDL source. Designers can also assign pins directly using the GUI in the Preference Editor of the ispLEVER software. The appendices explain this in further detail.
Design Considerations and Usage
This section discusses some of the design rules and considerations that must be taken into account when designing with the LatticeECP2/M sysIO buffer
Banking Rules
• If VCCIO or VCCJ for any bank is set to 3.3 V, it is recommended that it be connected to the same power supply as
VCCAUX, thus minimizing leakage.
• If VCCIO or VCCJ for any bank is set to 1.2V, it is recommended that it be connected to the same power supply as
VCC, thus minimizing leakage.
• When implementing DDR memory interfaces, the VREF1 of the bank is used to provide reference to the interface
pins and cannot be used to power any other referenced inputs.
• Only the bottom banks for LatticeECP2 (Banks 4 and 5) or left and bottom banks for LatticeECP2M (Banks 4, 5,
6 and 7) will support PCI clamps.
• All legal input buffers should be independent of bank VCCIO, except for 1.8V and 1.5V buffers, which require a
bank VCCIO of 1.8V and 1.5V.
Differential I/O Rules
• All banks can support LVDS input buffers. Only the banks on the right and left sides (Banks 2, 3, 6 and 7) will
support True Differential output buffers. The banks on the top and bottom will support the LVDS input buffers but
will not support True LVDS outputs. The user can use emulated LVDS output buffers on these banks.
• All banks support emulated differential buffers using external resistor pack and complementary LVCMOS drivers.
• Only 50% of the I/Os on the left and right sides can provide LVDS output buffer capability. LVDS can only be
assigned to the TRUE pad. The ispLEVER design tool will automatically assign the other I/Os of the differential
pair to the complementary pad. Refer to the device data sheet to see the pin listings for all LVDS pairs.
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Assigning VREF1/ VREF2 Groups for Referenced Inputs
Each bank has two dedicated VREF input pins, VREF1 and VREF2. Designers can group buffers to a particular VREF
rail, VREF1 or VREF2. This grouping is done by assigning a PGROUP VREF preference along with the LOCATE
PGROUP preference.
Preference Syntax
PGROUP <pgrp_name> [(VREF <vref_name>)+] (COMP <comp_name>)+;
LOCATE PGROUP <pgrp_name> BANK <bank_num>;
LOCATE VREF <vref_name> SITE <site_name>;
Example Showing VREF Groups
PGROUP “vref_pg1” VREF “ref1” COMP “ah(0)” COMP “ah(1)” COMP “ah(2)” COMP “ah(3)”
COMP “ah(4)” COMP “ah(5)” COMP “ah(6)” COMP “ah(7)”;
PGROUP “vref_pg2” VREF “ref2” COMP “al(0)” COMP “al(1)” COMP “al(2)” COMP “al(3)”
COMP “al(4)” COMP “al(5)” COMP “al(6)” COMP “al(7)”;
LOCATE VREF “ref1” SITE PR29C;
LOCATE VREF “ref2” SITE PR48B;
or
LOCATE PGROUP “ vref_pg1” BANK 2;
LOCATE PGROUP “ vref_pg2” BANK 2;
The example shows two VREF groups, “vref_pg1” assigned to VREF “ref1” and “vref_pg2” assigned to “ref2”. The
user must lock these VREF to either VREF1 or VREF2 using the LOCATE preference. Alternatively, users can designate to which bank the VREF group should be located. The software will then assign these to either the VREF1 or
VREF2 of the bank.
If the PGROUP VREF is not used, the software will automatically group all pins that need the same VREF reference
voltage. This preference is most useful when there is more than one bus that uses the same reference voltage and
the user wishes to associate each of these busses to different VREF resources.
Differential I/O Implementation
The LatticeECP2/M devices support a variety of differential standards as detailed in the following sections.
LVDS
True LVDS (LVDS25) drivers are available on 50% of the I/Os on the left and right side of the devices. LVDS input
support is provided on all sides of the device. All four sides of the device support LVDS using complementary LVCMOS drivers with external resistors (LVDS25E). Refer to the LatticeECP2/M Family Data Sheet for a detailed
explanation of these LVDS implementations.
BLVDS
All single-ended sysIO buffers pairs support the Bus-LVDS standard using complementary LVCMOS drivers with
external resistors. Please refer to the LatticeECP2/M Family Data Sheet for a detailed explanation of BLVDS implementation.
RSDS
All single-ended sysIO buffers pairs support RSDS standard using complementary LVCMOS drivers with external
resistors. Please refer to the LatticeECP2/M Family Data Sheet for a detailed explanation of RSDS implementation.
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LVPECL
All the sysIO buffers will support LVPECL inputs. LVPECL outputs are supported using complementary LVCMOS
driver with external resistors. Please refer to the LatticeECP2/M Family Data Sheet for a detailed explanation of
LVPECL implementation.
Differential SSTL and HSTL
All single-ended sysIO buffers pairs support differential SSTL and HSTL. Please refer to the LatticeECP2/M Family
Data Sheet for a detailed explanation of Differential HSTL and SSTL implementation.
Technical Support Assistance
e-mail:
[email protected]
Internet: www.latticesemi.com
Revision History
Date
Version
February 2006
01.0
Initial release.
Change Summary
September 2006
01.1
Updated to include LatticeECP2M support.
April 2007
01.2
Updated Supported Output Standards table.
June 2007
01.3
Updated VREF1 for DDR Memory Interface section.
June 2007
01.4
Updated sysIO Standards Supported by Bank table.
June 2007
01.5
Updated Power Supplies table.
Updated Banking Rules bullet list.
April 2008
01.6
Updated LatticeECP2M sysIO Banking diagram.
February 2009
01.7
Updated I/O Standards Supported by Bank table.
June 2010
01.8
Updated screen shots in Appendix B.
Updated document for Lattice Diamond design software support.
March 2011
01.9
Added support for GTL+ input standard using HSTL input buffer.
June 2013
02.0
Updated document with new corporate logo.
Updated Technical Support Assistance information.
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Appendix A. HDL Attributes for Synplicity® and Precision® RTL Synthesis
Using these HDL attributes, designers can assign the sysIO attributes directly in their source. The attribute definition and syntax for the appropriate synthesis vendor must be used. Below are a list of all the sysIO attributes, syntax and examples for Precision RTL Synthesis and Synplicity. This section only lists the sysIO buffer attributes for
these devices. You can refer to the Precision RTL Synthesis and Synplicity user manuals for a complete list of synthesis attributes. These manuals are available through the ispLEVER software Help system.
VHDL Synplicity/Precision RTL Synthesis
This section lists syntax and examples for all the sysIO Attributes in VHDL when using the Precision RTL Synthesis
or Synplicity synthesis tools.
Syntax
Table 9-11. VHDL Attribute Syntax for Synplicity and Precision RTL Synthesis
Attribute
Syntax
IO_TYPE
attribute IO_TYPE: string;
attribute IO_TYPE of Pinname: signal is “IO_TYPE Value”;
OPENDRAIN
attribute OPENDRAIN: string;
attribute OPENDRAIN of Pinname: signal is “OpenDrain Value”;
DRIVE
attribute DRIVE: string;
attribute DRIVE of Pinname: signal is “Drive Value”;
PULLMODE
attribute PULLMODE: string;
attribute PULLMODE of Pinname: signal is “Pullmode Value”;
PCICLAMP
attribute PCICLAMP: string;
attribute PCICLAMP of Pinname: signal is “PCIClamp Value”;
SLEWRATE
attribute PULLMODE: string;
attribute PULLMODE of Pinname: signal is “Slewrate Value”;
FIXEDDELAY
attribute FIXEDDELAY: string;
attribute FIXEDDELAY of Pinname: signal is “Fixeddelay Value”;
DIN
attribute DIN: string;
attribute DIN of Pinname: signal is “ ”;
DOUT
attribute DOUT: string;
attribute DOUT of Pinname: signal is “ ”;
LOC
attribute LOC: string;
attribute LOC of Pinname: signal is “pin_locations”;
Examples
IO_TYPE
--***Attribute Declaration***
ATTRIBUTE IO_TYPE: string;
--***IO_TYPE assignment for I/O Pin***
ATTRIBUTE IO_TYPE OF portA:
SIGNAL IS “PCI33”;
ATTRIBUTE IO_TYPE OF portB:
SIGNAL IS “LVCMOS33”;
ATTRIBUTE IO_TYPE OF portC:
SIGNAL IS “LVDS25”;
OPENDRAIN
--***Attribute Declaration***
ATTRIBUTE OPENDRAIN: string;
--***DRIVE assignment for I/O Pin***
ATTRIBUTE OPENDRAIN OF portB: SIGNAL IS “ON”;
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DRIVE
--***Attribute Declaration***
ATTRIBUTE DRIVE: string;
--***DRIVE assignment for I/O Pin***
ATTRIBUTE DRIVE OF portB: SIGNAL IS “20”;
PULLMODE
--***Attribute Declaration***
ATTRIBUTE PULLMODE : string;
--***PULLMODE assignment for I/O Pin***
ATTRIBUTE PULLMODE OF portA:
SIGNAL IS “DOWN”;
ATTRIBUTE PULLMODE OF portB:
SIGNAL IS “UP”;
PCICLAMP
--***Attribute Declaration***
ATTRIBUTE PCICLAMP: string;
--***PULLMODE assignment for I/O Pin***
ATTRIBUTE PCICLAMP OF portA:
SIGNAL IS “ON”;
SLEWRATE
--***Attribute Declaration***
ATTRIBUTE SLEWRATE : string;
--*** SLEWRATE assignment for I/O Pin***
ATTRIBUTE SLEWRATE OF portB: SIGNAL IS “FAST”;
FIXEDDELAY
--***Attribute Declaration***
ATTRIBUTE FIXEDDELAY: string;
--*** SLEWRATE assignment for I/O Pin***
ATTRIBUTE FIXEDDELAY OF portB: SIGNAL IS “TRUE”;
DIN/DOUT
--***Attribute Declaration***
ATTRIBUTE din : string;
ATTRIBUTE dout : string;
--*** din/dout assignment for I/O Pin***
ATTRIBUTE din OF input_vector: SIGNAL IS “ “;
ATTRIBUTE dout OF output_vector: SIGNAL IS “ “;
LOC
--***Attribute Declaration***
ATTRIBUTE LOC : string;
--*** LOC assignment for I/O Pin***
ATTRIBUTE LOC OF input_vector: SIGNAL IS “E3,B3,C3 “;
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Verilog Synplicity
This section lists syntax and examples for all the sysIO Attributes in Verilog using the Synplicity synthesis tool.
Syntax
Table 9-12. Verilog Synplicity Attribute Syntax
Attribute
Syntax
IO_TYPE
PinType PinName /* synthesis IO_TYPE=”IO_Type Value”*/;
OPENDRAIN
PinType PinName /* synthesis OPENDRAIN =”OpenDrain Value”*/;
DRIVE
PinType PinName /* synthesis DRIVE=”Drive Value”*/;
PULLMODE
PinType PinName /* synthesis PULLMODE=”Pullmode Value”*/;
PCICLAMP
PinType PinName /* synthesis PCICLAMP =” PCIClamp Value”*/;
SLEWRATE
PinType PinName /* synthesis SLEWRATE=”Slewrate Value”*/;
FIXEDDELAY
PinType PinName /* synthesis FIXEDDELAY=”Fixeddelay Value”*/;
DIN
PinType PinName /* synthesis DIN=” “*/;
DOUT
PinType PinName /* synthesis DOUT=” “*/;
LOC
PinType PinName /* synthesis LOC=”pin_locations “*/;
Examples
//IO_TYPE, PULLMODE, SLEWRATE and DRIVE assignment
output portB /*synthesis IO_TYPE=”LVCMOS33” PULLMODE =”UP” SLEWRATE =”FAST”
DRIVE =”20”*/;
output portC /*synthesis IO_TYPE=”LVDS25” */;
//OPENDRAIN
output portA /*synthesis OPENDRAIN =”ON”*/;
//PCICLAMP
output portA /*synthesis IO_TYPE=”PCI33” PULLMODE =”PCICLAMP”*/;
// Fixeddelay
input load /* synthesis FIXEDDELAY=”TRUE” */;
// Place the flip-flops near the load input
input load /* synthesis din=”” */;
// Place the flip-flops near the outload output
output outload /* synthesis dout=”” */;
//I/O pin location
input [3:0] DATA0 /* synthesis loc=”E3,B1,F3”*/;
//Register pin location
reg data_in_ch1_buf_reg3 /* synthesis loc=”R40C47” */;
//Vectored internal bus
reg [3:0] data_in_ch1_reg /*synthesis loc =”R40C47,R40C46,R40C45,R40C44” */;
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Verilog Precision
This section lists syntax and examples for all the sysIO Attributes in Verilog using the Precision RTL Synthesis tool.
Syntax
Table 9-13. Verilog Precision Attribute Syntax
Attribute
Syntax
IO_TYPE
//pragma attribute PinName IO_TYPE IO_TYPE Value
OPENDRAIN
// pragma attribute PinName OPENDRAIN OpenDrain Value
DRIVE
// pragma attribute PinName DRIVE Drive Value
PULLMODE
// pragma attribute PinName IO_TYPE Pullmode Value
PCICLAMP
// pragma attribute PinName PCICLAMP PCIClamp Value
SLEWRATE
// pragma attribute PinName IO_TYPE Slewrate Value
FIXEDDELAY
// pragma attribute PinName IO_TYPE Fixeddelay Value
LOC
// pragma attribute PinName LOC pin_location
Examples
//****IO_TYPE ***
//pragma attribute portA IO_TYPE PCI33
//pragma attribute portB IO_TYPE LVCMOS33
//pragma attribute portC IO_TYPE SSTL25_II
//*** Opendrain ***
//pragma attribute portB OPENDRAIN ON
//pragma attribute portD OPENDRAIN OFF
//*** Drive ***
//pragma attribute portB DRIVE 20
//pragma attribute portD DRIVE 8
//*** Pullmode***
//pragma attribute portB PULLMODE UP
//*** PCIClamp***
//pragma attribute portB PCICLAMP ON
//*** Slewrate ***
//pragma attribute portB SLEWRATE FAST
//pragma attribute portD SLEWRATE SLOW
// ***Fixeddelay***
// pragma attribute load FIXEDDELAY TRUE
//***LOC***
//pragma attribute portB loc E3
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Appendix B. sysIO Attributes Using the ispLEVER Design Planner User
Interface
Designers can assign sysIO buffer attributes using the Design Planner Spreadsheet View GUI available in the ispLEVER design tool. If you are using Lattice Diamond™ design software, refer to Appendix D. The Pin Attribute
Sheet list all the ports in a design and all the available sysIO attributes as preferences. By clicking on each of these
cells, a list of all the valid I/O preference for that port is displayed. Each column takes precedence over the next.
Therefore, when a particular IO_TYPE is chosen, the DRIVE, PULLMODE and SLEWRATE columns will only list
the valid combinations for that IO_TYPE. The pin locations can be locked using the pin location column of the Pin
Attribute sheet. Right-clicking on a cell will list the available pin locations. The Preference Editor will also conduct a
DRC check to search for any incorrect pin assignments.
Designers can enter DIN/DOUT preferences using the Cell Attributes sheet of the Preference Editor. All the preferences assigned using the Preference Editor are written into the preference file (.prf).
Figures 2 and 3 show the Pin Attribute sheet and the Cell Attribute sheet views of the preference editor. For further
information on how to use the Preference Editor, refer to the ispLEVER Help documentation in the Help menu
option of the software.
Figure 9-3. Pin Attributes Tab
Figure 9-4. Cell Attributes Tab
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Appendix C. sysIO Attributes Using Preference File (ASCII File)
Designers can enter sysIO attributes directly in the preference (.prf) file as sysIO buffer preferences. The PRF file is
an ASCII file containing two separate sections: a schematic section for those preferences created by the mapper or
translator, and a user section for preferences entered by the user. User preferences can be written directly into this
file. The synthesis attributes appear between the schematic start and schematic end of the file. The sysIO buffer
preferences can be entered after the schematic end line using the preference file syntax. Below are a list of sysIO
buffer preference syntax and examples.
IOBUF
This preference is used to assign the attribute IO_TYPE, PULLMODE, SLEWRATE and DRIVE.
Syntax
IOBUF [ALLPORTS | PORT <port_name> | GROUP <group_name>] (keyword=<value>)+;
where:
<port_name> = These are not the actual top-level port names, but should be the signal name attached to the port.
PIOs in the physical design (.ncd) file are named using this convention. Any multiple listings or wildcarding should
be done using GROUPs
Keyword = IO_TYPE, OPENDRAIN, DRIVE, PULLMODE, PCICLAMP, SLEWRATE.
Example
IOBUF PORT “port1” IO_TYPE=LVTTL33 OPENDRAIN=ON DRIVE=8 PULLMODE=UP
PCICLAMP =OFF SLEWRATE=FAST;
DEFINE GROUP “bank1” “in*” “out_[0-31]”;
IOBUF GROUP “bank1” IO_TYPE=SSTL18_II;
LOCATE
When this preference is applied to a specified component, it places the component at a specified site and locks the
component to the site. If applied to a specified macro instance, it places the macro’s reference component at a
specified site, places all of the macro’s pre-placed components (that is, all components that were placed in the
macro’s library file) in sites relative to the reference component, and locks all of these placed components at their
sites. This can also be applied to a specified PGROUP.
Syntax
LOCATE [COMP <comp_name> | MACRO <macro_name>] SITE <site_name>;
LOCATE PGROUP <pgroup_name> [SITE <site_name>; | REGION <region_name>;]
LOCATE PGROUP <pgroup_name> RANGE <site_1> [<site_2> | <count>] [<direction>] |
RANGE <chip_side> [<direction>];
LOCATE BUS < bus_name> ROW|COL <number>;
<bus_name> := string
<number> := integer
Note: If the comp_name, macro_name, or site_name begins with anything other than an alpha character (for example, “11C7”), you must enclose the name in quotes. Wildcard expressions are allowed in <comp_name>.
Examples
This command places the port Clk0 on the site A4:
LOCATE COMP “Clk0” SITE “A4”;
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This command places the component PFU1 on the site named R1C7:
LOCATE COMP “PFU1” SITE “R1C7”;
This command places bus1 on ROW 3 and bus2 on COL4
LOCATE BUS “bus1” ROW 3;
LOCATE BUS “bus2” COL 4;
USE DIN CELL
This preference specifies the given register to be used as an input flip-flop.
Syntax
USE DIN CELL <cell_name>;
where:
<cell_name> := string
Example
USE DIN CELL “din0”;
USE DOUT CELL
Specifies the given register to be used as an output flip-flop.
Syntax
USE DOUT CELL <cell_name>;
where:
<cell_name> := string
Example
USE DOUT CELL “dout1”;
PGROUP VREF
This preference is used to group all the components that need to be associated to one VREF pin within a bank.
Syntax
PGROUP <pgrp_name> [(VREF <vref_name>)+] (COMP <comp_name>)+;
LOCATE PGROUP <pgrp_name> BANK <bank_num>;
LOCATE VREF <vref_name> SITE <site_name>;
Example
PGROUP “vref_pg1” VREF “ref1” COMP “ah(0)” COMP “ah(1)” COMP “ah(2)” COMP “ah(3)”
COMP “ah(4)” COMP “ah(5)” COMP “ah(6)” COMP “ah(7)”;
PGROUP “vref_pg2” VREF “ref2” COMP “al(0)” COMP “al(1)” COMP “al(2)” COMP “al(3)”
COMP “al(4)” COMP “al(5)” COMP “al(6)” COMP “al(7)”;
LOCATE VREF “ref1” SITE PR29C;
LOCATE VREF “ref2” SITE PR48B;
or:
LOCATE PGROUP “ vref_pg1” BANK 2;
LOCATE PGROUP “ vref_pg2” BANK 2;
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Appendix D. Assigning sysIO Attributes Using Lattice Diamond Spreadsheet View
sysIO buffer attributes can be assigned using the Spreadsheet View available in the Lattice Diamond design software. The Port Assignments Sheet lists all the ports in a design and all the available sysIO attributes in multiple columns. Click on each of these cells for a list of all the valid I/O preferences for that port. Each column takes
precedence over the next. Therefore, when you choose a particular IO_TYPE, the columns for the DRIVE, PULLMODE, SLEWRATE and other attributes will only list the valid entries for that IO_TYPE.
Pin locations can be locked using the Pin column of the Port Assignments sheet or using the Pin Assignments
sheet. You can right-click on a cell and go to Assign Pins to see a list of available pins.
The Spreadsheet View also has an option to run a DRC check to check for any incorrect pin assignments. You can
enter the DIN/ DOUT preferences using the Cell Mapping Tab. All the preferences assigned using the Spreadsheet
View are written into the logical preference file (.lpf).
Figure 9-5 shows the Port Assignments Sheet of the Spreadsheet View. For further information on how to use the
Spreadsheet View, refer to the Diamond Help documentation, available in the Help menu option of the software.
Figure 9-5. Port Attributes Tab of the SpreadSheet View
Users can create a VREF pin using the Spreadsheet View as shown in Figure 9-6 and then assign VREF for a
bank using the VREF Column in the Ports Assignment Tab of the Spreadsheet View as shown in Figure 9-7. See
the Diamond online help for a detailed description of this setting.
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Figure 9-6. Creating a VREF in Spreadsheet View
Figure 9-7. Assigning VREF for an Input Port in Spreadsheet View
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