The following document contains information on Cypress products.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21361-4E
ASSP
Dual Serial Input
PLL Frequency Synthesizer
MB15F07SL
■ DESCRIPTION
The Fujitsu Semiconductor MB15F07SL is a serial input Phase Locked Loop (PLL) frequency synthesizer
with two 1100 MHz prescalers. The two 1100 MHz prescalers have a dual modulus division ratio of 128/129
or 64/65 enabling pulse swallowing operation.
The supply voltage range is between 2.4 V and 3.6 V. The MB15F07SL uses the latest BiCMOS process.
As a result, the supply current is typically 5 mA at 2.7 V. A refined charge pump supplies a well-balanced
output current of 1.5 mA or 6 mA. The charge pump current is selectable by serial data.
■ FEATURES
• High frequency operation
: PLL 1, 2: 1100 MHz Max
• Low power supply voltage
: VCC = 2.4 to 3.6 V
• Ultra Low power supply current : ICC = 5.0 mA Typ (VCC = 2.7 V, Ta = +25°C, in PLL1, 2 locking state)
ICC = 5.5 mA Typ (VCC = 3.0 V, Ta = +25°C, in PLL1, 2 locking state)
• Direct power saving function
: Power supply current in power saving mode
Typ 0.1 μA (VCC = 3.0 V, Ta = +25°C), Max 10 μA (VCC = 3.0 V)
• Dual modulus prescaler: 1100 MHz prescaler (64/65, 128/129)
• Serial input 14-bit programmable reference divider: R = 3 to 16,383
• Serial input programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 3 to 2,047
• Software selectable charge pump current
• On-chip phase control for phase comparator
• Operating temperature: Ta = –40 to +85°C
Copyright©2000-2012 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2012.3
MB15F07SL
■ PIN ASSIGNMENTS
16-pin SSOP
GND2
1
16
Clock
OSCIN
2
15
Data
GND1
3
14
LE
fin1
4
13
fin2
VCC1
5
12
VCC2
LD/fout
6
11
Xfin2
PS1
7
10
PS2
DO1
8
9
DO2
TOP
VIEW
(FPT-16P-M05)
2
DS04-21361-4E
MB15F07SL
■ PIN DESCRIPTIONS
Pin no.
SSOP-16
Pin
name
I/O
1
GND2
–
Ground for PLL 2 section.
2
OSCIN
I
The programmable reference divider input. TCXO should be connected with a AC
coupling capacitor.
3
GND1
–
Ground for the PLL 1 section.
4
fin1
I
Prescaler input pin for the PLL 1.
Connection to an external VCO should be via AC coupling.
5
VCC1
–
Power supply voltage input pin for the PLL 1 section.
O
Lock detect signal output (LD)/phase comparator monitoring
output (fout).
The output signal is selected by LDS bit in a serial data.
LDS bit = “H” ; outputs fout signal
LDS bit = “L” ; outputs LD signal
6
LD/fout
Descriptions
7
PS1
I
Power saving mode control for the PLL 1 section. This pin must be set at “L”
during Power-ON. (Open is prohibited.)
PS1 = “H” ; Normal mode
PS1 = “L” ; Power saving mode
8
Do1
O
Charge pump output for the PLL 1 section.
Phase characteristics of the phase detector can be selected via programming of
the FC-bit.
9
Do2
O
Charge pump output for the PLL 2 section.
Phase characteristics of the phase detector can be selected via programming of
the FC-bit.
10
PS2
I
Power saving mode control for the PLL 2 section. This pin must be set at “L”
during Power-ON. (Open is prohibited.)
PS2 = “H” ; Normal mode
PS2 = “L” ; Power saving mode
11
Xfin2
I
Prescaler complementary input for the PLL 2 section.
This pin should be grounded via a capacitor.
12
VCC2
–
Power supply voltage input pin for the PLL 2 section, the shift register and the
oscillator input buffer. When power is OFF, latched data of PLL 2 is lost.
13
fin2
I
Prescaler input pin for the PLL 2.
Connection to an external VCO should be via AC coupling.
14
LE
I
Load enable signal inpunt (with a schmitt trigger input buffer.)
When the LE bit is set “H”, data in the shift register is transferred to the
corresponding latch according to the control bit in the serial data.
15
Data
I
Serial data input (with a schmitt trigger input buffer.)
Data is transferred to the corresponding latch (PLL 1-ref counter, PLL 1-prog.
counter, PLL 2-ref. counter, PLL 2-prog. counter) according to the control bit in
the serial data.
16
Clock
I
Clock input for the 23-bit shift register (with a schmitt trigger input buffer.)
One bit of data is shifted into the shift register on a rising edge of the clock.
DS04-21361-4E
3
MB15F07SL
■ BLOCK DIAGRAM
VCC1 GND1
5
3
PS1 7
fin1 4
Intermittent
mode control
(PLL 1)
3-bit latch
7-bit latch
11-bit latch
LDS SW1 FC1
Binary 7-bit
swallow counter
(PLL 1)
Binary 11-bit
programmable
counter (PLL 1)
fp1
Charge Current
pump Switch
(PLL 1)
Phase
comp.
(PLL 1)
8 Do1
Lock
Det.
Prescaler
(PLL 1)
64/65, 128/129
(PLL 1)
2-bit latch
T1
T2
14-bit latch
1-bit latch
Binary 14-bit
programmable ref.
counter (PLL 1)
C/P setting
current CP
LD1
fr1
OSCIN 2
AND
fr2
T1
OR
T2
2-bit latch
fin2 13
Xfin2 11
PS2 10
C/P setting
current CP
14-bit latch
1-bit latch
LD
fr1
fr2
fp1
fp2
Intermittent
mode control
(PLL 2)
Schmitt
circuit
Data 15
Schmitt
circuit
Schmitt
circuit
LDS SW2 FC2
Binary 7-bit
swallow counter
(PLL 2)
Binary 11-bit
programmable
counter (PLL 2)
3-bit latch
7-bit latch
11-bit latch
Phase
comp.
(PLL 2)
Charge Current
pump switch
9 Do2
(PLL 2)
fp2
Latch selector
C C
N N
1 2
23-bit shift register
12
VCC2
4
6 LD/
fout
Lock
Det.
(PLL 2)
Prescaler
(PLL 2)
64/65, 128/129
LE 14
Clock 16
Binary 14-bit
programmable ref.
counter (PLL 2)
Selector
1
GND2
DS04-21361-4E
MB15F07SL
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Symbol
Unit
Min
Max
VCC
–0.5
+4.0
V
Input voltage
VI
–0.5
VCC+0.5
V
Output voltage
VO
GND
VCC
V
Tstg
–55
+125
°C
Power supply voltage
Storage temperature
Remark
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Unit
Min
Typ
Max
VCC
2.4
3.0
3.6
V
Input voltage
VI
GND
–
VCC
V
Operating temperature
Ta
–40
–
+85
°C
Power supply voltage
Remark
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
DS04-21361-4E
5
MB15F07SL
■ ELECTRICAL CHARACTERISTICS
(VCC = 2.4 V to 3.6 V, Ta = –40 to +85°C)
Parameter
Symbol
“H” level input
voltage
“L” level input
voltage
“H” level input
voltage
“L” level input
voltage
“H” level input
current
“L” level input
current
“H” level input
current
“L” level input
current
“H” level output
voltage
“L” level output
voltage
“H” level output
voltage
“L” level output
voltage
High impedance
cutoff current
“H” level output
current
“L” level output
current
Unit
Typ
Max
PLL 1, PLL 2 total,
fin1 = fin2 = 1100 MHz,
VCC1 = VCC2 = 2.7 V
(VCC1 = VCC2 = 3.0 V)
–
5.0
(5.5)
–
mA
IPS
PS1 = PS2 = “L”
–
0.1*2
10
μA
fin1*3
fin1
PLL 1
100
–
1100
MHz
fin2
fin2
PLL 2
100
–
1100
MHz
OSCIN
fosc
3
–
40
MHz
fin1
Pfin1
PLL 1, 50 Ω system
–15*8
–
+2
dBm
fin2
Pfin2
PLL 2, 50 Ω system
8
–
+2
dBm
OSCIN
VOSC
VCC
Vp-p
Data,
Clock,
LE
VIH
Schmitt trigger input
VCC × 0.7
+ 0.4
–
–
VIL
Schmitt trigger input
–
–
VCC × 0.3
– 0.4
ICC*1
Power saving current
Input sensitivity
Value
Min
Power supply current*1
Operating
frequency
Condition
*3
PS1,
PS2
Data,
Clock,
LE,
PS1, PS2
–
–
–15*
0.5
VIH
–
VCC × 0.7
–
–
VIL
–
–
–
VCC × 0.3
IIH*4
–
–1.0
–
+1.0
IIL*4
–
–1.0
–
+1.0
IIH
–
0
–
+100
IIL*4
–
–100
–
0
VCC – 0.4
–
–
–
–
0.4
VCC – 0.4
–
–
V
μA
μA
OSCIN
VOH
VCC = 3.0 V, IOH = –1 mA
VOL
VCC = 3.0 V, IOL = 1 mA
VDOH
VCC = 3.0 V, IDOH = –0.5 mA
VDOL
VCC = 3.0 V, IDOL = 0.5 mA
–
–
0.4
IOFF
VCC = 3.0 V,
VOFF = 0.5 V to VCC – 0.5 V
–
–
2.5
IOH*4
VCC = 3.0 V
–
–
–1.0
IOL*4
VCC = 3.0 V
1.0
–
–
V
LD/fout
Do1
Do2
Do1
Do2
V
V
nA
mA
LD/fout
(Continued)
6
DS04-21361-4E
MB15F07SL
(Continued)
(VCC = 2.4 to 3.6 V, Ta = –40 to +85°C)
Parameter
“H” level output
current
“L” level output
current
Charge pump
current rate
Symbol
IDOH*4
Do1
Do2
Min
Typ
Max
–
–6.0
–
–
–1.5
–
CS bit = “H”
–
6.0
–
CS bit = “L”
–
1.5
–
VCC = 3.0 V, CS bit = “H”
VDOH = VCC/2,
CS bit = “L”
Ta = +25°C
VCC = 3.0 V,
VDOL= VCC/2,
Ta = +25°C
IDOL
Value
Condition
Unit
mA
IDOL/IDOH
IDOMT*
VDO = VCC/2
–
3
–
%
vs VDO
IDOVD*6
0.5 V ≤ VDO ≤ VCC – 0.5 V
–
10
–
%
vs Ta
IDOTA*7
–40°C ≤ Ta ≤ +85°C,
VDO = VCC/2
–
10
–
%
5
*1 : Conditions; fosc = 12 MHz, Ta = +25°C, in locking state.
*2 : VCC1 = VCC2 = 3.0 V, fosc = 12.8 MHz, Ta = +25°C, in power saving mode.
*3 : AC coupling. 1000pF capacitor is connected under the condition of minimum operating frequency.
*4 : The symbol “–” (minus) means direction of current flow.
*5 : VCC = 3.0 V, Ta = +25°C (|I3| – |I4|)/[(|I3| + |I4|)/2] × 100(%)
*6 : VCC = 3.0 V, Ta = +25°C [(|I2| – |I1|)/2]/[(|I1| + |I2|)/2] × 100(%) (Applied to each IDOL, IDOH)
*7 : VCC = 3.0 V, [|IDO(+85°C) – IDO(–40°C)|/2]/[|IDO(+85°C) + IDO(–40°C)|/2] × 100(%) (Applied to each IDOL, IDOH)
*8 :
fin1
Prescaler divided ratio
64/65
128/129
fin2
Prescaler divided ratio
64/65
128/129
Charge pump current
1.5 mA mode
6.0 mA mode
1.5 mA mode
6.0 mA mode
Charge pump current
1.5 mA mode
6.0 mA mode
1.5 mA mode
6.0 mA mode
I1
I3
I2
IDOL
IDOH
Vfin1(min)
–10 dBm
–10 dBm
–15 dBm
–15 dBm
Vfin2(min)
–15 dBm
–10 dBm
–15 dBm
–15 dBm
I4
I2
I1
0.5
VCC/2
VCC - 0.5
VCC
Charge Pump Output Voltage (V)
DS04-21361-4E
7
MB15F07SL
■ FUNCTIONAL DESCRIPTION
The divide ratio can be calculated using the following equation:
fVCO = {(M × N) + A} × fOSC ÷ R (A < N)
fVCO :
Output frequency of external voltage controlled oscillator (VCO)
M :
Preset divide ratio of dual modulus prescaler (64 or 128 for PLL 1/PLL 2)
N :
Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A
:
Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
fOSC :
Reference oscillation frequency
R :
Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of PLL 1/
PLL 2 sections, programmable reference dividers of PLL 1/PLL 2 sections are controlled individually.
Serial data of binary data is entered through Data pin.
On rising edge of Clock, one bit of serial data is transferred into the shift register. When the LE signal is
taken high, the data stored in the shift register is transferred to one of latch of them depending upon the
control bit data setting.
Table 1. Control Bit
Control bit
Destination of serial data
CN1
CN2
L
L
The programmable reference counter for the PLL 1
H
L
The programmable reference counter for the PLL 2
L
H
The programmable counter and the swallow counter for the PLL 1
H
H
The programmable counter and the swallow counter for the PLL 2
Shift Register Configuration
Programmable Reference Counter
LSB
MSB
Data Flow
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
N
1
C
N
2
T
1
T
2
R
1
R
2
R
3
R
4
R
5
R
6
CN1, CN2
R1 to R14
T1, T2
CS
X
R
7
R
8
R
9
R R R R R
10 11 12 13 14
C
S
X
X
X
X
: Control bit
[Table 1]
: Divide ratio setting bits for the programmable reference counter (3 to 16,383)[Table 2]
: Test purpose bit
[Table 3]
: Charge pump currnet select bit
[Table 9]
: Dummy bits (Set “0” or “1”)
NOTE: Data input with MSB first.
8
DS04-21361-4E
MB15F07SL
Programmable Counter
MSB
LSB
Data Flow
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
N
1
C
N
2
L
D
S
S
W
F
C
1/2
1/2
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
CN1, CN2: Control bit
N1 to N11: Divide ratio setting bits for the programmable counter (3 to 2,047)
A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)
SW1/SW2 : Divide ratio setting bit for the prescaler
(PLL 1 for the SW1, PLL 2 for the SW2)
FC1/FC2 : Phase control bit for the phase detector (PLL 1: FC1, PLL 2: FC2)
LDS
: LD/fout signal select bit
NOTE: Data input with MSB first.
N
9
N N
10 11
[Table 1]
[Table 4]
[Table 5]
[Table 6]
[Table 7]
[Table 8]
Table 2. Binary 14-bit Programmable Reference Counter Data Setting
Divide ratio
(R)
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
1
0
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note : Divide ratio less than 3 is prohibited.
Table 3. Test Purpose Bit Setting
T1
T2
LD/fout pin state
L
L
Outputs fr1.
H
L
Outputs fr2.
L
H
Outputs fp1.
H
H
Outputs fp2.
Table 4. Binary 11-bit Programmable Counter Data Setting
Divide ratio
(N)
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
3
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
1
0
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
2047
1
1
1
1
1
1
1
1
1
1
1
Note : Divide ratio less than 3 is prohibited.
DS04-21361-4E
9
MB15F07SL
Table 5. Binary 7-bit Swallow Counter Data Setting
Divide ratio
(N)
A7
A6
A5
A4
A3
A2
A1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
127
1
1
1
1
1
1
1
Note : Divide ratio (A) range = 0 to 127
Table 6. Prescaler Data Setting
Prescaler
divide ratio
SW = “H”
SW = “L”
PLL 1
64/65
128/129
PLL 2
64/65
128/129
Table 7. Phase Comparator Phase Switching Data Setting
FC1, FC2 = “H”
FC1, FC2 = “L”
(1)
Do1, Do2
fr > fp
H
L
fr = fp
Z
Z
fr < fp
L
H
VCO polarity
(1)
(2)
VCO Output
Frequency
(2)
LPF Output Voltage
Notes: • Z = High-impedance
• Depending upon the VCO and LPF polarity, FC bit should be set.
Table 8. LD/fout Output Select Data Setting
LDS
LD/fout output signal
H
fout (fr1/fr2, fp1/fp2) signals
L
LD signal
Table 9. Charge Pump Current Setting
10
CS
Current value
H
±6.0 mA
L
±1.5 mA
DS04-21361-4E
MB15F07SL
Power Saving Mode (Intermittent Mode Control Circuit)
Table 10. PS Pin Setting
PS pin
Status
H
Normal mode
L
Power saving mode
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption.
See the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.
Setting the PS pin high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal
operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is
because of the unknown relationship between the comparison frequency (fp) and the reference frequency
(fr) which can cause a major change in the comparator output, resulting in a VCO frequency jump and an
increase in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the
error signal from the phase detector when it returns to normal operation.
Notes : • When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1 μs.
• PS pins must be set at “L” for Power-ON.
OFF
ON
tv > 1 s
VCC
Clock
Data
LE
tps > 100 ns
PS
(1)
(2)
(3)
(1) PS = L (power saving mode) at Power-ON
(2) Set serial data 1 μs later after power supply remains stable (VCC > 2.2 V).
(3) Release power saving mode (PS: “L” → “H”) 100 ns later after setting serial data.
DS04-21361-4E
11
MB15F07SL
■ SERIAL DATA INPUT TIMING
1st data
2nd data
Control bit
Data
MSB
Invalid data
LSB
Clock
t1
t2
t3
t6
t7
LE
t4
t5
On rising edge of the clock, one bit of the data is transfered into the shift register.
Parameter
Min
Typ
Max
Unit
Parameter
Min
Typ
Max
Unit
t1
20
–
–
ns
t5
100
–
–
ns
t2
20
–
–
ns
t6
20
–
–
ns
t3
30
–
–
ns
t7
100
–
–
ns
t4
30
–
–
ns
Note: LE should be “L” when the data is transferred into the shift register.
12
DS04-21361-4E
MB15F07SL
■ PHASE COMPARATOR OUTPUT WAVEFORM
fr 1 /
fr 2
fp 1 /
fp 2
t WU
t WL
LD
(FC bit = High)
D O1 /
D O2
(FC bit = Low)
D O1 /
D O2
LD Output Logic Table
IF-PLL section
Notes: •
•
•
•
•
RF-PLL section
LD output
Locking state/Power saving state
Locking state/Power saving state
H
Locking state/Power saving state
Unlocking state
L
Unlocking state
Locking state/Power saving state
L
Unlocking state
Unlocking state
L
Phase error detection range = –2π to +2π
Pulses on Do1/2 signals are output to prevent dead zone.
LD output becomes low when phase error is tWU or more.
LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.
tWU and tWL depend on OSCIN input frequency as follows.
tWU > 2/fosc: i. e. tWU > 156.3 ns when fosc = 12.8 MHz
tWU < 4/fosc: i. e. tWL < 312.5 ns when fosc = 12.8 MHz
DS04-21361-4E
13
MB15F07SL
■ MEASURMENT CIRCUIT (for Measuring Input Sensitivity fin/OSCIN )
fout
Oscilloscope
VCC1
0.1 μF
S.G.
1000 pF
1000 pF
50 Ω
50 Ω
DO1
PS1
LD/fout
VCC1
fin1
GND1
OSCIN
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
DO2
PS2
Xfin2
VCC2
fin2
LE
Data
Clock
S.G.
S.G.
GND2
1000 pF
Controller (divide ratio setting)
50 Ω
VCC2
1000 pF
0.1 μF
14
DS04-21361-4E
MB15F07SL
■ TYPICAL CHARACTERISTICS
1.
Fin Input Sensitivity
• fin1 input sensitivity
PLL1 input sensitivity - Input frequency
Ta = +25 °C
10
5
Pfin1 (dBm)
0
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
SPEC
-5
-10
VCC = 3.6 V
-15
-20
-25
-30
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400 1500
fin1 (MHz)
• fin2 input sensitivity
PLL2 input sensitivity - Input frequency
Ta = +25 °C
10
5
0
SPEC
Pfin2 (dBm)
-5
-10
-15
-20
-25
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
-30
-35
VCC = 3.6 V
-40
0
100
200
300
400
500
600
700
800
900
1000 1100 1200 1300
1400 1500
fin2 (MHz)
DS04-21361-4E
15
MB15F07SL
2. OSCIN Input Sensitivity
• OSCIN
Input sensitivity - Input frequency
Ta = +25 °C
10
SPEC
0
VOSC (dBm)
-10
-20
VCC = 2.4 V
-30
VCC = 2.7 V
VCC = 3.0 V
-40
VCC = 3.6 V
-50
0
5
10
15
20
25
30
35
40
45
50
fOSC (MHz)
16
DS04-21361-4E
MB15F07SL
3.
Do Output Current (PLL1)
• 1.5 mA mode
VDO − IDO
Ta = +25 °C
VCC = 3 V
Change pump output current IDO (mA)
10.00
2.000
/div
IDOL
0
−10.00
IDOH
0
4.800
.6000/div
Change pump output voltage VDO (V)
• 6.0 mA mode
VDO − IDO
Ta = +25 °C
VCC = 3 V
Change pump output current IDO (mA)
10.00
IDOL
2.000
/div
0
IDOH
−10.00
0
4.800
.6000/div
Change pump output voltage VDO (V)
DS04-21361-4E
17
MB15F07SL
4. Do Output Current (PLL2)
• 1.5 mA mode
VDO − IDO
Ta = +25 °C
VCC = 3 V
Change pump output current IDO (mA)
10.00
2.000
/div
IDOL
0
IDOH
−10.00
0
4.800
.6000/div
Change pump output voltage VDO (V)
• 6.0 mA mode
VDO − IDO
Ta = +25 °C
VCC = 3 V
Change pump output current IDO (mA)
10.00
IDOL
2.000
/div
0
IDOH
−10.00
0
4.800
.6000/div
Change pump output voltage VDO (V)
18
DS04-21361-4E
MB15F07SL
5. Fin Input Impedance
fin1 input impedance
1 : 360.88 Ω
−683.25 Ω
100 MHz
2 : 30.641 Ω
−206.18 Ω
400 MHz
3 : 10.805 Ω
−92.172 Ω
800 MHz
1
4 : 10.076 Ω
−54.955 Ω
1100 MHz
2
4
3
START
100.000 000 MHz
STOP 1 100.000 000 MHz
fin2 input impedance
1 : 299.88 Ω
−658.06 Ω
100 MHz
2:
26.68 Ω
−184.5 Ω
400 MHz
3 : 11.949 Ω
−75.16 Ω
800 MHz
1
4 : 14.246 Ω
−36.49 Ω
1100 MHz
2
4
3
START
DS04-21361-4E
100.000 000 MHz
STOP
1 100.000 000 MHz
19
MB15F07SL
6. OSCIN Input Impedance
OSCIN input impedance
1 : 9.451 kΩ
−3.1875 kΩ
3 MHz
2 : 4.7255 kΩ
−5.1685 kΩ
10 MHz
3 : 1.6918 kΩ
−3.8045 kΩ
4
20 MHz
1
3
2
4 : 463.75 Ω
−2.1069 kΩ
40 MHz
START 3.000 000 MHz
20
STOP 40.000 000 MHz
DS04-21361-4E
MB15F07SL
■ REFERENCE INFORMATION
Test Circuit
S.G.
OSCIN
fin
Spectrum
Analyzer
fVCO = 1005 MHz
KV = 20 MHz/V
fr = 200 kHz
fOSC = 13 MHz
LPF
LPF
Do
1800 pF
VCO
VCC = 3.0 V
VVCO = 3.3 V
Ta = +25 °C
CP : 6 mA mode
1.1 kΩ
2.2 kΩ
330 pF
0.018 μF
• PLL Reference Leakage
ATTEN 10 dB
RL 0 dBm
MKR −71.16 dB
200 kHz
10 dB/
CENTER 1.005000 GHz
RBW 10 kHz
VBW 10 kHz
SPAN 1.000 MHz
SWP 50.0 ms
• PLL Phase Noise
ATTEN 10 dB
RL 0 dBm
MKR −54.83 dB
9.58 kHz
10 dB/
C/N = 79.6 (dBc/Hz)
BW = 16 kHz
CENTER 1.005000 GHz
RBW 300 kHz
VBW 300 kHz
SPAN 50.00 kHz
SWP 1.40 s
(Continued)
DS04-21361-4E
21
MB15F07SL
(Continued)
PLL Lock Up time
PLL Lock Up time
1005 MH->1031 MHz within ± 1 kHz
Lch->Hch
299 s
50.00000
MHz
50.00000
MHz
10.00000
MHz/div
10.00000
MHz/div
0
Hz
10.00000
MHz
0S
2.0000000 ms
30.00500
MHz
30.00500
MHz
2.000
kHz/div
2.000
kHz/div
29.99500
MHz
29.99500
MHz
0S
22
1031 MH->1005 MHz within ± 1 kHz
Hch->Lch
330 s
2.0000000 ms
0S
2.0000000 ms
0S
2.0000000 ms
Meas # 91
DS04-21361-4E
MB15F07SL
■ APPLICATION EXAMPLE
VCO
OUTPUT
LPF
3V
0.1 μF
1000 pF
1000 pF
from controller
Clock
Data
LE
fin2
VCC2
Xfin2
PS2
Do2
16
15
14
13
12
11
10
9
MB15F07SL
1
GND2
2
3
4
5
6
7
8
OSCIN
GND1
fin1
VCC1
LD/fout
PS1
Do1
3V
1000 pF
LockDet
1000 pF
0.1 μF
TCXO
OUTPUT
VCO
LPF
■ USAGE PRECAUTIONS
(1) VCC2 must equal Vcc1.
Even if either PLL 2 or PLL 1 is not used, power must be supplied to both VCC2 and VCC1 to keep them
equal. It is recommended that the non-use PLL is controlled by power saving function.
(2) To protect against damage by electrostatic discharge, note the following handling precautions:
-Store and transport devices in conductive containers.
-Use properly grounded workstations, tools, and equipment.
-Turn off power before inserting or removing this device into or from a socket.
-Protect leads with conductive sheet, when transporting a board mounted device.
DS04-21361-4E
23
MB15F07SL
■ ORDERING INFORMATION
Part number
MB15F07SLPFV1
24
Package
Remarks
16-pin plastic SSOP
(FPT-16P-M05)
DS04-21361-4E
MB15F07SL
■ PACKAGE DIMENSIONS
16-pin plastic SSOP
(FPT-16P-M05)
16-pin plastic SSOP
(FPT-16P-M05)
Lead pitch
0.65 mm
Package width ×
package length
4.40 × 5.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.45mm MAX
Weight
0.07g
Code
(Reference)
P-SSOP16-4.4×5.0-0.65
Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max).
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
*1 5.00±0.10(.197±.004)
0.17±0.03
(.007±.001)
9
16
*2 4.40±0.10 6.40±0.20
(.173±.004) (.252±.008)
INDEX
Details of "A" part
+0.20
1.25 –0.10
+.008
.049 –.004
LEAD No.
1
8
0.65(.026)
"A"
0.24±0.08
(.009±.003)
0.10(.004)
C
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F16013S-c-4-8
DS04-21361-4E
(Mounting height)
0.13(.005)
M
0~8°
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(Stand off)
(.004±.004)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
25
MB15F07SL
MEMO
26
DS04-21361-4E
MB15F07SL
MEMO
DS04-21361-4E
27
MB15F07SL
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
Asia Pacific
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://sg.fujitsu.com/semiconductor/
Europe
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
30F, Kerry Parkside, 1155 Fang Dian Road, Pudong District,
Shanghai 201204, China
Tel : +86-21-6146-3688 Fax : +86-21-6146-3660
http://cn.fujitsu.com/fss/
Korea
FUJITSU SEMICONDUCTOR KOREA LTD.
902 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fsk/
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fsp/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any
third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right
by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or
other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations
of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department