RFP22N10, RF1S22N10SM Data Sheet 22A, 100V, 0.080 Ohm, N-Channel Power MOSFETs These N-Channel power MOSFETs are manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. These transistors can be operated directly from integrated circuits. July 1999 File Number 2385.3 Features • 22A, 100V • rDS(ON) = 0.080Ω • UIS SOA Rating Curve (Single Pulse) • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance Formerly developmental type TA9845. • 175oC Operating Temperature Ordering Information • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” PART NUMBER PACKAGE BRAND RFP22N10 TO-220AB RFP22N10 RF1S22N10SM TO-263AB F1S22N10 Symbol D NOTE: When ordering use the entire part number. Add the suffix, 9A, to obtain the TO-263AB variant in tape and reel, e.g. RF1S22N10SM9A. G S Packaging JEDEC TO-220AB JEDEC TO-263AB SOURCE DRAIN GATE DRAIN (FLANGE) GATE SOURCE 4-499 DRAIN (FLANGE) CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 RFP22N10, RF1S22N10SM Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFP22N10, RF1S22N10SMS UNITS Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 100 V Drain to Gate Voltage (RGS = 1MΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR 100 V Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 22 50 A A Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD 100 W Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.67 W/oC Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ , TSTG -55 to 175 oC Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 100 - - V Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0 (Figure 7) Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 9) 2 - 4 V VDS = 80V, VGS = 0V - - 1 µA VDS = 80V, VGS = 0V, TC = 150oC - - 50 µA VGS = ±20V, VDS = 0 - - ±100 nA ID = 22A, VGS = 10V (Figure 8) - - 0.080 Ω VDD = 50Vwwwwwwwww, ID = 11A, RL = 4.5Ω, VGS = 10V, RGS = 25Ω (Figure 11) - - 60 ns - 13 - ns - 24 - ns td(OFF) - 65 - ns tf - 18 - ns t(OFF) - - 120 ns - - 150 nC - - 75 nC - - 3.5 nC Zero-Gate Voltage Drain Current IDSS Gate to Source Leakage Current Drain to Source On Resistance (Note 2) IGSS rDS(ON) Turn-On Time t(ON) Turn-On Delay Time td(ON) Rise Time tr Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge QG(TOT) VGS = 0V to 20V Gate Charge at 10V QG(10) VGS = 0V to 10V Threshold Gate Charge QG(TH) VGS = 0V to 2V Thermal Resistance Junction to Case RθJC Thermal Resistance Junction to Ambient RθJA VDD = 80V, ID ≈ 22A, RL = 3.64Ω Ig(REF) = 1mA (Figure 11) - - 1.5 oC/W - - 62 oC/W MIN TYP MAX UNITS ISD = 22A - - 1.5 V ISD = 22A, dISD/dt = 100A/µs - - 200 ns TO-220 and TO-263 Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage (Note 2) Diode Reverse Recovery Time SYMBOL VSD trr TEST CONDITIONS NOTE: 2. Pulse Test: Pulse Duration = 300µs maximum, duty cycle = 2%. 4-500 RFP22N10, RF1S22N10SM Typical Performance Curves Unless otherwise Specified 25 POWER DISSIPATION MULTIPLIER 1.2 1.0 ID, DRAIN CURRENT (A) 20 0.8 0.6 0.4 15 10 5 0.2 0 0 0 25 125 50 75 100 TC , CASE TEMPERATURE (oC) 150 25 175 75 100 125 150 175 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 100 100 TJ = MAX RATED SINGLE PULSE TC = 25oC 10 VGS = 20V IAS, AVALANCHE CURRENT (A) ID , DRAIN CURRENT (A) ID MAX (CONTINUOUS) DC OPERATION OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 STARTING TJ = 25oC 10 STARTING TJ = 150oC If R = 0 tAV = (L)(IAS)/(1.3 RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS R)/(1.3 RATED BVDSS - VDD) + 1] VDSS(MAX) = 100V 0.1 1 1 0.01 100 10 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 3. FORWARD BIAS SAFE OPERATING AREA 0.1 1 tAV, TIME IN AVALANCHE (ms) 10 FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 50 50 VGS = 10V PULSE DURATION = 80µs VDS = 15V DUTY CYCLE = 0.5% MAX. VGS = 7V 40 VGS = 8V 30 VGS = 6V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TC = 25oC 20 VGS = 5V 10 ID , DRAIN CURRENT (A) ID , DRAIN CURRENT (A) 50 40 TC = -55oC 30 TC = 175oC TC = 25oC 20 10 VGS = 4V 0 0 0 2 4 6 8 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 5. SATURATION CHARACTERISTICS 4-501 10 0 2 4 6 8 VGS , GATE TO SOURCE VOLTAGE (V) FIGURE 6. TRANSER CHARACTERISTICS 10 RFP22N10, RF1S22N10SM Typical Performance Curves Unless otherwise Specified (Continued) 3.0 ID = 250µA NORMALIZED DRAIN TO SOURCE ON RESISTANCE NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 2.0 1.5 1.0 0.5 0 -50 100 50 150 0 TJ , JUNCTION TEMPERATURE (oC) 2.5 ID = 22A, VGS = 10V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 2.0 1.5 1.0 0.5 0 -50 200 0 50 100 FIGURE 7. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 200 FIGURE 8. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 2500 1.50 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGS VGS = VDS , ID = 250µA 1.25 2000 C, CAPACITANCE (pF) NORMALIZED GATE THRESHOLD VOLTAGE 150 TJ , JUNCTION TEMPERATURE (oC) 1.00 0.75 0.50 1500 CISS 1000 500 0.25 COSS CRSS 0 50 100 150 0 200 0 TJ , JUNCTION TEMPERATURE (oC) VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 9. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 10 VDD = VDSS GATE TO SOURCE VOLTAGE RL = 4.55Ω IG(REF) = 1mA VGS = 10V 7.5 VDD = VDSS 50 5 0.75VDSS 0.50VDSS 0.25VDSS 25 0.75VDSS 0.50VDSS 0.25VDSS 2.5 DRAIN TO SOURCE VOLTAGE 0 20 IG(REF) IG(ACT) t, TIME (µs) 80 IG(REF) 0 IG(ACT) NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 11. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT 4-502 15 20 25 FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 10 100 75 5 VDS , DRAIN TO SOURCE VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V) 0 -50 RFP22N10, RF1S22N10SM S Test Circuits and Waveforms VDS BVDSS tP L IAS VARY tP TO OBTAIN REQUIRED PEAK IAS VDS VDD + RG - VGS VDD DUT tP 0V IAS 0 0.01Ω tAV FIGURE 12. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 13. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) VDS tf tr VDS 90% 90% RL VGS + - DUT 10% 10% 0 VDD 90% RGS VGS VGS 0 FIGURE 14. SWITCHING TIME TEST CIRCUIT 50% 50% PULSE WIDTH 10% FIGURE 15. RESISTIVE SWITCHING WAVEFORMS VDD VDS Qg(TOT) RL Qgd VGS Qgs VGS + VDD VDS DUT 0 IG(REF) IG(REF) 0 FIGURE 16. GATE CHARGE TEST CIRCUIT 4-503 FIGURE 17. GATE CHARGE WAVEFORMS RFP22N10, RF1S22N10SM All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 4-504 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029