IRFPG40 Data Sheet July 1999 4.3A, 1000V, 3.500 Ohm, N-Channel Power MOSFET • 4.3A, 1000V • rDS(ON) = 3.500Ω • UIS SOA Rating Curve (Single Pulse) • -55oC to 150oC Operating and Storage Temperature Symbol D G Formerly developmental type TA09850. Ordering Information IRFPG40 PACKAGE TO-247 2879.2 Features This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. PART NUMBER File Number S BRAND IRFPG40 NOTE: When ordering, include the entire part number. Packaging JEDEC STYLE TO-247 SOURCE DRAIN GATE DRAIN (TAB) 4-365 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 IRFPG40 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified IRFPG40 UNITS Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS 1000 V Drain to Gate Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 1000 V Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 4.3 A Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 17 A Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS ±20 V Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD 150 W Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 W/ oC Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS 490 mJ Operating and Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 150 oC Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS 1000 - V 2.0 4.0 V VDS = Rated BVDSS, VGS = 0V - 25 µA VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 150oC - 250 µA VGS = ±20V - ±100 nA rDS(ON) ID = 2.5A, VGS = 10V (Figures 7, 8) - 3.5 Ω gfs ID = 2.5A, VDS = 100V (Figure 11) 3.5 - S - 30 ns - 50 ns td(OFF) - 170 ns tf - 50 ns - 120 nC - 0.83 oC/W - 40 oC/W MIN MAX UNITS ISD = 4.3A (Figure 12) - 1.8 V ISD = 3.9A, dlSD/dt = 100A/µs - 1000 ns Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 9) Gate Threshold Voltage VGS(TH) VDS = VGS, ID = 250µA Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time IDSS IGSS td(ON) Rise Time tr Turn-Off Delay Time Fall Time Total Gate Charge Qg(TOT) Thermal Resistance Junction to Case RθJC Thermal Resistance Junction to Ambient RθJA VDD = 500V, I = 3.9A, RGS = 9.1Ω, RL = 120Ω VGS = 10V ID = 3.9A, VDS = 800V, VGS = 10V (Figure 13) Free Air Operation Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage Reverse Recovery Time VSD trr TEST CONDITIONS NOTES: 2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. 4. VDD = 25V, starting TJ = 25oC, L = 640µH, RG = 25Ω, peak IAS = 9.2A (Figure 3). 4-366 IRFPG40 Typical Performance Curves Unless Otherwise Specified POWER DISSIPATION MULTIPLIER 1.2 100 TJ = MAX RATED, TC = 25oC SINGLE PULSE ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 10µs 10 100µs 1ms 1 10ms OPERATION IN THIS AREA LIMITED BY rDS(ON) 0.10 0.2 DC 0.01 1 0 0 25 50 75 100 TC , CASE TEMPERATURE (oC) 125 150 FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE 100 1000 FIGURE 2. FORWARD BIAS SAFE OPERATING AREA 100 10 If R = 0 tAV = (L)(IAS)/(1.3 RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R) In[(Ias x R)/(1.3 RATED BVDSS - VDD) + 1] VGS = 10V VGS = 6V 8 DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 10 VDS , DRAIN TO SOURCE VOLTAGE (V) IDM 10 STARTING TJ = 25oC PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 6 VGS = 5V 4 2 STARTING TJ = 150oC 1 0.01 0.10 VGS = 4V 0 10.00 1.00 0 TIME IN AVALANCHE (ms) FIGURE 3. UNCLAMPED INDUCTIVE SWITCHING SOA 8 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDS = 7V VGS = 6V 4 DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 5 VGS = 10V 500 FIGURE 4. OUTPUT CHARACTERISTICS 10 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TC = 25oC 100 200 300 400 VDS , DRAIN TO SOURCE VOLTAGE (V) 6 VGS = 5V 4 2 3 2 150oC 25oC 1 VGS = 4V 0 0 10 20 30 40 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 5. SATURATION CHARACTERISTICS 4-367 50 0 0 2 4 6 VGS , GATE TO SOURCE VOLTAGE (V) FIGURE 6. TRANSFER CHARACTERISTICS 8 IRFPG40 Typical Performance Curves (Continued) 3.0 6 PULSE DURATION = 80µs 2.7 DUTY CYCLE = 0.5% MAX ID = 2.5A, VGS = 10V 2.5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 10V 5 DRAIN TO SOURCE ON RESISTANCE (Ω) Unless Otherwise Specified 4 3 2 1 2.2 2.0 1.7 1.5 1.3 1.0 0.8 0 0 4 8 6 ID , DRAIN CURRENT (A) 2 10 0 -50 12 FIGURE 7. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 3000 ID = 250µA 2500 1.2 1.1 1.0 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD CISS 2000 COSS 1500 CRSS 1000 0.9 500 0 -60 -40 -20 0 20 40 60 80 100 0 120 140 150 1 TJ , JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs. JUNCTION TEMPERATURE 8 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDS ≥ 70V 100 25oC 6 150oC 4 2 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 100 FIGURE 10. CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE ISD, SOURCE TO DRAIN CURRENT (A) gfs, FORWARD TRANSCONDUCTANCE (S) 150 FIGURE 8. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.3 0 50 100 TJ , JUNCTION TEMPERATURE (oC) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 150oC 25oC 10 1 0.1 0 0 1 2 3 4 ID , DRAIN CURRENT (A) 5 FIGURE 11. TRANSCONDUCTANCE vs DRAIN CURRENT 4-368 6 0 0.3 0.6 0.9 1.2 SOURCE TO DRAIN VOLTAGE (V) FIGURE 12. SOURCE TO DRAIN DIODE VOLTAGE 1.5 IRFPG40 Typical Performance Curves Unless Otherwise Specified (Continued) GATE TO SOURCE VOLTAGE (V) 16 14 12 VDS = 100V VDS = 200V 10 VDS = 400V 8 6 4 2 0 0 10 20 30 40 60 50 70 80 Qg, GATE CHARGE (nC) FIGURE 13. GATE TO SOURCE VOLTAGE vs GATE CHARGE Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN + RG REQUIRED PEAK IAS - VGS VDS IAS VDD VDD DUT tP 0V IAS 0 0.01Ω tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tf tr VDS RL 90% 90% + RG - VDD 10% 10% 0 90% DUT VGS VGS 0 FIGURE 16. SWITCHING TIME TEST CIRCUIT 4-369 10% 50% 50% PULSE WIDTH FIGURE 17. RESISTIVE SWITCHING WAVEFORMS IRFPG40 Test Circuits and Waveforms (Continued) VDS (ISOLATED SUPPLY) CURRENT REGULATOR 12V BATTERY 0.2µF VDD Qg(TOT) SAME TYPE AS DUT 50kΩ Qgd 0.3µF VGS Qgs D VDS DUT G IG(REF) 0 S 0 IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 18. GATE CHARGE TEST CIRCUIT IG(REF) 0 FIGURE 19. GATE CHARGE WAVEFORMS All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. 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