[ /Title (RFD1 2N06R LE, RFD12 N06RL ESM, RFP12 N06RL E) /Subject (12A, 60V, 0.135 Ohm, NChannel, Logic Level, Power MOSFETs) /Autho r () /Keywords (Intersil Corporation, NChannel, Logic Level, Power MOS- RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE Data Sheet July 1999 12A, 60V, 0.135 Ohm, N-Channel, Logic Level, Power MOSFETs Features These N-Channel logic level ESD protected power MOSFETs are manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use with logic level (5V) driving sources in applications such as programmable controllers, automotive switching, switching regulators, switching converters, motor drivers, relay drivers, and emitter switches for bipolar transistors. This performance is accomplished through a special gate oxide design which provides full rated conductance at gate biases in the 3V to 5V range, thereby facilitating true on-off power control directly from logic circuit supply voltages. • rDS(ON) = 0.135Ω File Number 2407.4 • 12A, 60V • Electrostatic Discharge Protected • UIS Rating Curve (Single Pulse) • Design Optimized for 5V Gate Drive • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol D Formerly developmental type TA09861. G Ordering Information PART NUMBER PACKAGE BRAND RFD12N06RLE TO-251AA 12N6LE RFD12N06RLESM TO-252AA 12N6LE RFP12N06RLE TO-220AB 12N06RLE S NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-252AA variant in tape and reel, i.e., RFD12N06RLESM9A. Packaging JEDEC TO-251AA JEDEC TO-252AA SOURCE DRAIN GATE DRAIN (FLANGE) DRAIN (FLANGE) GATE SOURCE JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) 6-12 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE TC = 25oC, Unless Otherwise Specified Absolute Maximum Ratings Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Electrostatic Discharge Rating ESD, MIL-STD-883, Category B(2) Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE 60 60 12 26 -5 to10 40 0.32 Refer to UIS SOA Curve 2 -55 to 150 UNITS V V A A V W W/oC kV oC oC oC 300 260 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V 60 - - V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 1 - 2 V Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On Resistance (Note 2) IDSS IGSS rDS(ON) µA VGS = -5 to 10V - - ±10 µA ID = 12A, VGS = 5V (Figures 7, 8) - - 0.135 Ω - 0.160 Ω - 60 ns - 12 - ns tr - 20 - ns td(OFF) - 24 - ns tf - 12 - ns t(OFF) - - 60 ns - - 40 nC - - 20 nC - - 1.5 nC Rise Time Fall Time Gate Charge at 5V µA 25 - td(ON) Threshold Gate Charge 1 - - Turn-On Delay Time Total Gate Charge - ID = 12A, VGS = 4V t(ON) Turn-Off Time - VDD = 30V, ID ≈ 6A, RL = 5Ω, RGS = 6.25Ω, VGS = 5V, (Figures 15, 16) Turn-On Time Turn-Off Delay Time VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 150oC Qg(TOT) VGS = 0V to 10V Qg(5) VGS = 0V to 5V Qg(TH) VGS = 0V to 1V Thermal Resistance Junction to Case RθJC Thermal Resistance Junction to Ambient RθJA VDD = 48V, ID = 12A, RL = 4Ω, IG(REF) = 0.25mA (Figures 17, 18) - - 3.125 oC/W TO-251AA and TO-252AA - - 100 oC/W TO-220AB - - 62 oC/W Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage Reverse Recovery Time VSD trr TEST CONDITIONS MIN TYP MAX UNITS ISD = 12A - - 1.2 V ISD = 12A, dISD/dt = 100A/µs - - 200 ns NOTES: 2. Pulse test: pulse width ≤ 300ms, duty cycle ≤ 2%. 3. Repetitive rating: pulse width is limited by maximum junction temperature. 6-13 RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE Typical Performance Curves Unless Otherwise Specified POWER DISSIPATION MULTIPLIER 1.2 15 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 10 5 0.2 0 0 0 25 50 75 100 TC , CASE TEMPERATURE (oC) 125 100 IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT, (A) TJ = MAX RATED TC = 25oC ID MAX CONTINUOUS 10 DC OPERATION OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 100 150 125 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 100 0.1 75 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE 1 50 25 150 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Idm If R = 0 tav = (L)(Ias) / (1.3 RATED BVDSS - VDD) If R ≠ 0 tav = (L/R) In ((Ias x R) / (1.3 RATED BVDSS - VDD) + 1) STARTING TJ = 25oC STARTING TJ = 150oC 10 1 0.01 100 0.1 1 tAV, TIME IN AVALANCHE (ms) 10 NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 3. FORWARD BIAS SAFE OPERATING AREA ID, DRAIN CURRENT (A) VGS = 10V IDS(ON), DRAIN TO SOURCE CURRENT (A) 30 VGS = 5V VGS = 4V 20 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TC = 25oC VGS = 3V 10 VGS = 2V 0 0 1.5 3 4.5 6 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 5. SATURATION CHARACTERISTICS 6-14 7.5 30 PULSE DURATION = 80µs DUTY CYCLE = 0.5 % MAX VDS = 15V -55oC 25oC 150oC 20 10 0 0 1.5 3 4.5 6 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 6. TRANSFER CHARACTERISTICS 7.5 RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE Unless Otherwise Specified (Continued) 2.5 VDS = 15V, ID = 12A 1.3 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 1.2 NORMALIZED DRAIN TO SOURCE ON RESISTANCE NORMALIZED DRAIN TO SOURCE ON RESISTANCE 1.4 1.1 1.0 0.9 0.8 0.7 0.6 4.0 4.5 5.0 5.5 6.0 6.5 VGS, GATE TO SOURCE VOLTAGE (V) 1.4 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE 0.5 1.2 1.1 1.0 0.9 0.8 0.7 50 100 150 TJ, JUNCTION TEMPERATURE (oC) 0 50 100 150 ID = 250µA 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50 200 0 50 100 150 TJ, JUNCTION TEMPERATURE (oC) 10 60 1000 750 CISS 500 COSS 250 CRSS 0 0 5 10 15 20 25 VDS, DRAIN TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 200 FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 1500 1250 200 FIGURE 8. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE FIGURE 9. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE C, CAPACITANCE (pF) 1.0 TJ , JUNCTION TEMPERATURE (oC) 1.3 0 1.5 0 -50 VGS = VDS, ID = 250µA 0.6 -50 2.0 7.0 FIGURE 7. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs GATE TO SOURCE VOLTAGE 1.4 ID = 12A, VGS = 5V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX PLATEAU VOLTAGES IN DESCENDING ORDER: VDD = BVDSS VDD = 0.75 BVDSS VDD = 0.50 BVDSS VDD = 0.25BVDSS 45 30 5 GATE SOURCE VOLTAGE RL = 5.0Ω IG(REF) = 0.25mA VGS = 5V 15 DRAIN SOURCE VOLTAGE 0 0 20 IG(REF) IG(ACT) t, TIME (µs) 80 IG(REF) IG(ACT) NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 6-15 FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT VGS, GATE TO SOURCE VOLTAGE (V) Typical Performance Curves RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN REQUIRED PEAK IAS IAS + RG VDS VDD VDD - VGS DUT tP 0V IAS 0 0.01Ω tAV FIGURE 13. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 14. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) VDS VDS VGS tf tr RL 90% 90% + VGS - 10% 10% 0 0V 90% DUT RGS VGS 0 50% 10% FIGURE 15. SWITCHING TIME TEST CIRCUIT 50% PULSE WIDTH FIGURE 16. RESISTIVE SWITCHING WAVEFORMS VDS VDD RL Qg(TOT) VDS VGS = 10V VGS Qg(5) + VDD DUT Ig(REF) VGS = 5V VGS - VGS = 1V 0 Qg(TH) Ig(REF) 0 FIGURE 17. GATE CHARGE TEST CIRCUIT 6-16 FIGURE 18. GATE CHARGE WAVEFORMS RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. 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