RFP15N08L Data Sheet June 1999 15A, 80V, 0.140 Ohm, Logic Level, N-Channel Power MOSFET File Number 2840.1 Features • 15A, 80V The RFP15N08L is an N-Channel enhancement mode silicon gate power field effect transistor specifically designed for use with logic level (5 volt) driving sources in applications such as programmable controllers, automotive switching, and solenoid drivers. This performance is accomplished through a special gate oxide design which provides full rated conduction at gate biases in the 3-5 volt range, thereby facilitating true on-off power control from logic circuit supply voltages. • rDS(ON) = 0.140Ω • Design Optimized for 5 Volt Gate Drive • Can be Driven Directly from Q-MOS, N-MOS, TTL Circuits • SOA is Power Dissipation Limited • 175oC Rated Junction Temperature • Logic Level Gate Formerly developmental type TA09804. • High Input Impedance Ordering Information • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” PART NUMBER RFP15N08L PACKAGE TO-220AB BRAND RFP15N08L Symbol NOTE: When ordering, use the entire part number. D G S Packaging JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) 6-234 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 RFP15N08L TC = 25oC, Unless Otherwise Specified Absolute Maximum Ratings RFP15N08L UNITS Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS 80 V Drain to Gate Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 80 V Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS ±10 V Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 15 A 40 A Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Derated above 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 72 0.48 W W/oC Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 175 oC Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 1mA, VGS = 0V 80 - - V Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 1mA 1 - 2.5 V TC = 25oC, VDS = 65V, VGS = 0V - - 1 µA TC = 125oC, VDS = 65V, VGS = 0V - - 50 µA VGS = 10V, VDS = 0V - - 100 nA ID = 7.5A, VGS = 5V - - 1.05 V ID = 15A, VGS = 5V - - 3.0 V rDS(ON) ID = 7.5A, VGS = 5V - - 0.140 Ω V(plateau) VDS = 15V, ID = 15A - - 4.5 V VDD = 40V, ID = 7.5A, RGS = 6.25Ω, VGS = 5V - - 40 ns - - 325 ns td(OFF) - - 325 ns tf - - 325 ns - - 80 nC - - 45 nC - - 3 nC 2.083 oC/W Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On Voltage IDSS IGSS VDS(ON) Drain to Source On Resistance (Note 2) Forward Transconductance Turn-On Delay Time td(ON) Rise Time tr Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate Charge at 5V Threshold Gate Charge Thermal Resistance Junction to Case Qg(TOT) VGS = 0-10V Qg(5) VGS = 0-5V Qg(TH) VGS = 0-1V VDD = 64V, ID = 15A, RL = 4.27Ω RθJC - - Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage VSD Diode Reverse Recovery Time trr TEST CONDITIONS MIN TYP MAX ISD = 7.5A - - 1.4 V ISD = 4A, dISD/dt = 100A/µs - 225 - ns NOTES: 2. Pulsed: pulse duration = ≤ 300µs maximum, duty cycle = ≤ 2%. 3. Repititive rating: pulse width limited by maximum junction temperature. 6-235 UNITS RFP15N08L Typical Performance Curves Unless Otherwise Specified 100 TC = 25oC 0.8 0.6 0.4 ID MAX CONTINUOUS DC 10 ER AT I ON OPERATION IN THIS AREA IS LIMITED BY rDS(ON) 1 0 50 100 0 150 1 10 100 VDS, DRAIN SOURCE VOLTAGE (V) TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE 16 PULSE DURATION = 80µs DUTY CYCLE ≤ 0.5% MAX TC = 25oC IDS, DRAIN TO SOURCE CURRENT VGS = 7.5V 30 VGS = 5V VGS = 10V VGS = 4.5V 20 VGS = 4V VGS = 3.5V 10 VGS = 3V VGS = 2.5V VGS = 2V 0 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) 5 VDS = 10V PULSE DURATION = 80µs DUTY CYCLE ≤ 0.5% MAX 14 -40oC 10 25oC 8 6 4 2 0 125oC 0 -40oC 1 2 3 4 VGS, GATE TO SOURCE VOLTAGE (V) 5 FIGURE 4. TRANSFER CHARACTERISTICS 2.0 0.3 NORMALIZED DRAIN TO SOURCE ON RESISTANCE VGS = 5V PULSE DURATION = 80µs DUTY CYCLE ≤ 0.5% MAX 0.2 TC = 125oC 25oC 0.1 -40oC 0 125oC 12 FIGURE 3. SATURATION CHARACTERISTICS ON RESISTANCE (Ω) 1000 FIGURE 2. FORWARD BIAS SAFE OPERATING AREA 40 IDS, DRAIN TO SOURCE CURRENT (A) OP 0.2 0 rDS(ON), DRAIN TO SOURCE CURVES MUST BE DERATED LINEARLY WITH INCREASE IN TEMPERATURE 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0 2 4 6 8 10 12 ID, DRAIN TO SOURCE CURRENT (A) 14 16 FIGURE 5. DRAIN TO SOURCE ON RESISTANCE vs DRAIN CURRENT 6-236 VGS = 10V, ID = 15A PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 1.5 1 0.5 0 -50 0 50 100 150 TJ, JUNCTION TEMPERATURE (oC) FIGURE 6. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 200 RFP15N08L Typical Performance Curves Unless Otherwise Specified (Continued) 1.4 1600 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 1400 ID = 250µA 1.2 1200 C, CAPACITANCE (pF) 1 0.8 1000 CISS 800 600 COSS 400 CRSS 200 0.6 -50 0 50 100 150 TJ, JUNCTION TEMPERATURE (oC) 0 200 FIGURE 7. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 0 10 20 30 40 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 8. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 10 60 DRAIN TO SOURCE VOLTAGE (V) 50 RL = 4Ω IG(REF) = 0.5mA VGS = 5V BVDSS 45 8 GATE SOURCE VOLTAGE VDD = BVDSS 30 6 VDD = BVDSS 4 0.75BVDSS 0.50BVDSS 0.25BVDSS 15 2 DRAIN SOURCE VOLTAGE 0 GATE TO SOURCE VOLTAGE (V) NORMALIZED GATE THRESHOLD VOLTAGE VGS = VDS 0 20 IG (REF) IG (ACT) 80 t, TIME (µs) IG (REF) IG (ACT) NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 9. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms tON tOFF td(ON) td(OFF) tf tr RL VDS 90% 90% + RG - VDD 10% 10% 0 DUT 90% VGS VGS 0 FIGURE 10. SWITCHING TIME TEST CIRCUIT 6-237 10% 50% 50% PULSE WIDTH FIGURE 11. RESISTIVE SWITCHING WAVEFORMS RFP15N08L Test Circuits and Waveforms (Continued) VDS VDD RL Qg(TOT) VDS VGS = 10V VGS Qg(5) + VDD DUT VGS = 5V VGS - VGS = 1V IG(REF) 0 Qg(TH) IG(REF) 0 FIGURE 12. GATE CHARGE TEST CIRCUIT FIGURE 13. GATE CHARGE WAVEFORMS All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. 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