JANSR2N7411 Formerly FSL9110R4 2.5A, -100V, 1.30 Ohm, Rad Hard, P-Channel Power MOSFET June 1998 Features Description • 2.5A, -100V, rDS(ON) = 1.30Ω The Discrete Products Operation of Intersil Corporationhas developed a series of Radiation Hardened MOSFETs specifically designed for commercial and military space applications. Enhanced Power MOSFET immunity to Single Event Effects (SEE), Single Event Gate Rupture (SEGR) in particular, is combined with 100K RADS of total dose hardness to provide devices which are ideally suited to harsh space environments. The dose rate and neutron tolerance necessary for military applications have not been sacrificed. • Total Dose - Meets Pre-RAD Specifications to 100K RAD (Si) • Single Event - Safe Operating Area Curve for Single Event Effects - SEE Immunity for LET of 36MeV/mg/cm2 with VDS up to 80% of Rated Breakdown and VGS of 10V Off-Bias The Intersil portfolio of SEGR resistant radiation hardened MOSFETs includes N-Channel and P-Channel devices in a variety of voltage, current and on-resistance ratings. Numerous packaging options are also available. • Dose Rate - Typically Survives 3E9 RAD (Si)/s at 80% BVDSS - Typically Survives 2E12 if Current Limited to IDM This MOSFET is an enhancement-mode silicon-gate power field-effect transistor of the vertical DMOS (VDMOS) structure. It is specially designed and processed to be radiation tolerant. The MOSFET is well suited for applications exposed to radiation environments such as switching regulation, switching converters, motor drives, relay drivers and drivers for high-power bipolar switching transistors requiring high speed and low gate drive power. This type can be operated directly from integrated circuits. • Photo Current - 0.3nA Per-RAD(Si)/s Typically • Neutron - Maintain Pre-RAD Specifications for 3E13 Neutrons/cm2 - Usable to 3E14 Neutrons/cm2 Ordering Information PART NUMBER JANSR2N7411 PACKAGE TO-205AF Also available at other radiation and screening levels. See us on the web, Intersil’s home page: http://www.intersil.com. Contact your local Intersil Sales Office for additional information. BRAND JANSR2N7411 Die Family TA17716. Symbol MIL-PRF-19500/639. D G S Package TO-205AF D G S CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 2-100 File Number 4493 JANSR2N7411 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulsed Avalanche Current, L = 100µH, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . IAS Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IS Pulsed Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISM Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ , TSTG Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL (Distance >0.063in (1.6mm) from Case, 10s Max) Weight (Typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JANSR2N7411 -100 -100 UNITS V V 2.5 1.5 7.5 ±20 A A A V 15 6 0.12 7.5 2.5 7.5 -55 to 150 300 W W W/oC A A A oC oC 1.0 g CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS -100 - - V TC = -55oC - - -7.0 V TC = 25oC -2.0 - -6.0 V TC = 125oC -1.0 - - V TC = 25oC - - 25 µA TC = 125oC - - 250 µA TC = 25oC - - 100 nA TC = 125oC - - 200 nA - - -3.58 V TC = 25oC - 1.00 1.30 Ω TC = 125oC - - 2.16 Ω - - 20 ns - - 45 ns td(OFF) - - 40 ns tf - - 45 ns Drain to Source Breakdown Voltage BVDSS ID = 1mA, VGS = 0V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 1mA Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On-State Voltage Drain to Source On Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Not on Slash Sheet) IDSS IGSS VDS(ON) rDS(ON)12 td(ON) tr Qg(TOT) VDS = -80V, VGS = 0V VGS = ±20V VGS = -12V, ID = 2.5A ID = 1.5A, VGS = -12V VDD = -50V, ID = 2.5A, RL = 20Ω, VGS = -12V, RGS = 7.5Ω Gate Charge at 12V Qg(12) VGS = 0V to -20V VDD = -50V, ID = 2.5A VGS = 0V to -12V Threshold Gate Charge (Not on Slash Sheet) Qg(TH) VGS = 0V to -2V - - 14 nC - 7.0 7.9 nC - - 0.64 nC Gate Charge Source Qgs - 1.9 2.1 nC Gate Charge Drain Qgd - 3.4 3.8 nC Thermal Resistance Junction to Case RθJC - - 8.3 oC/W Thermal Resistance Junction to Ambient RθJA - - 175 oC/W 2-101 JANSR2N7411 Source to Drain Diode Specifications PARAMETER SYMBOL Forward Voltage VSD Reverse Recovery Time TEST CONDITIONS ISD = 2.5A trr MIN TYP MAX UNITS -0.6 - -1.8 V - - 110 ns ISD = 2.5A, dISD/dt = 100A/µs Electrical Specifications up to 100K RAD TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Drain to Source Breakdown Volts (Note 3) BVDSS VGS = 0, ID = 1mA -100 - V Gate to Source Threshold Volts (Note 3) VGS(TH) VGS = VDS, ID = 1mA -2.0 -6.0 V Gate to Body Leakage (Notes 2, 3) IGSS VGS = ±20V, VDS = 0V - 100 nA Zero Gate Leakage (Note 3) IDSS VGS = 0, VDS = -80V - 25 µA Drain to Source On-State Volts (Notes 1, 3) VDS(ON) VGS = -12V, ID = 2.5A - -3.58 V Drain to Source On Resistance (Notes 1, 3) rDS(ON)12 VGS = -12V, ID = 1.5A - 1.30 Ω NOTES: 1. Pulse test, 300µs Max. 2. Absolute value. 3. Insitu Gamma bias must be sampled for both VGS = -12V, VDS = 0V and VGS = 0V, VDS = 80% BVDSS . Single Event Effects (SEB, SEGR) (Note 4) ENVIRONMENT (NOTE 5) TEST SYMBOL Single Event Effects Safe Operating Area SEESOA ION SPECIES TYPICAL LET (MeV/mg/cm) TYPICAL RANGE (µ) APPLIED VGS BIAS (V) (NOTE 6) MAXIMUM VDS BIAS (V) Ni 26 43 20 -100 Br 37 36 10 -100 Br 37 36 15 -80 Br 37 36 20 -50 NOTES: 4. Testing conducted at Brookhaven National Labs; sponsored by Naval Surface Warfare Center (NSWC), Crane, IN. 5. Fluence = 1E5 ions/cm2 (typical), TC = 25oC. 6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR). Typical Performance Curves Unless Otherwise Specified LET = 26MeV/mg/cm2, RANGE = 43µ LET = 37MeV/mg/cm2, RANGE = 36µ -120 1E-3 LIMITING INDUCTANCE (HENRY) FLUENCE = 1E5 IONS/cm2 (TYPICAL) -100 VDS (V) -80 -60 -40 -20 1E-4 ILM = 10A 30A 1E-5 100A 300A 1E-6 TEMP = 25oC 0 0 5 10 15 20 25 VGS (V) 1E-7 -10 -30 -100 -300 DRAIN SUPPLY (V) FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA 2-102 FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT GAMMA DOT CURRENT TO IAS -1000 JANSR2N7411 Typical Performance Curves Unless Otherwise Specified (Continued) 3 50 ID , DRAIN CURRENT (A) ID , DRAIN (A) TC = 25oC 2 1 0 -50 0 50 100µs 1ms 1 TC , CASE TEMPERATURE (oC) 10ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 0.1 -1 150 100 10 100ms -10 -500 -100 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 2.5 PULSE DURATION = 250ms, VGS = -12V, ID = 1.5A 2.0 QGS NORMALIZED rDS(ON) QG -12V QGD VG 1.5 1.0 0.5 CHARGE 0.0 -80 BASIC GATE CHARGE WAVEFORM -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) THERMAL RESPONSE (ZθJC) NORMALIZED FIGURE 5. BASIC GATE CHARGE WAVEFORM FIGURE 6. NORMALIZED rDS(ON) vs JUNCTION TEMPERATURE 1 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 0.001 10-5 PDM SINGLE PULSE 10-4 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC + TC 10-3 10-2 10-1 FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE 2-103 t1 t2 100 101 JANSR2N7411 Typical Performance Curves Unless Otherwise Specified (Continued) IF R ≠ 0 tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1] IF R = 0 tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD) IAS , AVALANCHE CURRENT (A) 10 STARTING TJ = 25oC STARTING TJ = 150oC 1 1E-5 1E-4 1E-3 1E-2 tAV , TIME IN AVALANCHE (ms) FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING Test Circuits and Waveforms ELECTRONIC SWITCH OPENS WHEN IAS IS REACHED VDS L BVDSS + CURRENT I TRANSFORMER AS tP - VARY tP TO OBTAIN REQUIRED PEAK IAS 0V VDS IAS VDD + 50Ω - tP VDD 50V-150V DUT 50Ω VGS ≤ 20V tAV FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 10. UNCLAMPED ENERGY WAVEFORMS VDD tON tOFF td(ON) td(OFF) RL tr VDS VDS tf 90% 90% 0V DUT VGS = -12V 10% 10% RGS 90% 50% VGS 50% PULSE WIDTH 10% FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 12. RESISTIVE SWITCHING WAVEFORMS 2-104 JANSR2N7411 Screening Information Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table). Delta Tests and Limits (JANS) TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MAX UNITS Gate to Source Leakage Current IGSS VGS = ±20V ±20 (Note 7) nA Zero Gate Voltage Drain Current IDSS VDS = 80% Rated Value Drain to Source On Resistance rDS(ON) TC = 25oC at Rated ID Gate Threshold Voltage VGS(TH) ID = 1.0mA ±25 (Note 7) µA ±20% (Note 8) Ω ±20% (Note 8) V NOTES: 7. Or 100% of Initial Reading (whichever is greater). 8. Of Initial Reading. Screening Information TEST JANS Gate Stress VGS = -30V, t = 250µs Pind Required Pre Burn-In Tests (Note 9) MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC) Steady State Gate Bias (Gate Stress) MIL-STD-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours Interim Electrical Tests (Note 9) All Delta Parameters Listed in the Delta Tests and Limits Table Steady State Reverse Bias (Drain Stress) MIL-STD-750, Method 1042, Condition A VDS = 80% of Rated Value, TA = 150oC, Time = 240 hours PDA 5% Final Electrical Tests (Note 9) MIL-S-19500, Group A, Subgroups 2 and 3 NOTE: 9. Test limits are identical pre and post burn-in. Additional Screening Tests PARAMETER MAX UNITS VDS = -80V, t = 10ms 0.68 A IAS VGS(PEAK) = -15V, L = 0.1mH 7.5 A Thermal Response ∆VSD tH = 10ms; VH = -15V; IH = 1A 90 mV Thermal Impedance ∆VSD tH = 500ms; VH = -15V; IH = 1A 230 mV Safe Operating Area Unclamped Inductive Switching SYMBOL SOA TEST CONDITIONS 2-105 JANSR2N7411 Rad Hard Data Packages - Intersil Power Transistors 1. JANS Rad Hard - Standard Data Package A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning Attributes Data Sheet Hi-Rel Lot Traveler HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data F. Group A - Attributes Data Sheet G. Group B - Attributes Data Sheet H. Group C - Attributes Data Sheet I. Group D - Attributes Data Sheet 2. JANS Rad Hard - Optional Data Package A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning - Attributes Data Sheet - Hi-Rel Lot Traveler - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data - X-Ray and X-Ray Report F. Group A - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups A2, A3, A4, A5 and A7 Data G. Group B - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups B1, B3, B4, B5 and B6 Data H. Group C - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups C1, C2, C3 and C6 Data I. Group D - Attributes Data Sheet - Hi-Rel Lot Traveler - Pre and Post Radiation Data 2-106 JANSR2N7411 TO-205AF 3 LEAD JEDEC TO-205AF HERMETIC METAL CAN PACKAGE INCHES ØD ØD1 SYMBOL P A h SEATING PLANE L Øb e e1 2 e2 1 90o 3 45o j k MIN MILLIMETERS MAX MIN MAX NOTES A 0.160 0.180 4.07 4.57 - Øb 0.016 0.021 0.41 0.53 2, 3 ØD 0.350 0.370 8.89 9.39 - ØD1 0.315 0.335 8.01 8.50 - e 0.095 0.105 2.42 2.66 4 e1 0.190 0.210 4.83 5.33 4 e2 0.095 0.105 2.42 2.66 4 h 0.010 0.020 0.26 0.50 - j 0.028 0.034 0.72 0.86 - k 0.029 0.045 0.74 1.14 - L 0.500 0.560 12.70 14.22 3 P 0.075 - 1.91 - 5 NOTES: 1. These dimensions are within allowable dimensions of Rev. E of JEDEC TO-205AF outline dated 11-82. 2. Lead dimension (without solder). 3. Solder coating may vary along lead length, add typically 0.002 inches (0.05mm) for solder coating. 4. Position of lead to be measured 0.100 inches (2.54mm) from bottom of seating plane. 5. This zone controlled for automatic handling. The variation in actual diameter within this zone shall not exceed 0.010 inches (0.254mm). 6. Lead no. 3 butt welded to stem base. 7. Controlling dimension: Inch. 8. Revision 3 dated 6-94. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 2-107 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029