INFINEON KTS6027-2

Wireless Components
2 Band TV Tuner Mixer-Oscillator-PLL
with unbalanced IF-Amplifier
KTS6027-2, KTS6029-2 Version 2.0
Specification July 2001
Revision History: Current Version: Preliminary Datasheet V 1.1, July 2000
Previous Version:Target Data Sheet
Page
(in previous
Version)
Page
(in current
Version)
Subjects (major changes since last revision)
all
all
version to 1.1, status to preliminary
4-2
4-2
circuit diagram modified
4-3
4-3
circuit diagram modified
5-2
5-2
Bus input/output SDA max changed to 6V,
Bus input SCL max changed to 6V,
ADC input added
5-3
5-3
new reference for ESD protection
5-5
5-5
Current consumption for LOW/MID band and HIGH band added,
tbf’s replaced by data
Charge Pump output voltage VCP = 1.3 V min
5-8
5-8
Oscillator phsase noise -85 dBc/Hz min, -89 dBc/Hz typ
5-9
5-9
Oscillator phsase noise -85 dBc/Hz min, -89 dBc/Hz typ
Revision History: Current Version: Datasheet, V 2.0, July 2001
Previous Version:Preliminary Datasheet V 1.1, July 2000
Page
(in previous
Version)
Page
(in current
Version)
Subjects (major changes since last revision)
all
all
version to 2.0, preliminary deleted
5-2
5- 2
definition of thermal properties changed
5-5
5-5
current consumtion changed
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KTS6027-2, KTS6029-2
Product Info
Product Info
General Description
Features
Package
The KTS6027-2/KTS6029-2 is a 5 V
mixer/oscillator and synthesizer for
analog and digital TV and VCR tuners.
General
■
Suitable for analog and digital terrestrial TV tuner
■
Compatible with KTS6027-S or
KTS6029-S in normal mode
■
New features in extended mode
■
Full ESD protection
Mixer/Oscillator
■
High impedance mixer input for
LOW/MID band
■
Low impedance mixer input for
HIGH band
■
4 pin oscillator for LOW/MID band
■
4 pin oscillator for HIGH band
IF-Amplifier
Application
■
single ended IF preamplifier
■
75 Ω output impedance
■
PLL
■
PLL with short lock-in time
■
High voltage VCO tuning output
■
Fast I2C bus
■
4 NPN bandswitch buffers
■
Internal LOW-MID/HIGH switch
■
Lock-in flag
■
Power-down reset
■
4 programmable reference divider
ratios: 24, 64, 80, 128
■
4 programmable charge pump currents
The IC is suitable for NTSC tuners in TV- and VCR-sets or CATV set-top
receivers for analog TV and Digital Video Broadcasting.
Ordering Information
Wireless Components
Type
Ordering Code
Package
KTS6027-2
Q67037-A1162 ( tape and reel)
P-TSSOP-28-1
KTS6029-2
Q67037-A1163 ( tape and reel)
P-TSSOP-28-1
Product Info
Specification, July 2001
1
Table of Contents
1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
2
2.1
2.2
2.3
2.4
Product Description . . .
General Description . . . .
Features . . . . . . . . . . . . .
Application . . . . . . . . . . .
Package Outlines . . . . . .
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3
3.1
3.2
3.3
3.4
Functional Description. . . . . . . .
Pin Configuration . . . . . . . . . . . . .
Internal Pin Configuration . . . . . . .
Block Diagram . . . . . . . . . . . . . . .
Circuit Description. . . . . . . . . . . . .
......
......
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......
......
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. . . . . . . . 3-8
. . . . . . . . 3-9
. . . . . . . 3-10
. . . . . . . 3-15
. . . . . . . 3-16
4
4.1
4.2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
KTS6027-2 Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
KTS6029-2 Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
5
5.1
5.1.1
5.1.2
5.1.3
5.2
5.3
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.4.8
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
I2C Bus Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35
Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36
Gain (GV) test Set-up in LOW/MID. . . . . . . . . . . . . . . . . . . . . . . . . . 5-36
Gain (GV) test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36
Matching circuit for optimum noise figure in LOW/MID. . . . . . . . . . . 5-37
Noise Figure Test Set-up in LOW/MID . . . . . . . . . . . . . . . . . . . . . . . 5-37
Noise Figure Test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38
Cross modulation Test Set-up in LOW/MID band. . . . . . . . . . . . . . . 5-38
Cross modulation Test Set-up in HIGH band . . . . . . . . . . . . . . . . . . 5-39
Measurement of fref and fdiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39
5.5
5.5.1
5.5.2
5.5.3
5.5.4
Electrical Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input admittance (S11) of the LOW/MID band mixer input .
Input impedance (S11) of the HIGH band mixer input . . . .
Output admittance (S22) of the Mixer output . . . . . . . . . . .
Output impedance (S22) of the IF output . . . . . . . . . . . . . .
. 2-5
. 2-6
. 2-6
. 2-7
. 2-7
. . . . . . . 5-40
. . . . . . . 5-40
. . . . . . . 5-40
. . . . . . . 5-41
. . . . . . . 5-41
2
Product Description
Contents of this Chapter
2.1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.3
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.4
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
KTS6027-2, KTS6029-2
Product Description
2.1 General Description
The KTS6027-2, KTS6029-2 device combines a digitally programmable phase
locked loop (PLL), with a mixer-oscillator block including two balanced mixers
and oscillators for use in TV and VCR tuners.
The PLL block with four selectable chip addresses forms a digitally programmable phase locked loop. With a 4 MHz quartz crystal, the PLL permits precise
setting of the frequency of the tuner oscillator up to 1024 MHz in increments of
31.25, 50, 62.5 or 166.7 kHz. The tuning process is controlled by a microprocessor via an I2C bus. The device has four output ports. A flag is set when the
loop is locked. It can be read by the processor via the I2C bus.
The mixer-oscillator block includes two balanced mixers (one mixer with highimpedance input and one mixer with a balanced low-impedance input), two frequency and amplitude-stable balanced oscillators for LOW/MID and HIGH, an
IF amplifier, a low-noise reference voltage source, and a band switch.
2.2 Features
General
■
Suitable for analog and digital terrestrial TV tuner
■
Compatible with KTS6027-S or KTS6029-S in normal mode
■
New features in extended mode
■
Full ESD protection
Mixer/Oscillator
■
High impedance mixer input for LOW/MID band
■
Low impedance mixer input for HIGH band
■
4 pin oscillator for LOW/MID band
■
4 pin oscillator for HIGH band
IF-Amplifier
■
single ended IF preamplifier
■
75 Ω output impedance
PLL
Wireless Components
■
PLL with short lock-in time
■
High voltage VCO tuning output
■
Fast I2C bus
■
4 NPN bandswitch buffers
■
Internal LOW-MID/HIGH switch
2-6
Specification, July 2001
KTS6027-2, KTS6029-2
Product Description
■
Lock-in flag
■
Power-down reset
■
4 programmable reference divider ratios: 24, 64, 80, 128
■
4 programmable charge pump currents
2.3 Application
■
The IC is suitable for NTSC tuners in TV- and VCR-sets or CATV set-top
receivers for analog TV and Digital Video Broadcasting.
2.4 Package Outlines
P-TSSOP-28-1
Wireless Components
2-7
Specification, July 2001
3
Functional Description
Contents of this Chapter
3.1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.2
Internal Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.4
3.4.1
3.4.2
3.4.3
3.4.4
Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Mixer-Oscillator block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
PLL block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
I2C-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
KTS6027-2, KTS6029-2
Functional Description
3.1 Pin Configuration
OSCHIGHIN
1
28
HIGHIN
OSCHIGHOUT
2
27
HIGHIN
OSCHIGHOUT
3
26
LOW/MIDIN
OSCHIGHIN
4
25
VCC
OSCLOW/MIDIN
5
24
MIXOUT
OSCLOW/MIDOUT
6
23
MIXOUT
OSCLOW/MIDOUT
7
OSCLOW/MIDIN
8
RFGND
KTS6027-2
22
PLLGND
21
SDA
9
20
SCL
ADC
10
19
AS
IFOUT
11
18
XTAL
PHIGH
12
17
PFM
VT
13
16
PMID
CP
14
15
PLOW
KTS6027-2_Pin_config
Figure 3-1
KTS6027-2 Pin Configuration
HIGHIN
1
28
OSCHIGHIN
HIGHIN
2
27
OSCHIGHOUT
LOW/MIDIN
3
26
OSCHIGHOUT
VCC
4
25
OSCHIGHIN
MIXOUT
5
24
OSCLOW/MIDIN
MIXOUT
6
23
OSCLOW/MIDOUT
PLLGND
7
22
OSCLOW/MIDOUT
SDA
8
21
OSCLOW/MIDIN
SCL
9
20
RFGND
AS
10
19
ADC
XTAL
11
18
IFOUT
PFM
12
17
PHIGH
PMID
13
16
VT
PLOW
14
15
CP
KTS6029-2
KTS6029-2_Pin_config
Figure 3-2
Wireless Components
KTS6029-2 Pin Configuration
3-9
Specification, July 2001
KTS6027-2, KTS6029-2
Functional Description
3.2 Internal Pin Configuration
Note: Pin designation refers to KTS6027-2. KTS6029-2 has reversed pinning
Table 3-1 Pin Definition and Function
Pin No.
Symbol
Equivalent I/O-Schematic
Average DC voltage
LOW/MID
HIGH
0.0 V
1.6 V
0.0 V
2.8 V
0.0 V
2.8 V
1
OSCHIGHIN
2
OSCHIGHOUT
3
OSCHIGHOUT
4
OSCHIGHIN
0.0 V
1.6 V
5
OSCLOW/
MIDIN
1.6 V
0.0 V
6
OSCLOW/
MIDOUT
2.3 V
0.0 V
7
OSCLOW/
MIDOUT
2.3 V
0.0 V
8
OSCLOW/
MIDIN
1.6 V
0.0 V
9
RFGND
0.0 V
0.0 V
Wireless Components
2
3
1
4
6
7
5
8
analog ground
3 - 10
Specification, July 2001
KTS6027-2, KTS6029-2
Functional Description
Table 3-1 Pin Definition and Function (continued)
Pin No.
10
Symbol
Equivalent I/O-Schematic
ADC
Average DC voltage
LOW/MID
HIGH
VADC
VADC
2.3 V
2.3 V
5.0 V
VCE
10
11
IFOUT
11
12
PHIGH
12
Wireless Components
3 - 11
Specification, July 2001
KTS6027-2, KTS6029-2
Functional Description
Table 3-1 Pin Definition and Function (continued)
Pin No.
13
Symbol
Equivalent I/O-Schematic
VT
Average DC voltage
LOW/MID
HIGH
VT
VT
2.1 V
2.1 V
5 V or VCE
5V
5 V or VCE
5V
14
14
CP
13
15
PLOW
16
PMID
17
PFM
5 V or VCE
5 V or VCE
18
XTAL
3.0 V
3.0 V
15
16
17
18
Wireless Components
3 - 12
Specification, July 2001
KTS6027-2, KTS6029-2
Functional Description
Table 3-1 Pin Definition and Function (continued)
Pin No.
19
Symbol
Equivalent I/O-Schematic
AS
Average DC voltage
LOW/MID
HIGH
VAS
VAS
n.a.
n.a.
n.a.
n.a.
0.0 V
0.0 V
19
20
SCL
20
21
SDA
21
22
PLLGND
Wireless Components
digital ground
3 - 13
Specification, July 2001
KTS6027-2, KTS6029-2
Functional Description
Table 3-1 Pin Definition and Function (continued)
Pin No.
23
Symbol
Equivalent I/O-Schematic
Average DC voltage
MIXOUT
LOW/MID
HIGH
3.8 V
3.8 V
3.8 V
3.8 V
5.0 V
5.0 V
1.8 V
0.0 V
0.0 V
0.9 V
0.0 V
0.9 V
IF Amp.
23
24
24
MIXOUT
Oscillator
25
VCC
26
LOW/MIDIN
supply voltage
26
27
HIGHIN
28
HIGHIN
Wireless Components
27
28
3 - 14
Specification, July 2001
KTS6027-2, KTS6029-2
Functional Description
28
(1)
27
(2)
26
(3)
25
(4)
24
(5)
23
(6)
22
(7)
21
(8)
20
(9)
19
(10)
18
(11)
PLOW
PMID
PFM
XTAL
AS
SCL
SDA
PLLGND
MIXOUT
MIXOUT
VCC
HIGHIN
HIGHIN
LOW/MIDIN
3.3 Block Diagram
17
(12)
16
(13)
15
(14)
VCC
I2C Bus
LOW
or MID
RF Input
LOW/MID
FL
Lock
Detector
HIGH
LOW
or MID
Mixer
LOW/MID
ADC
Reference
Divider
HIGH
Prog.
Divider
LOW
or MID
Oscillator
LOW/MID
SAW
Driver
CP,
CM,
OS
HIGH
IFOUT
ADC
(20)
(19) (18)
9
10
11
RFGND
(21)
8
OSCLOW/MIDIN
(22)
7
OSCLOW/MIDOUT
(23)
6
OSCLOW/MIDOUT
(24)
5
OSCLOW/MIDIN
(25)
4
OSCHIGHIN
(26)
3
OSCHIGHOUT
(27)
2
OSCHIGHOUT
OSCHIGHIN
(28)
1
fref
Phase/
Frequency
Comparator
Charge
Pump
(17)
12
PHIGH
Oscillator
HIGH
fdiv
(16)
13
(15)
14
CP
Mixer
HIGH
Crystal
Oscillator
VT
RF Input
HIGH
Ports
KTS602729_block_diag
Note: Pin designations in parenthesis refer to KTS6029-2
Figure 3-3
Wireless Components
Block Diagram
3 - 15
Specification, July 2001
KTS6027-2, KTS6029-2
Functional Description
3.4 Circuit Description
3.4.1
General
In the normal mode (see Table 5-7 Test modes on page 32) the IC is compatible with
KTS6027-S / KTS6029-S. An extended mode makes a reference divider ratio
of 24 (see Table 5-8 Reference divider ratio on page 32) and two additional charge pump
currents (see Table 5-9 Charge pump current on page 33) available.
3.4.2
Mixer-Oscillator block
The mixer oscillator section includes two balanced mixers (double balanced
mixer), two balanced oscillators for LOW and / or MID band and HIGH band, an
IF amplifier, a reference voltage source and a band switch.
Filters between tuner input and IC separate the TV frequency signals into two
bands. The band switching in the tuner front-end is done by using two or three
port outputs. In the selected band the signal passes a tuner input stage with
MOSFET amplifier, a double-tuned bandpass filter and is then fed to the balanced mixer input of the IC which has in case of LOW / MID a high-impedance
input and in case of HIGH a low-impedance input. The input signal is mixed
there with the signal from the activated on chip oscillator to the IF frequency
which is filtered out at the balanced high-impedance output pair by means of a
parallel tuned circuit. The following SAW preamplifier has a low output impedance to drive the SAW filter directly.
3.4.3
PLL block
The oscillator signal is internally DC-coupled as a differential signal to the programmable divider inputs. The signal subsequently passes through a programmable divider with ratio N = 256 through 32767 and is then compared in a digital
frequency / phase detector to a reference frequency fref = 31.25, 50, 62.5 or
166.7 kHz.
This frequency is derived from an unbalanced, low-impedance 4 MHz crystal
oscillator (pin XTAL) divided by R = 128, 80, 64 or 24.
The phase detector has two outputs that drive two current sources of opposite
polarity as charge pump. If the negative edge of the divided VCO signal appears
prior to the negative edge of the reference signal, the positive current source
pulses for the duration of the phase difference. In the reverse case the negative
current source pulses. If the two signals are in phase, the charge pump output
(CP) goes into the high-impedance state (PLL is locked). An active low-pass filter integrates the current pulses to generate the tuning voltage for the VCO
Wireless Components
3 - 16
Specification, July 2001
KTS6027-2, KTS6029-2
Functional Description
(internal amplifier, external pull-up resistor at TUNE and external RC circuitry).
The charge pump output is also switched into the high-impedance state if the
control bits T0 = 1 and T1 = 0. Here it should be noted, however, that the tuning
voltage can alter over a long period in the high-impedance state as a result of
self-discharge in the peripheral circuitry. TUNE may be switched off by the control bit OS to allow external adjustments.
If the VCO is not oscillating the PLL locks to a tuning voltage of 33 V .
By means of the control bits CP, CM, T0 and T1 the pump current can be
switched between four values by software. This programmability permits alteration of the control response time of the PLL in the locked-in state. In this way
different VCO gains can be compensated, for example.
The software-switched ports PLOW, PMID, PHIGH and PFM are general-purpose open-collector outputs. The test bits T0 = 0 and T1 = 1 switches the test
signals fref (i.e.fXTAL / 64) and fdiv (divided input signal) to PLOW and PMID
respectively.
The lock detector resets the lock flag FL if the width of the charge pump current
pulses is wider than the period of the crystal oscillator (i.e. 250 ns). Hence, if FL
= 1, the maximum deviation of the input frequency from the programmed frequency is given by
∆f = ± IP (KVCO / fXTAL) (C1+C2) / (C1C2)
where IP is the charge pump current, KVCO the VCO gain, fXTAL the crystal oscillator frequency and C1, C2 the capacitances in the loop filter (see Figure 4-1
KTS6027-2 Evaluation Board on page 20). As the charge pump pulses at i.e. 62.5 kHz (=
fref), it takes a maximum of 16 µs for FL to be reset after the loop has lost lock
state.
Once FL has been reset, it is set only if the charge pump pulse width is less than
250 ns for eight consecutive fref periods. Therefore it takes between 128 and
144 µs for FL to be set after the loop regains lock.
3.4.4
I2C-Bus Interface
Data is exchanged between the processor and the PLL via the I2C bus. The
clock is generated by the processor (input SCL), while pin SDA functions as an
input or output depending on the direction of the data (open collector, external
pull-up resistor). Both inputs have hysteresis and a low-pass characteristic,
which enhance the noise immunity of the I2C bus.
The data from the processor pass through an I2C bus controller. Depending on
their function the data are subsequently stored in registers. If the bus is free,
both lines will be in the marking state (SDA, SCL are HIGH). Each telegram
begins with the start condition and ends with the stop condition. Start condition:
SDA goes LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH
Wireless Components
3 - 17
Specification, July 2001
KTS6027-2, KTS6029-2
Functional Description
while SCL remains HIGH. All further information transfer takes place during
SCL = LOW, and the data is forwarded to the control logic on the positive clock
edge.
The table ”Bit Allocation” (see Table 5-4 Bit Allocation Read / Write on page 31) should be
referred to the following description. All telegrams are transmitted byte-by-byte,
followed by a ninth clock pulse, during which the control logic returns the SDA
line to LOW (acknowledge condition). The first byte is comprised of seven
address bits. These are used by the processor to select the PLL from several
peripheral components (chip select). The LSB bit (R/W) determines whether
data are written into (R/W = 0) or read from (R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the MSB bit of the
first or third data byte determines whether a divider ratio or control information
is to follow. In each case the second byte of the same data type has to follow
the first byte.
If the address byte indicates a READ operation, the PLL generates an acknowledge and then shifts out the status byte onto the SDA line. If the processor generates an acknowledge, a further status byte is output; otherwise the data line
is released to allow the processor to generate a stop condition. The status word
consists the lock flag and the power-on flag.
Four different chip addresses can be set by appropriate DC level at pin AS (see
Table 5-6 Address selection on page 32).
While applying the supply voltage, a power-on reset circuit prevents the PLL
from setting the SDA line to LOW, which would block the bus. The power-on
reset flag POR is set at power-on and when VCC falls below 3.2 V. It will be reset
at the end of a READ operation.
Wireless Components
3 - 18
Specification, July 2001
4
Applications
Contents of this Chapter
4.1
4.2
KTS6027-2 Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
KTS6029-2 Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
KTS6027-2, KTS6029-2
Applications
4.1 KTS6027-2 Evaluation Board
RGen = 75 Ω
HIGH
RGen = 75 Ω
SDA
SCL
AS
PFM
PMID
PLOW
VCC
LOW/
MID
4n7
1:1*)
100p
100p
4n7
4n7
4n7
4n7
4 MHz
68p
22p
68p
47n
220
220
220
18p
1n
22p
L4
2p2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
10
11
12
13
14
KTS6027-2
2
1p2
3
1p2
4
1p2
5
1p2
L1
6
7
2p7
2p2
L2
L3
8
2p2
9
120p
ADC
1k
1p
18p
C2
47n
4n7
4n7
2p7
PHIGH
22k
1
C1
2n2
33k
560
100n
220
BA892
47p
1k8
2k7
BB659C
100k
1k
1n
1k8
BB659C
3k3
2k7
RLoad = 75 Ω
IFoutput
4n7
+ 33 V
10n
KTS6027-2 Application Circuit
Figure 4-1
KTS6027-2 Evaluation Board
Table 4-1 Recommended band limits in MHz
RF input
Table 4-1 Coils
Oscillator
turns
E
wire
E
min
max
min
max
L1
1.5
2 mm
0.4 mm
LOW
55.25
127.25
101
173
L2
3.5
2.5 mm
0.5 mm
MID
133.25
361.25
179
407
L3
9.5
2.5 mm
0.4 mm
HIGH
367.25
803.25
413
849
L4
12.5
3.5 mm
0.3 mm
*)
Wireless Components
4 - 20
TOKO B4F Type 617DB-1023
Specification, July 2001
KTS6027-2, KTS6029-2
Applications
4.2 KTS6029-2 Evaluation Board
10n
BB659C
1k8
1k8
1n
47p
+ 33 V
IFoutput
RLoad = 75 Ω
2k7
BB659C
4n7
1k
33k
560
C2
2n2
100k
3k3
BA892
22k
2k7
220
18p
1p
L1
1p2
28
1p2
27
1p2
26
1p2
25
L2
L3
2p7
2p2
24
23
100n
1k
2p2
2p7
22
PHIGH
ADC
120p
21
4n7
20
C1
47n
4n7
19
18
17
16
15
10
11
12
13
14
KTS6029-2
1
2
3
4
5
6
7
8
9
2p2
L4
22p
22p
1n
18p
68p
68p
47n
220
220
220
100p
100p
4n7
4 MHz
1:1*)
4n7
LOW/
MID
HIGH
RGen = 75 Ω
4n7
4n7
4n7
VCC
RGen = 75 Ω
SDA
SCL
AS
PFM
PMID
PLOW
KTS6029-2 Application Circuit
Figure 4-2
KTS6029-2 Evaluation Board
Table 4-1 Recommended band limits in MHz
RF input
Table 4-1 Coils
Oscillator
turns
E
wire
E
min
max
min
max
L1
1.5
2 mm
0.4 mm
LOW
55.25
127.25
101
173
L2
3.5
2.5 mm
0.5 mm
MID
133.25
361.25
179
407
L3
9.5
2.5 mm
0.4 mm
HIGH
367.25
803.25
413
849
L4
12.5
3.5 mm
0.3 mm
*)
Wireless Components
4 - 21
TOKO B4F Type 617DB-1023
Specification, July 2001
5
Reference
Contents of this Chapter
5.1
5.1.1
5.1.2
5.1.3
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
5.2 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-4 Bit Allocation Read / Write . . . . . . . . . . . . . . . . . . . . . .
Table 5-5 Description of symbols. . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-6 Address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-7 Test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-8 Reference divider ratio. . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-9 Charge pump current . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-10 Bandswitching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-11 A/D converter levels. . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 5-31
. . . . . . . 5-31
. . . . . . . 5-31
. . . . . . . 5-32
. . . . . . . 5-32
. . . . . . . 5-32
. . . . . . . 5-33
. . . . . . . 5-33
. . . . . . . 5-34
5.3
I2C Bus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.4.8
Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36
Gain (GV) test Set-up in LOW/MID. . . . . . . . . . . . . . . . . . . . . . . . . . 5-36
Gain (GV) test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36
Matching circuit for optimum noise figure in LOW/MID. . . . . . . . . . . 5-37
Noise Figure Test Set-up in LOW/MID . . . . . . . . . . . . . . . . . . . . . . . 5-37
Noise Figure Test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38
Cross modulation Test Set-up in LOW/MID band. . . . . . . . . . . . . . . 5-38
Cross modulation Test Set-up in HIGH band . . . . . . . . . . . . . . . . . . 5-39
Measurement of fref and fdiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39
5.5
5.5.1
5.5.2
5.5.3
5.5.4
Electrical Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40
Input admittance (S11) of the LOW/MID band mixer input . . . . . . . . 5-40
Input impedance (S11) of the HIGH band mixer input . . . . . . . . . . . 5-40
Output admittance (S22) of the Mixer output . . . . . . . . . . . . . . . . . . 5-41
Output impedance (S22) of the IF output . . . . . . . . . . . . . . . . . . . . . 5-41
KTS6027-2, KTS6029-2
Reference
5.1 Electrical Data
5.1.1
Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even
momentarily and individually, as permanent damage to the IC may result.
Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB= - 20°C ...TAmax
Parameter 1).
Symbol
Limit Values
min
max
Supply voltage
VCC
-0.3
6
Ambient temperature
TA
-10
TAmax
Unit
Remarks
V
°C
2).
Junction temperature
TJ
Storage temperature
TStg
Temperature difference junction to case 3).
TJC
-40
+125
°C
+125
°C
2
K
PLL
CP
VCHGPMP
-0.3
ICHGPMP
Crystal oscillator pin XTAL
VXTAL
3
V
1
mA
VCC
IXTAL
-5
Bus input/output SDA
VSDA
-0.3
Bus output current SDA
ISDA(L)
Bus input SCL
VSCL
Chip address switch AS
V
mA
6
V
5
mA
-0.3
6
V
VAS
-0.3
VCC
V
VCO tuning output (loop filter)
VT
-0.3
35
V
ADC inpur
VADC
-0.3
VCC
V
Port outputs PLOW, PMID, PHIGH, PFM
VP
-0.3
VCC
V
IP(L)
-1
25
mA
tmax = 0.1 sec.
at 5.5 V
40
mA
tmax = 0.1 sec.
at 5.5 V
Total port output current
Wireless Components
ΣIP(L)
5 - 23
open collector
Specification, July 2001
KTS6027-2, KTS6029-2
Reference
Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB= - 20°C ... + 85°C (continued)
Parameter 1)
Symbol
Limit Values
Unit
min
max
-0.3
3
V
2
V
-5
6
mA
-0.3
3
V
VCC
V
2
kV
Remarks
Mixer-Oscillator
Mix input LOW/MID
Vi
Mix inputs HIGH
Vi
Ii
VCO base voltage
VB
VCO collector voltage
VC
ESD-Protection 4).
all pins
VESD
1). All values are referred to ground (pin), unless stated otherwise.
Currents with a positive sign flow into the pin and currents with a negative sign flow out of pin.
2).The maximum ambient temperature depends on the mounting conditions of the package. Any application
mounting must guarantee not to exceed the maximum junction temperature of 125 °C. As reference the temperature difference junction to case is given.
3).Referred to top center of package
4). According to EIA/JESD22-A114-B (HBM incircuit test), as a single device incircuit contact discharge test.
Wireless Components
5 - 24
Specification, July 2001
KTS6027-2, KTS6029-2
Reference
5.1.2
Operating Range
Within the operational range the IC operates as described in the circuit
description. The AC / DC characteristic limits are not guaranteed.
Table 5-2 Operating Range
Parameter
Symbol
Limit Values
min
max
Unit
Supply voltage
VCC
+4.5
+5.5
Programmable divider factor
N
256
32767
LOW/MID Mixer input frequency
range
fi
40
500
MHz
HIGH Mixer input frequency
range
fi
350
900
MHz
LOW/MID Oscillator frequency
range
fO
75
560
MHz
HIGH Oscillator frequency range
fO
380
950
MHz
Ambient temperature
TAMB
-20
TAmax
°C
Test Conditions
L
Item
V
1).
1).see 5.1.1 Absolute Maximum Ratings on page 23
Wireless Components
5 - 25
Specification, July 2001
KTS6027-2, KTS6029-2
Reference
5.1.3
AC/DC Characteristics
AC / DC characteristics involve the spread of values guaranteed in the specified
supply voltage and ambient temperature range. Typical characteristics are the
median of the production.
Table 5-3 AC/DC Characteristics with TAMB = 25 °C, VCC
Symbol
Limit Values
Unit
min
typ
max
Test Conditions
L
Item
Supply
Supply voltage
VCC
4.5
5
5.5
V
Current consumption
ICC
48
61
74
mA
LOW/MID band
51
65
79
mA
HIGH band
4.0
4.8
MHz
series resonance
100
Ω
series resonance
Digital Unit
PLL
Crystal oscillator connections XTAL
Crystal frequency
fXTAL
3.2
Crystal resistance
RXTAL
10
Oscillation frequency
fXTAL
3,99975
4,000
4,00025
MHz
fXTAL = 4 MHz
Input impedance
ZXTAL
-700
-900
-1100
Ω
fXTAL = 4 MHz
ICPDH
± 430
± 650
± 860
µA
VCP = 1.8 V
ICPH
± 180
± 250
± 360
µA
VCP = 1.8 V
ICPDL
± 90
± 125
± 180
µA
VCP = 1.8 V
ICPL
± 35
± 50
± 70
µA
VCP = 1.8 V
nA
T0=1, T1=0
2.5
V
PLL locked
Charge pump output CP
Output current,
see Table 5-9 Charge
pump current on page 33
Tristate current
ICPZ
Output voltage
VCP
±1
1.3
Drive output VT (open collector)
HIGH output current
ITH
10
µA
VTH = 33 V, T0 = 1,
T1 = 0
LOW output voltage
VTL
0.5
V
ITL = 1.0 mA
I2C-Bus
Bus inputs SCL, SDA
HIGH input voltage
VIH
3
5.5
V
LOW input voltage
VIL
0
1.5
V
HIGH input current
IIH
10
µA
VIH = VCC
LOW input current
IIL
µA
VIL = 0 V
Wireless Components
-10
5 - 26
Specification, July 2001
KTS6027-2, KTS6029-2
Reference
Table 5-3 AC/DC Characteristics with TAMB = 25 °C, VCC (continued)
Symbol
Limit Values
min
typ
Unit
Test Conditions
L
Item
max
Bus output SDA (open collector)
HIGH output current
IOH
10
µA
VOH = 5.5 V
LOW output voltage
VOL
0.4
V
IOL = 3 mA
Rise time
tr
300
ns
Fall time
tf
300
ns
400
kHz
Edge speed SCL,SDA
Clock timing SCL
Frequency
fSCL
0
HIGH pulse width
tH
0.6
µs
LOW pulse width
tL
1.3
µs
Set-up time
tsusta
0.6
µs
Hold time
thsta
0.6
µs
Set up time
tsusto
0.6
µs
Bus free
tbuf
1.3
µs
Set-up time
tsudat
0.1
µs
Hold time
thdat
0
µs
Input hysteresis
SCL, SDA
Vhys
Pulse width of spikes
which are suppressed
tsp
Capacitive load for
each bus line
CL
Start condition
Stop condition
Data transfer
200
0
mV
50
ns
400
pF
Port outputs PLOW, PMID, PHIGH, PFM (open collector)
HIGH output current
IPOH
1
µA
VPOH = 5 V
LOW output voltage
VPOL
0.5
V
IPOL = 25 mA
HIGH input current
IADCH
10
µA
LOW input current
IADCL
ADC port input
-10
µA
Address selection input AS
HIGH input current
IASH
LOW input current
IASL
Wireless Components
50
-50
5 - 27
µA
VASH = 5 V
µA
VASL = 0 V
Specification, July 2001
KTS6027-2, KTS6029-2
Reference
Table 5-3 AC/DC Characteristics with TAMB = 25 °C, VCC (continued)
Symbol
Limit Values
min
Unit
Test Conditions
typ
max
18
21
dB
fRF = 55.25 to 361.25
MHz, fIF = 41,25 to
58.75 MHz
11
dB
fRF = 55.25 to 361.25
MHz
L
Item
Analog Unit
LOW/MID Band Section (including IF amplifier)
Voltage gain
GV
15
Mixer noise figure
NF
9
Output voltage
causing 0.8 % of
crossmodulation in
channel,
Vo
109
dBµV
fRFw = 55.25 MHz
Vo
109
dBµV
fRFw = 361.25 MHz
IP2
140
dBµV
fRF1 = 55.25 MHz
fRF2 = 111.00 MHz,
PRF1 = PRF2
IP2
135
dBµV
fRF1 = 361.25 MHz
fRF2 = 723.00 MHz,
PRF1 = PRF2
IP3
110
dBµV
fRF1 = 55.25 MHz
fRF2 = 60.75 MHz,
fRF2 = 61.75 MHz,
PRF1 = PRF2 = PRF3
IP3
110
dBµV
fRF1 = 253.25 MHz
fRF2 = 258.75 MHz,
fRF2 = 259.75 MHz,
PRF1 = PRF2 = PRF3
Output voltage causing 1 dB compression
Vo
115
dBµV
fRF = 55.25 MHz
Vo
115
dBµV
fRF = 361.25 MHz
Mixer input
impedance
Ri
see 5.4.6 on page 38
Input IP2
Input IP3
Ci
0.5
1
1.5
kΩ
parallel equivalent
circuit, fRF = 100 MHz
2
3
pF
parallel equivalent
circuit, fRF = 100 MHz
Oscillator frequency
shift, PLL unlocked
∆fOsc(V)
400
kHz
VCC = 5 V ± 10 %
Oscillator frequency
drift, PLL unlocked
∆fOsc(T)
500
kHz
∆T = 25 °C
Oscillator frequency
drift, PLL unlocked
∆fOsc(t)
100
kHz
t = 5 s up to 15 min
after switching on
Wireless Components
5 - 28
Specification, July 2001
KTS6027-2, KTS6029-2
Reference
Table 5-3 AC/DC Characteristics with TAMB = 25 °C, VCC (continued)
Symbol
Oscillator pulling,
PLL unlocked
Unit
Test Conditions
min
typ
100
108
dBµV
∆f = 10 kHz
fRF = 55.25 MHz
100
108
dBµV
∆f = 10 kHz
fRF = 361.25 MHz
ΦOSC
-86
-89
dBc/Hz
aIF
15
20
dB
Vi = 80 dBµV
Vi
Vi
Oscillator
Limit Values
L
Item
max
fm = 10kHz
phase noise 1).
IF suppression
HIGH Band Section (including IF amplifier)
Voltage gain
GV
Mixer noise figure
NF
26
29
32
dB
fRF = 367.25 MHz to
801.25 MHz,
fIF = 41,25 to
58.75 MHz
6
9
dB
fRF = 367.25 to
613.25 MHz
7
10
dB
fRF = 619.25 to
801.25 MHz
Output voltage
causing 0.8 % of
crossmodulation in
channel,
see 5.4.7 on page 39
Vo
109
dBµV
fRFw = 403.25 MHz
Vo
109
dBµV
fRFw = 775.25 MHz
Input IP2
IP2
130
dBµV
fRF1 = 373.25 MHz
fRF2 = 747.00 MHz,
PRF1 = PRF2
Input IP3
IP3
99
dBµV
fRF1 = 503.25 MHz
fRF2 = 510.25 MHz,
fRF2 = 512.25 MHz,
PRF1 = PRF2 = PRF3
IP3
99
dBµV
fRF1 = 775.25 MHz
fRF2 = 780.75 MHz,
fRF2 = 781.75 MHz,
PRF1 = PRF2 = PRF3
Output voltage causing 1 dB compression
Vo
115
dBµV
fRF = 503.25 MHz
Vo
115
dBµV
fRF = 799.25 MHz
Mixer input
impedance
Ri
14
20
26
Ω
serial equivalent circuit, fRF = 600 MHz
Li
6
10
14
nH
serial equivalent circuit, fRF = 600 MHz
Oscillator frequency
shift, PLL unlocked
∆fOsc(V)
400
kHz
VCC = 5 V ± 10 %
Oscillator frequency
drift, PLL unlocked
∆fOsc(T)
800
kHz
∆T = 25 °C
Wireless Components
5 - 29
Specification, July 2001
KTS6027-2, KTS6029-2
Reference
Table 5-3 AC/DC Characteristics with TAMB = 25 °C, VCC (continued)
Symbol
Limit Values
min
Oscillator frequency
drift, PLL unlocked
∆fOsc(t)
Oscillator pulling,
PLL unlocked
Vi
Oscillator
typ
Unit
Test Conditions
kHz
t = 5 s up to 15 min
after switching on
L
Item
max
100
100
108
dBµV
∆f = 10 kHz
fRF = 367.25 MHz
100
108
dBµV
∆f = 10 kHz
fRF = 801.25 MHz
-86
-89
dBc/Hz
15
20
dB
Vi = 80 dBµV
Ω
serial equivalent
circuit,
fIF = 45.75 MHz
fm = 10kHz
phase noise 1)
IF suppression
aIF
SAW preamplifier
IF output impedance
RIF
80
LIF
7
nH
Rejection at the IF outputs
Divider interference
rejection
Vo
30
dBµV
2).
Channel CH6
INTCH6
70
dBc
VRFpix = 80 dBµV
VRFsnd = 80 dBµV
INTCHA5
70
dBc
VRFpix = 80 dBµV
beat 3).
Channel A-5 beat
rejection
4).
■ This value is only guaranteed in lab.
1). Measured in the evaluation board. (see Chapter 4)
2). This is the level of divider interferences close to the IF frequency. For example channel S3:
fOSC = 158.15 MHz, 1/4 fOSC = 39.5375 MHz. Measured in the evaluation board. (see Chapter 4)
3). Channel 6 beat is the interfering product of fRFpix + fRFsnd - fOSC of channel 6 at 42 MHz. Measured in
the evaluation board. (see Chapter 4)
4). Channel A-5 beat is the interfering product of fRFPIX + fRFSND - fOSC of channel A-5, fbeat = 45.5 MHz.
The possible mechanisms are fOSC - 2 x fIF or 2 x fRFpix - fOSC. Measured in the evaluation board.
(see Chapter 4)
Wireless Components
5 - 30
Specification, July 2001
KTS6027-2, KTS6029-2
Reference
5.2 Programming
Table 5-4 Bit Allocation Read / Write
Byte
MSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
Ack
Address Byte
1
1
0
0
0
MA1
MA0
0
A
Progr. Divider
Byte 1
0
N14
N13
N12
N11
N10
N9
N8
A
Progr. Divider
Byte 2
N7
N6
N5
N4
N3
N2
N1
N0
A
Control Byte
1
CP
T1
T0
CM
RSA
RSB
OS
A
Bandswitch
x
x
x
x
P3
P2
P1
P0
A
1
1
0
0
0
MA1
MA0
1
A
POR
FL
x
x
x
A2
A1
A0
A
Write Data
Byte 1).
Read Data
Address Byte
Status Byte
1). see Table 5-10 Bandswitching on page 33
Table 5-5 Description of symbols
Description
Symbol
MA0, MA1
Address selection bits (see Table 5-6 Address selection on page 32)
N14 to N0
programmable divider bits:
N = 214 x N14 + 213 x N13 + ..... + 23 x N3 + 22 x N2 + 21 x N1 + N0
CP
charge pump current:
T1, T0
test bits (see Table 5-7 Test modes on page 32)
CM
charge pump mode bit (see Table 5-9 Charge pump current on page 33)
RSA, RSB
reference divider bits (see Table 5-8 Reference divider ratio on page 32)
OS
tuning amplifier control bit:
bit = 0: enable VT
bit = 1: disable VT
PLOW, PMID, PHIGH,
PFM, see 5-10 on page 33
NPN ports control bits:
bit = 0: NPN open-collector output is inactive
bit = 1: NPN open-collector output is active
A0, A1, A2
ADC bits (see Table 5-11 A/D converter levels on page 34)
FL
PLL lock flag
POR
Power-on reset flag
flag is set at power-on and reset at the end of READ operation
x
don‘t care
Wireless Components
bit = 0: charge pump current = 50 µA
bit = 1: charge pump current = 250µA
bit = 1: loop is locked
5 - 31
Specification, July 2001
KTS6027-2, KTS6029-2
Reference
Table 5-6 Address selection
Voltage at AS
MA1
MA0
(0...0.1) * VCC
0
0
(0.2...0.3) * VCC or open circuit
0
1
(0.4...0.6) * VCC
1
0
(0.9...1) * VCC
1
1
Table 5-7 Test modes
Mode
Test mode
Normal operation
normal
Charge pump output, CP is in high-impedance state
1).
PMID = fdiv output, PLOW = fref output
Extended operation
extended
T1
T0
0
0
0
1
1
0
1
1
1). In this mode the IC is compatible with KTS6027-S / KTS6029-S
Table 5-8 Reference divider ratio
RSA
RSB
fref 2).
x
0
50 kHz
0
1
31.25 kHz
1
1
62.5 kHz
0
0
50 kHz
0
1
31.25 kHz
24
1
0
166.7 kHz
64
1
1
62.5 kHz
Reference divider ratio
Mode 1).
80
128
normal
64
T1
T0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
80
128
extended
1
1
1). see Table 5-7 Test modes on page 32
2). With a 4 MHz quartz.
Wireless Components
5 - 32
Specification, July 2001
KTS6027-2, KTS6029-2
Reference
Table 5-9 Charge pump current
Charge pump current
CP
Mode 1).
T0
0
0
normal
250 µA
1
50 µA
0
x
0
0
extended
CM
x
0
50 µA
125 µA
T1
1
1
1
250 µA
1
0
600 µA
1
1
1). see Table 5-7 Test modes on page 32
Table 5-10 Bandswitching
Bit Designation
P3
P2
P1
P0
Active Port
Pin
PHIGH 1).
12
0
0
0
0
PLOW
15
0
0
0
1
PMID
16
0
0
1
0
0
0
1
1
not used
PHIGH
12
0
1
0
0
PLOW, PFM
15, 17
0
1
0
1
PMID, PFM
16, 17
0
1
1
0
0
1
1
1
not used
PHIGH
12
1
0
0
0
PLOW, PFM
15, 17
1
0
0
1
PMID, PFM
16, 17
1
0
1
0
1
0
1
1
not used
PHIGH, PFM
12, 17
1
1
0
0
PLOW, PFM
15, 17
1
1
0
1
PMID, PFM
16, 17
1
1
1
0
1
1
1
1
not used
1). Default after power-on
Wireless Components
5 - 33
Specification, July 2001
KTS6027-2, KTS6029-2
Reference
Table 5-11 A/D converter levels
A2
A1
A0
(0...0.15)*VCC
0
0
0
(0.15...0.3)*VCC
0
0
1
(0.3...0.45)*VCC
0
1
0
(0.45...0.6)*VCC
0
1
1
(0.6...1)*VCC
1
0
0
Voltage at ADC
Wireless Components
5 - 34
Specification, July 2001
Wireless Components
Stop
Ack.
Addressing
5 - 35
1
1
0
0
0
1st Byte
Ack.
2nd Byte Ack. 3rd Byte Ack.
MA1 MA0 R/W
Start-ADB-DB1-DB2-CB-BB-Stop
Start= start condition
Start-ADB-CB-BB-DB1-DB2-Stop
ADB= address byte
Start-ADB-DB1-DB2-Stop
DB1= prog. divider byte 1
Start-ADB-CB-BB-Stop
DB2= prog. divider byte 2
CB= Control byte
BB= Bandswitch byte
Stop= stop condition
KTS6027-2, KTS6029-2
Abbreviations:
Ack.
Reference
Specification, July 2001
Telegram examples:
4th Byte
5.3 I2C Bus Timing Diagram
Start
KTS6027-2, KTS6029-2
Reference
5.4 Test Circuits
5.4.1
Gain (GV) test Set-up in LOW/MID
LOW/
MIDIN
50 Ω
Vmeas
V
50 Ω
RMS
Votmeter
IFOUT
Device
under
Test
Vi
50 Ω
spectrum
analyser
Vo
GVHFM
5.4.2
■
Zi >> 50 Ω => Vi = 2 x Vmeas = 80 dBµV
■
Vi = Vmeas + 6dB = 80 dBµV
■
Gv = 20 log(V0 / Vi)
Gain (GV) test Set-up in HIGH
HIGHIN IFOUT
50 Ω
Vmeas
V
RMS
Votmeter
50 Ω
Vi
Balun
1:1
Device
under
Test
Vo
50 Ω
spectrum
analyser
HIGHIN
GUHFM
Wireless Components
■
Vi = Vmeas = 70 dBµV
■
Gv = 20 log(V0 / Vi) + 1 dB (1 dB = insertion loss of balun)
5 - 36
Specification, July 2001
KTS6027-2, KTS6029-2
Reference
5.4.3
Matching circuit for optimum noise figure in LOW/MID
22p
15p
1n
In
In
Out
7 turns
wire ⍪ 0.5 mm
coil ⍪ 5.5 mm
22p
1n
Out
50 τ semi rigid cable
300 mm long
96 pF/m
33dB/100m
22p
NFM
For fRF = 150 MHz
For fRF = 50 MHz
■
loss = 0 dB
■
loss = 1.3 dB
■
image suppression = 16 dB
■
image suppression = 13 dB
5.4.4
Noise Figure Test Set-up in LOW/MID
Noise
Source
IN
OUT
LOW/
MIDIN
IFOUT
Noise
Figure
Meter
Device
under
Test
Matching
Circuit
NF = NFmeas - loss of matching circuit (dB)
NFVHFM
Wireless Components
5 - 37
Specification, July 2001
KTS6027-2, KTS6029-2
Reference
5.4.5
Noise Figure Test Set-up in HIGH
Noise
Source
Noise
Figure
Meter
HIGHIN IFOUT
Device
under
Test
Balun
1:1
HIGHIN
loss of balun = 1 dB
NF = NFmeas - loss of balun (dB)
NFUHFM
5.4.6
Cross modulation Test Set-up in LOW/MID band
Vmeas
V
50 Ω
RMS
Votmeter
unwanted
signal
source
AM = 80 %
A
LOW/
MIDIN
C
50 Ω
18 dB
attenuator
IFOUT
45.75 MHz
Hybrid
50 Ω
B
wanted
signal
source
Vi
Device
under
Test
Vo
50 Ω
modulation
analyser
D
50 Ω
XVHFM
Wireless Components
■
Zi >> 50 Ω => Vi = 2 x Vmeas
■
wanted output signal at fpix, Vo = 100 dBµV
■
unwanted output signal at fsnd , 80 % AM modulated with 1 kHz
5 - 38
Specification, July 2001
KTS6027-2, KTS6029-2
Reference
5.4.7
Cross modulation Test Set-up in HIGH band
Vmeas
50 Ω
V
RMS
Votmeter
unwanted
signal
source
AM = 80 %
18 dB
attenuator
A
C
HIGHIN IFOUT
50 Ω
Hybrid
Vi
Device
under
Test
Balun
1:1
50 Ω
B
wanted
signal
source
D
45.75 MHz
50 Ω
modulation
analyser
Vo
HIGHIN
50 Ω
XUHFM
5.4.8
■
wanted output signal at fpix, Vo = 100 dBµV
■
unwanted output signal at fsnd , 80 % AM modulated with 1 kHz
Measurement of fref and fdiv
VVCC
+5V
Test Mode: T1 = 1, T0 = 0
18p
4 MHz
Device under
Test
5k
PMID
5k
fref
PLOW
fdiv
Counter
Counter
fQ = fref * R
R: reference divider ratio
fVCO = fdiv * N
N: divider ratio
MEAS_COF
Wireless Components
5 - 39
Specification, July 2001
KTS6027-2, KTS6029-2
Reference
5.5 Electrical Diagrams
5.5.1
Input admittance (S11) of the LOW/MID band mixer input
0.8
2
0.5
0.6
0.7
1
1.5
0.9
Y0 = 20mS
0.4
3
0.3
4
0.2
5
0.1
10
0.1
0.2
0.3
0.4
0.5
0.6
0.7
1
0.9
0.8
1.5
2
3
4
5
10
20
20
0
48.25 MHz
20
10
0.1
407.25 MHz
5
0.2
4
0.3
3
0.7
0.8
0.9
1
1.5
0.6
2
0.5
0.4
Y_VHFMIX
5.5.2
Input impedance (S11) of the HIGH band mixer input
50
45
25
10
0
30
75
35
40
Z0 = 50 Ω (symmetrical)
20
0
15
15
200
250
10
855.25 MHz
500
5
415.25 MHz
1k
500
250
200
150
75
40
45
50
35
30
25
20
15
10
5
100
1k
Rdiff
0
1k
5
500
10
250
200
15
15
0
50
40
45
35
75
30
25
0
10
20
Zn_UHFMIX
Wireless Components
5 - 40
Specification, July 2001
KTS6027-2, KTS6029-2
Reference
5.5.3
Output admittance (S22) of the Mixer output
0.8
2
0.5
0.6
0.7
1
1.5
0.9
Y0 = 20mS
0.4
3
0.3
4
0.2
5
0.1
10
0.1
0.2
0.3
0.4
0.5
0.6
0.7
1
0.9
0.8
1.5
2
3
4
5
10
20
20
Rdiff
45.75 MHz
0
20
10
0.1
5
0.2
4
0.3
3
0.7
0.8
0.9
1
1.5
0.6
2
0.5
0.4
Y_MIXOUT
5.5.4
Output impedance (S22) of the IF output
1.5
1
0.9
0.8
0.5
2
0.6
0.7
Z0 = 50 Ω
0.4
3
0.3
4
5
0.2
10
0.1
20
10
5
4
3
2
1.5
0.8
0.9
1
0.7
0.6
0.5
0.4
0.3
0.2
0.1
20
0
45.75 MHz
20
0.1
10
0.2
5
4
0.3
3
1.5
1
0.8
0.9
0.7
0.6
2
0.5
0.4
UIFOUT
Wireless Components
5 - 41
Specification, July 2001