SONY CXA2503AR

CXA2503AR
Decoder/Driver/Timing Generator for Color LCD Panels
For the availability of this product, please contact the sales office.
Description
The CXA2503AR is an IC designed exclusively to
drive color LCD panels LCX005BK/BKB and
LCX009AK/AKB.
This IC greatly reduces the number of circuits and
parts required to drive LCD panels by incorporating
RGB decoder functions for video signals, driver
functions, and a timing generator for driving panels
onto a single chip.
This chip has a built-in serial interface circuit and
electronic attenuators which allow various mode
settings and adjustments to be performed through
direct control from an external microcomputer, etc.
Features
• Color LCD panels LCX005BK/BKB and LCX009AK/
AKB driver
• Supports NTSC and PAL systems
• Supports 16:9 wide display
• Supports composite inputs, Y/C inputs and Y/color
difference inputs
• Serial interface circuit
• Electronic attenuators (D/A converter)
• BPF, trap and delay line
• Sharpness function
• 2-point γ correction circuit
• R, G, B signal delay time adjustment circuit
• Polarity inversion circuit (line inverted mode)
• Supports external RGB input
• Supports AC drive for LCD panel during no signal
64 pin LQFP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
6
• Supply voltage VCC1 – GND1, 3
VCC2 – GND2
14
VDD1 – VSS1
4.5
VDD2 – VSS2
4.5
• Analog input pin voltage VINA
–0.3 to VCC1
•
•
•
•
V
V
V
V
V
Digital input pin voltage VIND –0.3 to VDD1 + 0.3 V
Operating temperature Topr
–15 to +75 °C
Storage temperature
Tstg
–40 to +125 °C
Allowable power dissipation
PD (Ta ≤ 75°C) 350mW Note)
Operating conditions
Supply voltage VCC1 – GND1, 3 4.25 to 5.25
VCC2 – GND2
11.0 to 13.5
VDD1 – VSS1
2.7 to 3.6
VDD2 – VSS2
2.7 to 3.6
V
V
V
V
Note) With substrate
Size: 114.3 × 76.1 × 1.5mm
Material: Glass fabric base epoxy
Applications
• LCD viewfinders
• Compact liquid crystal projectors
• Compact LCD monitors
Structure
Bipolar CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97910-PS
CXA2503AR
SCLK
41
DATA
42
LOAD
B OUT
43
TEST2
FB B
44
TEST3
G OUT
45
TEST4
FB G
46
RGT
R OUT
47
GND2
FB R
48
VCC2
SIG.CENTER
Block Diagram
40
39
38
37
36
35
34
33
GND2
+12V
buf
buf
SEREAL
BAS I/F
buf
VSS2 32 VSS2
VCC1 49 +4.5V
B-Y IN 50
31 VD2
CLAMP
PAL ID
DEMOD
R-Y IN 51
EXT COLOR
& BALANCE
VGATE
PAL
SW
COLOR
HUE
WIDE
VTST
POL SW
FRP
C OUT 52
30 VD1
29 EN
INT/EXT
R-BRT
BLK LIM 53
SUBBRIGHT
APC
VPAL
VWIN
28 VCK1
B-BRT
APC 54
VXO
HUE
PALSW
LPF
PS
27 VCK2
BRT
BRIGHT
MATRIX
VXO OUT 55
26 VST
HUE
COLOR
CONTRAST
CNTRAST
VXO IN 56
COLOR CONT
V REG 57
REG.
24 FLD IN
γ -2
KILLER
START UP 58
D/A
GAMMA
RGB
ACC DET
25 TEST1
S/H
γ -1
EXT SW
BPF
23 FLD OUT
PIC CONT
C IN 59
ACC AMP
HD
FILT ADJ
F0 ADJ 60
CLP
BGP
SBLK
GND3 61
GND3
HAFC
PLL-COUNTER
& DECODER
HCNT
H-PULSE
22 HD
21 HCK1
20 HCK2
V-SEP
Y IN 62
CLAMP
TRAP
DL 1
19 HST
HGATE
H-SKEW DET
PD
18 CLR
PIC 63
SYNC SEP
TEST0 64
+3V 17 VDD2
PLL
H. FILTER
VCO ADJ
+3V
VSS1
GND1
SYNC IN
H.FIL OUT
S.SEP IN
10
11
12
13
14
15
16
VDD1
TRAP
9
CKO
VD IN
8
CKI
7
VSS1
6
RPD
5
VCO ADJ
4
EXT B
3
EXT G
2
EXT R
1
PWRST
GND1
–2–
CXA2503AR
Pin Description
Pin
No.
Symbol
I/O
Description
1
PWRST
2
VD IN
3
TRAP
External trap connection
4
GND1
Analog 4.5V GND
5
SYNC IN
I
Video input for sync separation
6
H.FIL OUT
O
Video output for sync input
7
S.SEP IN
I
Sync separation circuit input
8
EXT R
I
External digital input R
9
EXT G
I
External digital input G
10
EXT B
I
External digital input B
11
VCO ADJ
O
VCO adjustment voltage output
12
RPD
O
Phase comparator output
13
VSS1
14
CKI
I
Oscillation cell input
15
CKO
O
Oscillation cell output
16
VDD1
Digital 3V power supply for oscillation cell
17
VDD2
Digital 3V power supply
18
CLR
O
CLR pulse output
19
HST
O
H start pulse output
20
HCK2
O
H clock pulse 2 output
21
HCK1
O
H clock pulse 1 output
22
HD
O
HD pulse output
23
FLD OUT
O
Field identification output
24
FLD IN
I
Field identification input
25
TEST1
26
VST
O
V start pulse output
27
VCK2
O
V clock pulse 2 output
28
VCK1
O
V clock pulse 1 output
29
EN
O
EN pulse output
30
VD1
O
VD1 pulse output
31
VD2
O
VD2 pulse output
32
VSS2
—
I
System reset
External vertical sync input
Digital 3V GND for oscillation cell
Test (Leave this pin open.)
Digital 3V GND
–3–
Input pin for
open status
CXA2503AR
Pin
No.
Symbol
I/O
Description
Input pin for
open status
33
SCLK
I
Serial interface clock input
H
34
DATA
I
Serial interface data input
H
35
LOAD
I
Serial interface load input
H
36
TEST2
Test (Leave this pin open.)
37
TEST3
Test (Leave this pin open.)
38
TEST4
Test (Leave this pin open.)
39
RGT
40
GND2
41
B OUT
O
B output
42
FB B
O
B signal DC voltage feedback circuit capacitor connection
43
G OUT
O
G output
44
FB G
O
G signal DC voltage feedback circuit capacitor connection
45
R OUT
O
R output
46
FB R
O
R signal DC voltage feedback circuit capacitor connection
47
VCC2
48
SIG.CENTER
49
VCC1
50
B-Y IN
I
B-Y demodulator input (or B-Y color difference signal input)
51
R-Y IN
I
R-Y demodulator input (or R-Y color difference signal input)
52
C OUT
O
Chroma signal output
53
BLK LIM
I
Black peak limiter level adjustment
54
APC
O
APC detective filter connection
55
VXO OUT
O
VXO output
56
VXO IN
I
VXO input
57
V REG
O
Constant voltage capacitor connection
58
START UP
O
Startup time constant connection
59
C IN
I
Chroma signal input
60
F0 ADJ
O
Internal filter adjusting resistor connection
61
GND3
62
Y IN
I
Y signal input
63
PIC
I
Y signal frequency response adjustment
64
TEST0
I
Test (Leave this pin open.)
I
Switches between Normal scan (H) and Reverse scan (L)
H
Analog 12V GND
Analog 12V power supply
I
RGB output DC voltage adjustment
Analog 4.5V power supply
Analog 4.5V GND
(H: Pull up)
–4–
CXA2503AR
Analog Block Pin Description
Pin
No.
Symbol
Pin voltage
Equivalent circuit
Description
VDD2
TG block system reset pin.
The system is reset when this
pin is connected to GND.
Connect a capacitor between
this pin and GND.
2µA
1
1
PWRST
—
1k
GND1
VDD2
50k
2
VDIN
External vertical sync signal
input.
50k
—
2
50k
GND1
VCC1
70µA
External trap connection.
Connect the trap between this
pin and GND to remove the
chroma component.
1k
3
TRAP
2.2V
300
3
130µA
GND1
VDD1
1k
5
SYNC IN
1.5V
5
2.1V
1k
30µA
Sync input.
Normally inputs the Y signal.
The standard signal input level
is 0.5Vp-p (100% white level
from the sync tip).
GND1
VDD2
20k
6
H.FIL OUT
2.5V
Outputs the video signal for
input to the sync separation
circuit.
6
20k
GND1
–5–
CXA2503AR
Pin
No.
Symbol
Pin voltage
Equivalent circuit
Description
VDD2
17k
7
S.SEP IN
1.0V
Sync separation circuit input.
Input the H FILTER output
signal.
7
10µA
1.8V 2.8V
GND1
8
EXT-R
VCC1
30µA
8
9
EXT-G
—
300
9
10
50k 2.7V
10
GND1
EXT-B
External digital signal inputs.
There are two threshold
values: Vth1 (= 1.0V) and
Vth2 (= 2.0V). When one of
the RGB signals exceeds
Vth1, all of the RGB outputs
go to black level; when an
input exceeds Vth2, only the
corresponding output goes to
white level.
VCC2
11
VCO ADJ
—
500
VCO adjustment voltage
output.
11
70µA
GND2
41
B OUT
VCC2
41
43
G OUT
VCC2
2
50
43
45
RGB signal outputs.
50
40µA
45
R OUT
42
FB B
GND2
VCC2
42
44
FB G
2.5V
1k
44
46
46
FB R
GND2
–6–
Smoothing capacitor
connection for the feedback
circuit of RGB output DC level
control.
Use a low-leakage capacitor
because of high impedance.
CXA2503AR
Pin
No.
Symbol
Pin voltage
Equivalent circuit
Description
VCC2
150k
48
SIG.
CENTER
6.0V
300
48
150k
RGB output DC voltage
control.
When used with a VCC2 of
12V or more, apply 6V from
an external source.
GND2
VCC1
50
B-Y IN
50
—
500
500
51
10k
51
R-Y IN
30µA
50µA
GND1
Color difference demodulation
circuit inputs.
Color difference signal is input
when using Y/color difference
input. At this time, the clamp
level is approximately 2.8V.
Pin 52 signal is input in other
modes. (except D-PAL∗1) At
this time, the DC level is
approximately 2.0V.
VCC1
52
C OUT
1.3V
52
350µA
Color adjusted chroma signal
output. The burst level is
approximately 140mVp-p (typ.).
(420mVp-p during D-PAL.)
GND1
VCC1
50k
53
BLK LIM
—
Sets the RGB output
amplitude (black-black) clip
level.
53
GND1
VCC1
54
APC
2.7V
1k
54
APC detective filter
connection.
GND1
∗1 D-PAL is a demodulation method that uses an external delay line during demodulation; S-PAL is a demodulation
method that internally processes chroma demodulation.
–7–
CXA2503AR
Pin
No.
Symbol
Pin voltage
Equivalent circuit
Description
VCC1
55
VXO OUT
2.9V
VXO output.
55
400µA
GND1
VCC1
500
56
VXO IN
3.2V
56
VXO input.
3k
3.2V
GND1
VCC1
57
V REG
3.6V
Smoothing capacitor
connection for the internally
generated constant voltage
source circuit. Connect a
capacitor of 1µF or more.
60k
57
30k
GND1
VCC1
Prevents output of the HST
and VST pulses for driving
LCD panels for a certain time
during power-on. Connect a
capacitor between this pin and
GND. When not using this pin,
connect to VCC1.
0.5µA
58
START UP
—
1k
58
GND1
VCC1
500 15p
59
C IN
—
59
20k
30µA
GND1
–8–
Video signal input when using
composite signal input.
Chroma signal input when
using Y/C signal input.
Leave this pin open when
using Y/color difference input.
CXA2503AR
Pin
No.
Symbol
Pin voltage
Equivalent circuit
Description
VCC1
Connect resistance of 82kΩ
between this pin and GND1 to
adjust the internal filters using
the outflow current value.
1k
60
F0 ADJ
60
2.4V
15µA
GND1
VCC1
Y signal input.
The standard signal input level
is 0.5Vp-p (100% white level
from the sync tip).
Input at low impedance (75Ω
or less).
1k
62
Y IN
62
3.1V
70µA
GND1
VCC1
20k
30k
63
PIC
2.25V
63
10k
2.25V
50µA
GND1
–9–
50µA
Adjusts frequency response of
luminance signal.
Increasing the voltage
emphasizes contours.
CXA2503AR
Setting Conditions for Measuring Electrical Characteristics
When measuring the electrical characteristics, the TG (timing generator) block must be initialized by performing
Settings 1 and 2 below.
Setting 1. System reset
After turning on the power, set SW1 to ON and start up V1 from GND in order to activate the TG
block system reset. (See Fig. 1-1.)
Setting 2. Horizontal AFC adjustment
Input SIG5 (VL = 0mV) to (A) and adjust serial bus register PLL ADJ so that WL and WH of the
TP12 output waveform are the same. (See Fig. 1-2.)
SIG5
VDD
WS
V1 (PWRST)
TR
TP12
TR > 10µs
WL
Fig. 1-1. System reset
WH
WL = WH
Fig. 1-2. Horizontal AFC adjustment
– 10 –
CXA2503AR
Electrical Characteristics – DC Characteristics
Unless otherwise specified, Settings 1 and 2 and the following setting conditions are required.
VCC1 = 4.5V, VCC2 = 12.0V, GND1 = GND2 = GND3 = 0V, VDD1 = VDD2 = 3.0V, VSS1 = VSS2 = 0V, Ta = 25°C
SW1, SW53, SW63 = ON
SW8, SW9, SW10, SW59 = A
SW50, SW51 = B
V53 = 0V, V63 = 2.2V
Set the serial bus registers to the "Serial Bus Register Initial Settings".
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
ICC11
Input SIG4 to (A) and SIG2 (0dB) to (B).
Measure the ICC1 current value.
COMP input mode
20
27
34
mA
ICC12
Input SIG4 to (A) and SIG2 (0dB) to (B).
Measure the ICC1 current value.
Y/C input mode
19
26
33
mA
ICC13
Input SIG4 to (A), (D) and (E).
Measure the ICC1 current value.
SW50, SW51 = A, SW59 = B
Y/color difference input mode
15
21
27
mA
ICC2
Input SIG4 to (A) and SIG2 (0dB) to (B).
Measure the ICC2 current value.
3
5
8
mA
IDD1
Input SIG4 to (A) and SIG2 (0dB) to (B).
Measure the IDD current value.
LCX009 mode
4
6
8
mA
IDD2
Input SIG4 to (A) and SIG2 (0dB) to (B).
Measure the IDD current value.
LCX005 mode
3.5
5
6.5
mA
Power supply characteristics
Current consumption
VCC1
Current consumption
VCC2
Current consumption
VDD
– 11 –
CXA2503AR
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Digital block I/O characteristics
VIN = VDD
Input current
FLDIN pin
II1
Normal input
pin
Input current
II2
Input pin with pull-up resistor∗1
VIN = VSS
High level input voltage
VIH
CMOS input cell∗3
Low level input voltage
VIL
CMOS input cell∗3
High level output voltage
Output pins except CKO
and RPD
VOH1
IOH = –1mA∗2
Low level output voltage
Output pins except CKO
and RPD
VOL1
IOL = 1mA∗2
High level output voltage
CKO pin
VOH2
IOH = –3mA
Low level output voltage
CKO pin
VOL2
IOL = 3mA
High level output voltage
RPD pin
VOH3
IOH = –0.5mA
Low level output voltage
RPD pin
VOL3
IOL = 0.7mA
Output off leak current
RPD pin
IOFF
High impedance status
VOUT = VSS or VOUT = VDD
–10
10
VIN = VSS
–145
–60
–24
µA
V
0.7VDD
0.3VDD
V
V
2.8
0.3
V
V
0.5VDD
0.5VDD
V
V
VDD – 1.2
–40
µA
1.0
V
40
µA
∗1 Input pins with pull-up resistors: SCLK, DATA, LOAD, RGT
∗2 Output pins except CKO and RPD: CLR, HST, HCK1, HCK2, HD, VD1, VD2, FLDOUT, VST, VCK1, VCK2, EN
∗3 CMOS input cells: FLDIN, SCLK, DATA, LOAD, RGT
– 12 –
CXA2503AR
Electrical Characteristics – AC Characteristics
Unless otherwise specified, Settings 1 and 2 and the following setting conditions are required.
VCC1 = 4.5V, VCC2 = 12.0V, GND1 = GND2 = GND3 = 0V, VDD1 = VDD2 = 3.0V, VSS1 = VSS2 = 0V, Ta = 25°C
SW1, SW53, SW63 = ON
SW8, SW9, SW10 = A
SW50, SW51, SW59 = B
V53 = 0V, V63 = 2.2V
Set the serial bus registers to the "Serial Bus Register Initial Settings".
Unless otherwise specified, measure the non-inverted outputs for TP41, TP43 and TP45.
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Y signal system
Video maximum gain
GV
Input SIG4 to (A) and measure the ratio between the output
amplitude (white – black) and input amplitude at TP43.
19
22
25
dB
Contrast characteristics
TYP
GCNTTP
Input SIG4 to (A) and measure the ratio between the output
amplitude (white – black) and input amplitude at TP43.
13
17
21
dB
Contrast characteristics
MIN
GCNTMN
Input SIG4 to (A) and measure the ratio between the output
amplitude (white – black) and input amplitude at TP43.
–9
–5
–1
dB
FCYYC
Y signal frequency
characteristics
FCYCMN
FCYCMP
Picture adjustment
variable amount 1
(composite input,
LCX005 mode)
GSHP1X
GSHP1N
Picture adjustment
variable amount 2
(composite input,
LCX009 mode)
GSHP2X
Picture adjustment
variable amount 3
(Y/C input,
LCX005 mode)
GSHP3X
Picture adjustment
variable amount 4
(Y/C input,
LCX009 mode)
GSHP4X
Carrier leak
(residual carrier)
GSHP2N
GSHP3N
GSHP4N
CRLEKY
TDYYC
Y signal
I/O delay time
TDYCMN
TDYCMP
Assume the output amplitude at
TP43 when SIG1 (0dB, no burst,
100kHz) is input to (A) as 0dB.
Vary the frequency of the input
signal to obtain the frequency
with an output amplitude of –3dB.
Y/C input,
V63 = 1.5V
5.0
MHz
Composite input
(NTSC), V63 = 2.2V
2.5
MHz
Composite input
(PAL), V63 = 2.2V
3.0
MHz
Assume the output amplitude at TP43 when SIG7 (100kHz) is
input to (A) as 0dB. Set SIG7 to 1.8MHz and measure
GSHP1X and GSHP1N as the amounts by which the output
amplitude at TP43 changes when V63 = 4V and 0V, respectively.
Assume the output amplitude at TP43 when SIG7 (100kHz) is
input to (A) as 0dB. Set SIG7 to 2.0MHz and measure
GSHP2X and GSHP2N as the amounts by which the output
amplitude at TP43 changes when V63 = 4V and 0V, respectively.
Assume the output amplitude at TP43 when SIG7 (100kHz)
is input to (A) as 0dB. Set SIG7 to 1.8MHz and measure
GSHP3X and GSHP3N as the amounts by which the output
amplitude at TP43 changes when V63 = 4V and 0V, respectively.
Assume the output amplitude at TP43 when SIG7 (100kHz)
is input to (A) as 0dB. Set SIG7 to 2.5MHz and measure
GSHP4X and GSHP4N as the amounts by which the output
amplitude at TP43 changes when V63 = 4V and 0V, respectively.
8
–3
6
Input SIG2 (0dB) to (A). Using a spectrum analyzer,
measure the input and the 3.58MHz or 4.43MHz
component of TP43, and obtain
CRLEKY = 150mV × 10∆CLK/20
using their difference ∆CLK.
Input SIG9 (VL = 150mV) to (A).
Measure the delay time from the 2T
pulse peak of the input signal to the
peak of the non-inverted output at
TP43.
– 13 –
2
dB
dB
2
dB
dB
14
–2
dB
dB
15
–1
10
1
9
–4
10
dB
12
0
dB
30
mV
Y/C input
230
330
430
ns
Composite input
(NTSC)
430
530
630
ns
Composite input
(PAL)
430
530
630
ns
CXA2503AR
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
NTSC
–3
0
3
dB
PAL
–3
0
3
dB
NTSC
–3
0
3
dB
PAL
–3
0
3
dB
Chroma signal block
ACC amplitude
characteristics 1
ACC amplitude
characteristics 2
ACC1
ACC2
FAPCN
APC pull-in range
FAPCP
Color adjustment
characteristics
MAX
GCOLMX
Color adjustment
characteristics
MIN
GCOLMN
HUE adjustment
range MAX
HUEMX
HUE adjustment
range MIN
HUEMN
ACKN
Killer operation
input level
ACKP
Input SIG5 (VL = 150mV) to (A) and SIG2
(0dB/+6dB/–20dB, 3.58MHz burst/chroma
phase = 180°, or 4.43MHz burst/chroma
phase = ±135°) to (B). Measure the output
amplitude at TP52, assuming the output
corresponding to 0dB, +6dB and –20dB as
V0, V1 and V2, respectively.
ACC1 = 20 log (V1/V0)
ACC2 = 20 log (V2/V0)
SW59 = A
Input SIG5 (VL = 150mV) to (A) and SIG2
(0dB, 3.58MHz burst/chroma phase = 180°,
or 4.43MHz burst/chroma phase = ±135°) to
(B). Changing the SIG2 burst frequency,
measure the frequency fl at which the TP41
output appears (the killer mode is canceled).
NTSC: FAPCN = fl – 3579545Hz
PAL: FAPCP = fl – 4433619Hz
SW59 = A
NTSC
±500
Hz
PAL
±500
Hz
Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,
3.58MHz burst/chroma phase = 180°) to (B). Assume
the chroma output when serial bus register COLOR =
80H, 0FFH and 0H as V0, V1 and V2, respectively.
GCOLMX = 20 log (V1/V0)
GCOLMN = 20 log (V2/V0)
SW59 = A
Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,
burst/chroma phase variable) to (B). Assume the
phase at which the output amplitude at TP41 reaches
a minimum when serial bus register HUE = 80H,
0FFH and 0H as θ0, θ1 and θ2, respectively.
HUEMX = θ1 – θ0
HUEMN = θ2 – θ0
SW59 = A
Input SIG5 (VL = 150mV) to (A) and SIG2
(level variable, 3.58MHz burst/chroma
NTSC
phase = 180°, or 4.43MHz burst/chroma
phase = ±135°) to (B), and measure the
output amplitude at TP41. Gradually reduce
the SIG2 amplitude level and measure the
PAL
level at which the killer operation is activated.
SW59 = A
– 14 –
4
6
–25
dB
–15
dB
–30
–40
deg
30
60
deg
–36
–30
dB
–34
–28
dB
CXA2503AR
Item
Demodulation output
amplitude ratio
(NTSC)
Demodulation output
phase difference
(NTSC)
Symbol
VRBN
VGBN
θRBN
θGBN
VRBP
Demodulation output
amplitude ratio (PAL)
VGBP
Demodulation output
phase difference
(PAL)
θRBP
θGBP
Color difference input
color adjustment
characteristics
MAX
GEXCMX
Color difference input
color adjustment
characteristics
MIN
GEXCMN
Color difference
balance
VEXCBL
GEXRMX
Color difference input
balance adjustment R
GEXRMN
GEXBMX
Color difference input
balance adjustment B
GEXBMN
Conditions
Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 3.58MHz)
to B and change the chroma phase. Assume the maximum
amplitude at TP41 as VB, the maximum amplitude at TP43
as VG, and the maximum amplitude at TP45 as VR.
VRBN = VR/VB, VGBN = VG/VB
SW59 = A
Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 3.58MHz)
to B and change the chroma phase. Assume the phase at
which the amplitude at TP41, TP43 and TP45 reaches a
maximum as θB, θG and θR, respectively.
θRBN = θR – θB, θGBN = θG – θB
SW59 = A
Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 4.43MHz)
to B and change the chroma phase. Assume the maximum
amplitude at TP41 as VB, the maximum amplitude at TP43
as VG, and the maximum amplitude at TP45 as VR.
VRBP = VR/VB, VGBP = VG/VB
SW59 = A
Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 4.43MHz)
to B and change the chroma phase. Assume the phase at
which the amplitude at TP41, TP43 and TP45 reaches a
maximum as θB, θG and θR, respectively.
θRBP = θR – θB, θGBP = θG – θB
SW59 = A
Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz,
no burst) to (D). Assume the output amplitude at TP41
when serial bus register COLOR = 80H as VC0, when
COLOR = 0H as VC2, and when SIG1 is set to –10dB and
COLOR = 0FFH as VC1.
GEXCMX = 20 log (VC1/VC0) + 10
GEXCMN = 20 log (VC2/VC0)
SW50, SW51 = A
Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz,
no burst) to (D) and (E). Assume the output amplitude at
TP41 as VB and the output amplitude at TP45 as VR.
VEXCBL = VR/VB
SW50, SW51 = A
Input SIG5 (VL = 150mV) to (A) and SIG1 (–6dB, 100kHz,
no burst) to (D) and (E). Assume the output amplitude at
TP45 and TP41 when serial bus register HUE = 80H as VR0
and VB0, respectively, when HUE = 0FFH as VR1 and
VB1, respectively, and when HUE = 0H as VR2 and VB2,
respectively.
GEXRMX = 20 log (VR1/VR0)
GEXRMN = 20 log (VR2/VR0)
GEXBMX = 20 log (VB1/VB0)
GEXBMN = 20 log (VB2/VB0)
SW50, SW51 = A
– 15 –
Min.
Typ.
Max.
0.53
0.63
0.73
0.25
0.32
0.39
99
109
119
deg
230
242
254
deg
0.65
0.75
0.85
0.33
0.40
0.47
80
90
100
deg
232
244
256
deg
4
6
dB
–20
–15
0.8
1.0
1.2
2
3
2
Unit
dB
dB
–3
–2
dB
–3
–2
dB
3
dB
CXA2503AR
Item
Symbol
Conditions
Min.
Typ.
Max.
NTSC
0.23
0.25
0.28
PAL
0.17
0.19
0.21
Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no
burst) to (E). Assume the output amplitude at TP45 as
VEXR and the output amplitude at TP43 as VEXRG.
VEXGR = VEXRG/VEXR
SW50, SW51 = A
0.48
0.53
0.58
VOUT
Input SIG5 (VL = 0mV) to (A). Adjust serial bus register
BRIGHT so that the output (black-black) at TP43 is 9Vp-p
and measure the DC voltage at TP41, TP43 and TP45.
5.85
6.00
6.15
V
∆VOUT
Input SIG5 (VL = 0mV) to (A). Adjust serial bus register
BRIGHT so that the output (black-black) at TP43 is 9Vp-p,
measure the DC voltage at TP41, TP43 and TP45, and
obtain the maximum difference between these values.
0
100
mV
VEXGB
G-Y matrix
characteristics
VEXGR
Input SIG5 (VL = 150mV) to (A) and SIG1
(0dB, 100kHz, no burst) to (D). Assume the
output amplitude at TP41 as VEXB and the
output amplitude at TP43 as VEXBG.
VEXGB = VEXBG/VEXB
SW50, SW51 = A
Unit
RGB signal output block
RGB signal output
DC voltage
RGB signal output
DC voltage difference
VLIMMX
RGB output limiter
operation voltage
VLIMMN
Input SIG3 to (A). Vary V53 and measure the maximum
value VLIMMX and minimum value VLIMMN of the voltage
range (black – black) over which the black limiter operates for
the TP41, TP43 and TP45 outputs. Assume the value when
V53 = 0V as VLIMMX, and when V53 = 4.5V as VLIMMN.
9.0
Vp-p
5.2
Vp-p
BRTMX
Input SIG5 (VL = 0mV) to (A) and measure the output
(black – black) at TP41, TP43 and TP45 when serial bus
register BRIGHT = 0H.
BRTMN
Input SIG5 (VL = 0mV) to (A) and measure the output
(black – black) at TP41, TP43 and TP45 when serial bus
register BRIGHT = 0FFH.
Amount of change in
sub-brightness
SBBRT
Input SIG5 (VL = 0mV) to (A) and measure the difference
between the outputs (black-black) at TP41 and TP45 and
the output (black – black) at TP43 when serial bus registers
R-BRT = B-BRT = 0H and when R-BRT = B-BRT = 0FFH.
±1.5
±2.0
Difference in gain
between RGB output
signals
∆GRGB
Input SIG4 to (A) and obtain the level difference between
the maximum and minimum non-inverted output amplitudes
(white – black) at TP41, TP43 and TP45.
–0.5
0
0.5
dB
Difference in RGB
output inverted/
non-inverted gain
∆GINV
Input SIG4 to (A) and obtain the level difference between
the non-inverted output amplitudes (white – black) and the
inverted output amplitudes at TP41, TP43 and TP45.
–0.5
0
0.5
dB
Difference in black level
potential between RGB
output signals
∆VBL
Input SIG4 to (A) and obtain the level difference between
the maximum and minimum black levels of both the inverted
and non-inverted outputs at TP41, TP43 and TP45.
300
mV
Amount of change in
brightness
– 16 –
9.0
Vp-p
4.0
Vp-p
V
CXA2503AR
Item
Symbol
Gγ1
γ gain
Gγ2
Gγ3
Vγ1MN
γ1 adjustment variable
range
Vγ1MX
Vγ2MN
γ2 adjustment variable
range
Vγ2MX
Conditions
Input SIG8 to (A). Adjust the non-inverted output black level at
TP43 to 6 – 4.5V with serial bus register BRIGHT and the noninverted output amplitude (white – black) at TP43 to 3.5V with
serial bus register CONTRAST. Measure VG1, VG2 and VG3.
Gγ1 = 20 log (VG1/0.0357)
Gγ2 = 20 log (VG2/0.0357)
Gγ3 = 20 log (VG3/0.0357)
(See Fig. 5 for definitions of VG1, VG2 and VG3.)
Input SIG8 to (A) and adjust serial bus register BRIGHT so
that the output at TP43 is 9Vp-p (black – black). Read the
point where the gain of the non-inverted output at TP43
changes when serial bus register γ1 = 0H and 0FFH from
the input signal IRE level.
Vγ1MN when γ1 = 0H, and Vγ1MX when γ1 = 0FFH.
Input SIG8 to (A) and adjust serial bus register BRIGHT so
that the output at TP43 is 9Vp-p (black – black). Read the
point where the gain of the non-inverted output at TP43
changes when serial bus register γ2 = 0H and 0FFH from
the input signal IRE level.
Vγ2MN when γ2 = 0H, and Vγ2MX when γ2 = 0FFH.
Min.
Typ.
Max.
Unit
23.0
26.0
29.0
dB
12.0
15.0
18.0
dB
18.0
22.0
26.0
dB
0
IRE
100
IRE
100
IRE
0
IRE
Filter characteristics
Amount of BPF
attenuation
ATBPF
ATRAPN
Amount of TRAP
attenuation
ATRAPP
R-Y, B-Y and LPF
characteristics
Assume the chroma amplitude at TP52
when SIG5 (VL = 0mV) is input to (A)
and SIG1 (0dB at input center frequency
(3.58MHz or 4.43MHz)) is input to (B) as
0dB. Obtain the amount by which the
output at TP52 is attenuated when the
frequencies noted on the right are input.
SW59 = A
NTSC 1.5MHz
–16
–10
dB
PAL
–16
–10
dB
NTSC 5.5MHz
–7
–2
dB
PAL
–8
–3
dB
–40
–30
dB
–40
–30
dB
1.0
1.3
MHz
2.0MHz
6.8MHz
Input SIG2 (0dB, 3.58MHz or 4.43MHz) to (A)
NTSC
and measure the output at TP43. Assume the
amplitude at TP43 during Y/C input mode as 0dB,
and obtain the amount of attenuation during
PAL
COMP input mode.
Assume the amplitude of the 100kHz component of the
output at TP43 when SIG5 (VL = 150mV) is input to (A) and
SIG2 (0dB, 3.58MHz + 100kHz) is input to (B) as 0dB.
Obtain the frequency which attenuates the beat component
of the output by 3dB when the SIG2 frequency is increased
with respect to 3.58MHz.
0.8
WSSEP
Input SIG5 (VL = 0mV, VS = 143mV, WS variable) to (A)
and confirm that it is synchronized with the HD output at
TP22. Gradually narrow the WS of SIG5 from 4.7µs and
obtain the WS at which synchronization with the HD output
at TP22 is lost.
2.0
VSSEP
Input SIG5 (VL = 0mV, WS = 4.7µs, VS variable) to (A)
and confirm that it is synchronized with the HD output at
TP22. Gradually reduce the VS of SIG5 from 143mV and
obtain the VS at which synchronization with the HD output
at TP22 is lost.
DEMLPF
Sync separation, TG block
Input sync signal width
sensitivity
Sync separation input
sensitivity
– 17 –
µs
40
60
mV
CXA2503AR
Item
Symbol
TDSYL
Sync separation
output delay time
TDSYH
HPLLN
Horizontal pull-in
range
HPLLP
Output transition time
(∗2 pins)
tTLH
tTHL
Conditions
Input SIG5 (VL = 0mV, WS = 4.7µs, VS = 143mV) to (A) and
measure the delay time with the RPD output at TP12. TDSYL is
from the falling edge of the input HSYNC to the falling edge of
the RPD output at TP12, and TDSYH is from the falling edge of
the input HSYNC to the rising edge of the RPD output at TP12.
Input SIG5 (VL = 0mV, WS = 4.7µs, VS = 143mV,
horizontal frequency variable) to (A) and confirm that NTSC
it is synchronized with the HD output at TP22. Obtain
the frequency fH at which the input and output are
synchronized by changing the horizontal frequency
of SIG5 from the non-synchronized condition.
PAL
HPLLN = fH – 15734
HPLLP = fH – 15625
Min.
Typ.
Max.
Unit
430
630
830
ns
4.7
5.0
5.3
µs
±500
Hz
±500
Hz
Input SIG5 (VL = 0mV) to (A).
Load = 30pF
(See Fig. 3.)
Cross-point time
difference
∆T
Input SIG5 (VL = 0mV) to (A).
Measure HCK1/HCK2 and VCK1/VCK2.
Load = 30pF
(See Fig. 4.)
HCK duty
DTYHC
Input SIG5 (VL = 0mV) to (A).
Measure the HCK1/HCK2 duty.
Load = 30pF
30
ns
30
ns
10
ns
47
50
53
%
0.8
1.0
1.2
V
1.8
2.0
2.2
V
50
100
150
ns
50
100
150
ns
0
V
External I/O characteristics
VTEXTB
External RGB input
threshold voltage
VTEXTW
Propagation delay time
between external RGB
input and output
TD1EXT
TD2EXT
Input SIG5 (VL = 0mV) to (A) and SIG6 (VL variable) to (C).
Raise the SIG6 amplitude (VL) from 0V and assume the
voltage where the outputs at TP41, TP43 and TP45 go to black
level as VTEXTB. Then raise the amplitude further and assume
the voltage where these outputs go to white level as VTEXTW.
Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 3V) to (C).
Measure the rise delay time TD1EXT and the fall delay
time TD2EXT of the outputs at TP41, TP43 and TP45.
(See Fig. 2.)
EXTBK
Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 1.7V) to (C).
Measure the difference from the black level of the outputs
at TP41, TP43 and TP45.
Output white level during
EXTWT
external RGB input
Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 2.7V) to (C).
Measure the difference from the black level of the outputs
at TP41, TP43 and TP45.
Output blanking level
during external RGB
input
– 18 –
3.5
V
CXA2503AR
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Serial transfer block
ts0
LOAD setup time, activated by the rising edge of SCLK.
(See Fig. 6.)
150
ns
ts1
DATA setup time, activated by the rising edge of SCLK.
(See Fig. 6.)
150
ns
th0
LOAD hold time, activated by the rising edge of SCLK.
(See Fig. 6.)
150
ns
th1
DATA hold time, activated by the rising edge of SCLK.
(See Fig. 6.)
150
ns
tw1L
SCLK pulse width. (See Fig. 6.)
160
ns
tw1H
SCLK pulse width. (See Fig. 6.)
160
ns
tw2
LOAD pulse width. (See Fig. 6.)
Data setup time
Data hold time
Minimum pulse width
µs
1
Other
VPLLMN
AFC adjustment voltage
output range
VPLLTP
VPLLMX
Measure the DC voltage of the output at TP11 when serial
bus register PLL ADJ = 0H, 80H and 0FFH as VPLLMN,
VPLLTP and VPLLMX, respectively.
– 19 –
5.65
5.8
5.95
7.4
7.5
7.6
9.15
9.3
9.45
V
Digital block I/O characteristics
Power supply characteristics Setting 2
ICC11
Symbol
COMP
COMP
COMP
COMP
IDD1
IDD2
II1
II2
Input current
Input current
– 20 –
COMP
COMP
COMP
COMP
COMP
COMP
COMP
COMP
COMP
VIH
VIL
VOH1
VOL1
VOH2
VOL2
VOH3
VOL3
IOFF
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
High level output voltage
Low level output voltage
High level output voltage
Low level output voltage
Output off leak current
Current consumption VDD
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
Y/color
difference
COMP
NTSC
NTSC
NTSC
System
Y/C
COMP
COMP
Input
Current consumption VCC2 ICC2
ICC13
Current consumption VCC1 ICC12
Horizontal AFC adjustment
Item
—
—
—
—
—
—
—
—
—
—
—
LCX005
LCX009
—
—
—
—
—
Panel
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
SHS1
S/H
Mode settings
Description of Electrical Characteristics Measurement Methods
Serial Bus Register Initial Values
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
H-POSI HD-POSI
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
HUE
DAC settings
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
B-BRT
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
γ1
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
γ2
(—: don't care, ADJ: adjustment, SET: setting)
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
COLOR BRIGHT CONTRAST R-BRT
Serial bus
CXA2503AR
Y signal block
GV
Symbol
– 21 –
NTSC
Y/C
GSHP4N
CRLEKY COMP
Carrier leak
—
NTSC
PAL
COMP
TDYCMP COMP
Y signal I/O delay time TDYCMN
TDYYC
Y/C
—
NTSC
Y/C
NTSC
Y/C
GSHP3N
GSHP4X
NTSC
Y/C
NTSC
GSHP2N COMP
GSHP3X
NTSC
NTSC
NTSC
COMP
GSHP2X
GSHP1N COMP
COMP
PAL
COMP
FCYCMP
GSHP1X
NTSC
NTSC
COMP
Y/C
FCYCMN
FCYYC
Picture quality
adjustment variable
amount 4
Picture quality
adjustment variable
amount 3
Picture quality
adjustment variable
amount 2
Picture quality
adjustment variable
amount 1
Y signal frequency
response
NTSC
Contrast characteristics
GCNTMN COMP
MIN
NTSC
COMP
NTSC
System
Input
COMP
Contrast characteristics
GCNTTP
TYP
Video maximum gain
Item
Through
Through
Through
S/H
—
—
—
—
Through
Through
Through
Through
LCX009 Through
LCX009 Through
LCX005 Through
LCX005 Through
LCX009 Through
LCX009 Through
LCX005 Through
LCX005 Through
LCX005 Through
LCX005 Through
LCX009 Through
—
—
—
Panel
Mode settings
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
H-POSI HD-POSI
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
HUE
DAC settings
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
B-BRT
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
γ1
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
γ2
(—: don't care, ADJ: adjustment, SET: setting)
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
0H
80H
0FFH
COLOR BRIGHT CONTRAST R-BRT
Serial bus
CXA2503AR
Chroma signal block
COMP
COMP
COMP
ACC2
ACC2
FAPCN
GCOLMN COMP
Color adjustment
characteristics MIN
—
—
—
—
PAL
NTSC
PAL
NTSC
– 22 –
Demodulation
output phase
difference PAL
Demodulation
output amplitude
ratio PAL
Demodulation
output phase
difference NTSC
Demodulation
output amplitude
ratio NTSC
COMP
COMP
COMP
θRBP
θGBP
COMP
θGBN
VGBP
COMP
θRBN
COMP
COMP
VGBN
VRBP
COMP
PAL
—
—
—
PAL
PAL
—
—
PAL
NTSC
—
—
NTSC
NTSC
—
NTSC
—
PAL
COMP
ACKP
VRBN
—
NTSC
COMP
ACKN
Killer operation input
level
—
NTSC
HUEMN COMP
HUE adjustment
characteristics MIN
—
—
—
HUEMX
NTSC
NTSC
NTSC
—
—
NTSC
PAL
Panel
System
10H
10H
10H
Through
Through
Through
Through
10H
10H
10H
Through
Through
10H
10H
10H
Through
Through
Through
10H
Through
10H
Through
10H
10H
Through
Through
10H
10H
10H
10H
Through
Through
Through
Through
10H
10H
Through
Through
10H
80H
80H
80H
0H
0H
0H
80H
80H
80H
0H
0H
0H
80H
0H
0H
80H
80H
80H
0H
0H
80H
0H
80H
80H
0H
0H
0H
0FFH
80H
80H
0H
0H
0H
0H
80H
80H
0H
0H
80H
HUE
0H
H-POSI HD-POSI
Through
S/H
Mode settings
HUE adjustment
characteristics MAX
COMP
GCOLMX COMP
COMP
COMP
ACC1
FAPCP
COMP
Input
ACC1
Symbol
Color adjustment
characteristics MAX
APC pull-in range
ACC amplitude
characteristics 2
ACC amplitude
characteristics 1
Item
DAC settings
80H
80H
80H
80H
80H
80H
96H
96H
96H
80H
80H
80H
96H
80H
80H
96H
96H
96H
80H
80H
96H
80H
96H
96H
80H
80H
96H
96H
80H
80H
80H
80H
0H
0FFH
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
0H
0H
0H
0H
80H
80H
80H
80H
0H
0H
0H
80H
80H
80H
0H
80H
80H
0H
0H
0H
80H
80H
0H
80H
0H
0H
80H
80H
0H
0H
0H
0H
80H
80H
80H
80H
0H
0H
80H
80H
γ1
B-BRT
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
γ2
(—: don't care, ADJ: adjustment, SET: setting)
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
COLOR BRIGHT CONTRAST R-BRT
Serial bus
CXA2503AR
Chroma signal block
RGB signal output block
GEXCMN
Color difference input
color adjustment
characteristics MIN
– 23 –
—
Difference in gain between
∆GRGB
RGB output signals
—
—
BRTMN
—
—
—
—
BRTMX
—
—
—
VLIMMN
SBBRT
Amount of change in
sub-brightness
Amount of change in
brightness
—
—
—
—
PAL
NTSC
—
—
—
—
—
—
—
System
—
—
—
Y/color
difference
Y/color
difference
Y/color
difference
Y/color
difference
Y/color
difference
Y/color
difference
Y/color
difference
Y/color
difference
Y/color
difference
Y/color
difference
Input
VLIMMX
∆VOUT
RGB signal output
DC voltage difference
RGB output limiter
operation voltage
VOUT
VEXGR
VEXGB
GEXBMN
GEXBMX
GEXRMN
GEXRMX
RGB signal output
DC voltage
G-Y matrix
characteristics
Color difference input
balance adjustment B
Color difference input
balance adjustment R
Color difference balance VEXCBL
GEXCMX
Symbol
Color difference input
color adjustment
characteristics MAX
Item
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Panel
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
S/H
Mode settings
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
H-POSI HD-POSI
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
0H
0FFH
0H
0FFH
80H
80H
80H
HUE
DAC settings
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
0H
0FFH
80H
0B4H
0FFH
0H
ADJ
ADJ
ADJ
ADJ
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
SET
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
SET
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
B-BRT
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
γ1
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
γ2
(—: don't care, ADJ: adjustment, SET: setting)
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
COLOR BRIGHT CONTRAST R-BRT
Serial bus
CXA2503AR
RGB signal output block
Filter characteristics
∆GINV
Difference in RGB
output inverted/
non-inverted gain
– 24 –
R-Y, B-Y and LPF
characteristics
Amount of TRAP
attenuation
Y/C
SET
ATRAPP
DEMLPF
SET
NTSC
PAL
NTSC
SET
—
—
COMP
—
—
ATRAPN
Amount of BPF attenuation ATBPF
γ2 adjustment variable Vγ2MN
range
Vγ2MX
—
—
—
—
—
Gγ3
—
—
—
—
System
—
—
—
—
—
Input
Gγ2
γ1 adjustment variable Vγ1MN
range
Vγ1MX
γ gain
Gγ1
Difference in black
level potential between ∆VBL
RGB output signals
Symbol
Item
—
—
—
—
—
—
—
—
—
—
—
—
—
Panel
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
Through
S/H
Mode settings
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
H-POSI HD-POSI
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
HUE
DAC settings
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
96H
96H
96H
96H
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
B-BRT
0H
0H
0H
0H
0H
0H
0FFH
0H
78H
78H
78H
0H
0H
γ1
0H
0H
0H
0H
0FFH
0H
0H
0H
0D7H
0D7H
0D7H
0H
0H
γ2
(—: don't care, ADJ: adjustment, SET: setting)
80H
80H
80H
80H
46H
46H
46H
46H
ADJ
ADJ
ADJ
80H
80H
COLOR BRIGHT CONTRAST R-BRT
Serial bus
CXA2503AR
– 25 –
Sync separation, TG block
External I/O characteristics
Other
—
—
—
—
—
—
—
Propagation delay time TD1EXT
between external RGB
input and output
TD2EXT
—
—
—
—
—
—
VPPLMX
—
VPPLMN
VPPLTP
—
—
—
Output white level during
EXTWT
external RGB input
AFC adjustment
voltage output range
—
—
—
EXTBK
—
—
—
—
VTEXTW
—
—
—
—
VTEXTB
External RGB input
threshold voltage
Output blanking level
during external
RGB input
—
—
—
—
—
DTYHC
—
—
HCK duty
—
—
∆T
tTHL
—
—
—
tTLH
Cross-point time
difference
Output transition time
—
PAL
—
—
NTSC
—
HPLLN
HPLLP
—
—
—
Horizontal pull-in range
—
—
—
—
Panel
—
—
—
System
—
—
—
Through
Through
Through
Through
Through
Through
SHS1
SHS1
SHS1
SHS1
Through
Through
Through
Through
Through
Through
S/H
Mode settings
Sync separation output TDSYL
delay time
TDSYH
VSSEP
Sync separation input
sensitivity
Input
—
Symbol
Input sync signal width
WSSEP
sensitivity
Item
—
—
—
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
10H
—
—
—
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
H-POSI HD-POSI
—
—
—
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
HUE
DAC settings
—
—
—
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
—
—
—
64H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
—
—
—
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
—
—
—
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
B-BRT
—
—
—
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
γ1
—
—
—
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
0H
γ2
(—: don't care, ADJ: adjustment, SET: setting)
—
—
—
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
80H
COLOR BRIGHT CONTRAST R-BRT
Serial bus
CXA2503AR
CXA2503AR
3V
SIG6
0V
TP41, 43, 45
non-inverted output
50%
TD1EXT
TD2EXT
Fig. 2. Conditions for measuring the delay between external RGB input and output
90%
50%
10%
tTLH
∆T
tTHL
Fig. 3. Output transition time measurement
conditions
∆T
Fig. 4. Cross-point time difference measurement
conditions
White
Non-inverted output
VG3
VG2
3.5V
VG1
Black
1.5V
Fig. 5. γ characteristics measurement conditions
– 26 –
CXA2503AR
DATA
D15 D14 D13 D12 D11 D10 D9
ts1
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
th1
SCLK
50%
tw1H
tw1L
50%
LOAD
ts0
th0
Fig. 6. Serial transfer block measurement conditions
– 27 –
tw2
CXA2503AR
Input Waveforms
SG No.
Waveform
Sine wave video signal:With/without burst
Amplitude and frequency variable
SIG1
150mV
← Value noted on left: 0dB
150mV
← Value noted on left: 0dB
150mV
143mV
Chroma signal: Burst, chroma frequency (3.579545MHz, 4.433619MHz)
Chroma phase and burst frequency variable
SIG2
143mV
Ramp waveform
357mV
SIG3
143mV
1H
5-step staircase waveform
150mV
SIG4
143mV
1H
VL amplitude variable
VS variable: 143mV unless otherwise specified
WS variable:4.7µs unless otherwise specified
fH variable: 15.734kHz (NTSC) or
15.625kHz (PAL)
unless otherwise specified
VL
SIG5
VS
fH
WS
– 28 –
CXA2503AR
SG No.
Waveform
30µs
5µs
VL amplitude variable
VL
SIG6
Horizontal sync signal
75mV
Frequency variable
175mV
SIG7
143mV
10-step staircase waveform
357mV
SIG8
143mV
1H
2T pulse waveform
VL amplitude variable
VS variable:143mV unless otherwise specified
WS variable:4.7µs unless otherwise specified
fH variable: 15.734kHz (NTSC) or
15.625kHz (PAL)
unless otherwise specified
VL
SIG9
VS
WS
fH
– 29 –
CXA2503AR
Electrical Characteristics Measurement Circuit
+12V
ICC2
TP45
0.1µ
47µ
TP43
100p
TP41
100p
100p
S39 TP38 TP37 TP36 TP35 TP34 TP33
+4.5V
0.01µ
0.47µ
45
44
43
42
41
40
39
38
37
36
35
34
33
FB R
R OUT
FB G
G OUT
FB B
B OUT
GND2
RGT
TEST4
TEST3
TEST2
LOAD
DATA
SCLK
SW50
A 0.01µ
(E)
B
A 0.01µ
B
SW51
TP52
V53
49 VCC1
VSS2 32
50 B-Y IN
VD2 31
TP31
51 R-Y IN
VD1 30
TP30
52 C OUT
EN 29
TP29
53 BLK LIM
VCK1 28
TP28
54 APC
VCK2 27
TP27
VST 26
TP26
56 VXO IN
TEST1 25
TP25
57 V REG
FLD IN 24
TP24
FLD OUT 23
TP23
HD 22
TP22
60 F0 ADJ
HCK1 21
TP21
61 GND3
HCK2 20
TP20
62 Y IN
HST 19
TP19
63 PIC
CLR 18
TP18
SW53
15k
0.068µ
46
0.1µ
(D)
0.47µ
47
VCC2
47µ
0.47µ
48
SIG.CENTER
ICC1
∗1
55 VXO OUT
0.22µ
∗2
1µ
58 START UP
(B)
SW59
A
59 C IN
B
82k
∗6
1µ
V1
4.5V
S2
0.033µ
0.47µ
750
B
9
10
11
12
13
14
A B
A
SW8
SW9
(A)
SW10
(C)
ICC3
68p
33k
3300p
∗3
3.3µ
10k
∗1 Used crystal: KINSEKI CX-5F
Frequency deviation: within ±30ppm, frequency temperature
characteristics: within ±30ppm, load capacity: 16pF
NTSC: 3.579545MHz
PAL: 4.433619MHz
∗2 NTSC: none, PAL: 18pF
∗3 Varicap diode: 1T369 (SONY)
16
220p
1k
10k
∗5
15
0.01µ
∗4 L value: 8.2µH during LCX005 mode
3.9µH during LCX009 mode
∗5 Trap (TDK)
NTSC: NLT4532-S3R6B
PAL: NLT4532-S4R4
∗6 Resistance value tolerance: ±2%,
temperature coefficient: ±200ppm or less
– 30 –
3V
∗4
TP11 TP12
AB
VDD1
8
CKO
7
CKI
6
VSS1
5
RPD
S.SEP IN
4
VCO ADJ
H.FIL OUT
3
EXT B
SYNC IN
2
EXT G
GND1
1
SW1
VDD2 17
EXT R
TRAP
64 TEST0
VD IN
S64
SW63
PWRST
V63
47µ
0.1µ
CXA2503AR
Description of Operation
The CXA2503AR incorporates the three functions of an RGB decoder block, an RGB driver block and a timing
generator (TG) block onto a single chip using BiCMOS technology.
1) RGB decoder block
• Input mode switching
The input mode can be switched between composite input, Y/C input and Y/color difference input by the
serial bus settings.
During composite input:
The composite signal is input to Pins 5, 59 and 62.
During Y/C input:
The Y signal is input to Pins 5 and 62, and the C signal to Pin 59.
During Y/color difference input: The Y signal is input to Pins 5 and 62, the B-Y signal to Pin 50, and the R-Y
signal to Pin 51.
• System switching
The input system can be switched between NTSC and PAL (DPAL using external delay line and SPAL) by
the serial bus settings.
• Trap, BPF
The center frequency of the built-in trap and BPF can be switched to 3.58MHz during NTSC and 4.43MHz
during PAL.
During composite input, the Y signal enters the trap circuit and the C signal enters the BPF. These signals do
not pass through the trap or BPF during Y/C input and Y/color difference input.
• ACC detection, ACC amplifier
The amplitude of the burst signal output from the ACC amplifier is detected and the ACC amplifier is
controlled to maintain the burst signal amplitude at a constant level.
• VXO, APC detection
The VXO local oscillation circuit is a crystal oscillation circuit. The phases of the input burst signal and the
VXO oscillator output are compared in the APC detection block, and the detective output is used to form a
PLL loop that controls the VXO oscillation frequency, which means that the need for adjustments is
eliminated.
• External inputs
These are digital inputs with two thresholds. When one of the RGB inputs is higher than the lower threshold
Vth1 (≈ 1.0V), all RGB outputs go to black level. When the higher threshold Vth2 (≈ 2.0V) is exceeded, the
output for only the signal in question goes to white level, while the other outputs remain at black level.
– 31 –
CXA2503AR
2) RGB driver block
• γ correction
In order to support the characteristics of LCD panels, the I/O characteristics are as shown in Fig. 1. The
characteristics change as shown in Fig. 2 by adjusting the serial bus register γ1, and as shown in Fig. 3 by
adjusting γ2.
B'
Output
Output
Output
B'
A'
B
A
A
B
B
A
Input
Input
Fig. 1
Input
Fig. 2
Fig. 3
• Sample-and-hold circuit
As LCD panels sample RGB signals simultaneously, RGB signals output from the CXA2503AR must be
sampled-and-held in sync with the LCD panel drive pulses.
S/H1
R
S/H2
G
S/H4
HCK1
S/H4
A
B
S/H3
B
S/H4
C
SH1 SH2 SH3 SH4
RGT = H (normal)
SH1
SH2
RGT = L (inverted)
SHS1
SHS2
SHS3
B
A
C
Through Through Through
SHS1
SHS2
SHS3
SH1
B
A
C
SH2
A
C
B
SH3
A
C
B
SH3
SH4
C
B
A
SH4
Through Through Through
C
B
A
SH1: R signal SH pulse
SH2: G signal SH pulse
SH3: B signal SH pulse
SH4: RGB signal SH pulse
The sample-and-hold circuit performs sample and hold by receiving the SH1 to SH4 pulses from the TG
block. Since LCD panels perform color coding using an RGB delta arrangement, each horizontal line must
be compensated by 1.5 dots. This relationship is reversed during right/left inversion. This compensation
timing is also generated by the TG block. The sample-and-hold timing changes according to the phase
relationship with the HCK1 pulse, so the timing should be set to SHS1, 2 or 3 in accordance with the actual
board.
– 32 –
CXA2503AR
• RGB output
RGB outputs (Pins 41, 43, and 45) are inverted each horizontal line by the FRP pulse supplied from the TG
block as shown in the figure below. Feedback is applied so that the center voltage (Vsig center) of the output
signal matches the reference voltage (VCC2 + GND2)/2 (or the voltage input to SIG CENTER (Pin 48)). In
addition, the white level output is clipped by the Vsig center ±0.7V, and the black level output is clipped by
the limiter operation point that is adjusted at the BLKLIM (Pin 53).
Video IN
FRP
Black level limiter
White level limiter
Vsig center
White level limiter
RGB OUT
Black level limiter
3) TG block
• PLL and AFC circuits
The TG block contains a PLL circuit phase comparator and frequency division counter, and a PLL circuit can
be comprised by connecting an external VCO circuit.
The PLL error detection signal is generated at the following timing. The phase comparison output of the
entire bottom of HSYNC and the internal frequency division counter becomes RPD. RPD output is converted
to DC error with the lag-lead filter, and then it changes the varicap capacitance to stabilize the oscillation
frequency at 702fH in the LCX005BK/BKB and 1050fH in the LCX009AK/AKB. The PLL of this system is
adjusted by setting the serial bus register PLL ADJ so that RPD changes in the center of the window as
shown in the figure below.
H SYNC
WS
RPD
WL
WH
WL = WH
• H position
The horizontal display position can be set at 2fH intervals in 32 different ways by the serial bus settings.
The picture center is set at the internal default value, but because there is a difference between the RGB
signal and the drive pulse delays on the actual board, the picture center may not match the design center. In
this case, adjust with the serial bus.
– 33 –
CXA2503AR
• Right/left inversion
The LCD panel is arranged in a delta pattern, where identical signal lines are offset by 1.5 dots from
adjoining lines. For this reason, a 1.5-bit offset is attached to the horizontal start pulse (HST) between odd
lines and even lines. HCK and S/H are also 1.5-bit offset in a similar manner.
When the panel is driven by left scan (Reverse scan), this offset relationship is inverted for even and odd
lines. Moreover, since the dot arrangement is asymmetrical, the HST position is also changed.
RGT = H: Right scan mode
RGT = L: Left scan mode
Left scan
(Reverse scan)
Right scan
(Normal scan)
V SCANNER
H SCANNER
Display area
LCD panel
• WIDE mode
Setting the WIDE mode by switching the aspect ratio with the serial bus shifts the unit to WIDE mode. In this
mode, the aspect ratio is converted through pulse eliminator processing, allowing 16:9 quasi-WIDE display.
During WIDE mode, vertical pulse eliminator scanning of 1/4 for NTSC or 1/2 and 1/4 for PAL are performed,
and the video signal is compressed to achieve a 16:9 aspect ratio. In addition, in areas outside the display
area, black is displayed by performing high-speed scanning.
The timing during high-speed scanning is a 2H cycle pulse consisting of normal drive (1H) and quadruplespeed drive (1H) and black signals are written in the 28 and 27 lines, respectively at the top and bottom of
this display area. During this time, FRP is changed to a 4H cycle, HST to a 2H cycle, and EN and CLR are
not output.
Vertical high-speed scanning
See the attached sheets for detailed timing.
218LINE
(225LINE)
Display area
4:3 display
Black display area
28LINE
(28LINE)
Display area
163LINE
(169LINE)
Black display area
27LINE
(28LINE)
Vertical pulse eliminator scanning 16:9 display
(during normal-speed scanning)
Numbers in parentheses are for the LCX009AK/AKB.
All other numbers are for the LCX005BK/BKB.
– 34 –
CXA2503AR
During high-speed scanning
During normal-speed scanning
VCK1
Quadruple-speed scanning
Normal-speed scanning
HST
2H cycle
FRP
(internal pulse)
4H cycle
SBLK
(internal pulse)
• AC driving of LCD panels during no signal
HST, HCK1, HCK2, VST, VCK1, VCK2, HD, VD1, VD2 and FRP are made to run free so that the LCD panel
is AC driven even when there is no composite sync from the SYNC IN pin.
During this time, the HSYNC separation circuit stops and the PLL counter is made to run free. In addition, the
VSYNC separation circuit is also stopped, so the auxiliary V counter is used to create the reference pulse for
generating VD1 and VST.
The cycle of this V counter is designed to be 269H for NTSC and 321H for PAL. However, when there is no
vertical sync signal for 5 frames, the no signal state is assumed and the free running VD1 and VST pulses
are generated from the next field.
In addition, RPD is kept at high impedance when there is no signal in order to prevent the AFC circuit from
causing errors due to phase comparison.
– 35 –
CXA2503AR
Description of Serial Control Operation
1) Control method
Control data consists of 16 bits of data which is loaded one bit at a time at the rising edge of SCLK. This
loading operation starts from the falling edge of LOAD and is completed at the next rising edge. (D13 to D15
are dummy data.)
Digital block control data is established by the vertical sync signal, so if data is transferred multiple times for
the same item, the data immediately before the vertical sync signal is valid.
Analog (electronic attenuator) block control data becomes valid each time the LOAD signal is input.
D15 D14 D13 D12 D11 D10 D9
DATA
D8
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
LOAD
Serial transfer timing
2) Serial data map
The serial data map is as follows.
D15
D14
D13
D12
D11
D10
D9
D8
D7
∗
∗
∗
0
0
0
0
∗
∗
∗
0
0
1
0
∗
∗
∗
0
1
0
∗
∗
∗
1
0
0
0
0
HUE
∗
∗
∗
1
0
0
0
1
COLOR
∗
∗
∗
1
0
0
1
0
BRIGHT
∗
∗
∗
1
0
0
1
1
CONTRAST
∗
∗
∗
1
0
1
0
0
R-BRT
∗
∗
∗
1
0
1
0
1
B-BRT
∗
∗
∗
1
0
1
1
0
γ1
∗
∗
∗
1
0
1
1
1
γ2
∗
∗
∗
1
1
0
0
0
PLL ADJ
S/H phase
0
0
D6
D5
D4
D3
VD
HD
Supported
polarity polarity panel
D1
System
D0
Input
switching
Y/color
External FRP
SYNC FRP256
Mode Aspect difference
1F
VSYNC polarity GEN inversion
clamp
HD-POSITION
– 36 –
D2
H-POSITION
CXA2503AR
3) Serial data mode settings
• Input switching
D1
D0
0
X
Composite input (default)
1
0
Y/C input
1
1
Y/color difference input
• System switching
D3
D2
0
X
NTSC (default)
1
0
D-PAL
1
1
S-PAL
• Supported panel switching
D4
0
LCX005 (default)
1
LCX009
• HD output polarity switching
D5
0
Negative polarity (default)
1
Positive polarity
• VD1 output polarity switching
D6
0
Negative polarity (default)
1
Positive polarity
• Sample-and-hold timing switching
D8
D7
0
0
SHS1 (default)
0
1
SHS2
1
0
SHS3
1
1
Through (sample-and-hold not performed)
• Y/color difference clamp position switching
This switches the position at which the R-Y and B-Y input signals are clamped during Y/color difference input
mode.
D0
0
Pedestal position (default)
1
SYNC position
• Aspect switching
D1
0
4:3 (normal) (default)
1
16:9 (pulse eliminator WIDE)
• Mode switching
This is the test mode. Set to normal mode.
D2
0
Normal mode (default)
1
Test mode
– 37 –
CXA2503AR
• FRP256 field inversion
This further inverts the polarity of the RGB output that is inverted every 1H for 256 fields.
D3
0
OFF (default)
1
ON
• Sync generator function
This stops the HST, VST and FRP outputs of the TG block.
D4
0
OFF (default)
1
ON
• FRP polarity inversion function
D5
0
ON (1H inversion) (default)
1
OFF (polarity not inverted)
• External VSYNC input switching
Internal VSYNC separation is not performed and an externally input VSYNC is used.
D6
0
OFF (default)
1
ON
• H position setting
D4
D3
D2
D1
D0
0
0
0
0
0
to
to
to
to
to
1
0
0
0
0 (default)
to
to
to
to
to
1
1
1
1
1
Variable in 2fH (= 1 bit) increments
CLK (internal)
10001
HST
10000
01111
1 step 1 step
• HD phase setting
D9
D8
D7
D6
D5
0
0
0
0
0 (default)
to
to
to
to
to
1
1
1
1
1
Variable in 4fH (= 1 bit) increments
HSYNC
HD
00000
11111
31 steps
– 38 –
CXA2503AR
4) Serial data electronic attenuator (D/A converter) settings
• HUE
D7
D6
1
0
• COLOR
D7
D6
1
0
• BRIGHT
D7
D6
1
0
• CONTRAST
D7
D6
1
0
• R-BRT
D7
D6
1
0
• B-BRT
D7
D6
1
0
• γ-1
D7
D6
0
0
• γ-2
D7
D6
0
0
• PLL-ADJ
D7
D6
1
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0 (default)
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0 (default)
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0 (default)
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0 (default)
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0 (default)
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0 (default)
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0 (default)
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0 (default)
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0 (default)
– 39 –
CXA2503AR
LCX005BK/BKB and LCX009AK/AKB Color Coding Diagram
The delta arrangement is used for the color coding in the LCD panels with which this IC is compatible. Note
that the shaded region within the diagram is not displayed.
LCX005BK/BKB pixel arrangement
dummy1
HSW1
dummy1
dummy2
G
B
Vline1
Vline2
B
R
G
B
Vline3
G
Vline218
R
B
dummy3
G
G
B
G
B
R
B
R
G
R
G
B
G
R
G
B
R
B
R
G
B
R
B
B
B
R
G
R
G
G
B
R
G
R
G
B
G
B
R
G
G
R
B
B
B
G
R
R
R
B
G
R
B
G
G
G
B
G
R
R
B
R
B
G
R
G
218 222
G
R
B
R
G
R
B
R
G
B
G
2
R
B
R
B
G
R
G
B
G
R
B
R
G
R
B
G
B
R
B
G
R
G
R
B
dummy2 to 5
G Photo-shielding
B R G B R
area
B R G B R G
B
G
R
HSW175
R
B
G
B
R
G
R Display
G B area
R
B
G
G
R
B
G
R
G
R
B
HSW174
R
B
G
R
B
R
B
G
B
G
R
B
G
B
G
R
G
R
B
G
R
G
R
B
R
B
G
R
B
G
G
R
B
B
R
B
G
R
B
B
G
R
G
R
B
G
Vline217
G
R
B
R
B
HSW3
HSW2
R
B
2
dummy4
B
R
3
G
B
R
G
B
R
G
B
R
G
B
521
Basic specifications
Total horizontal dots:
537H
Horizontal display dots: 521H
Total dots:
Display dots:
– 40 –
G
B
R
13
537
Total vertical dots:
Vertical display dots:
R
222H
218H
119,214H
113,578H
G
CXA2503AR
LCX009AK/AKB pixel arrangement
dummy1 to 4
dummy1
dummy2
B
R
Vline1
Vline2
R
G
B
R
R
G
R
dummy3
G
B
Vline225
R
B
B
R
G
R
R
G
B
G
G
B
R
R
G
B
G
R
14
G
B
R
G
B
G
B
R
G
G
B
R
G
B
R
G
B
B
B
B
800
Basic specifications
Total horizontal dots:
827H
Horizontal display dots: 800H
Total dots:
Display dots:
228H
225H
188,556H
180,000H
– 41 –
G
B
R
G
R
G
R
R
R
G
B
R
225 228
G
B
G
B
G
R
B
R
B
G
R
G
R
B
R
B
13
827
Total vertical dots:
Vertical display dots:
R
R
B
G
G
B
G
R
B
G
B
G
R
R
G
R
B
G
R
G
B
G
R
R
G
R
B
G
R
G
R
B
B
R
B
G
R
G
2
area
G B
R
B
dummy5 to 8
R G B R
B Photo-shielding
G
R
B
G
R
B
R
B
R
B
G
R
HSW268
R
B R area
G
G Display
R
B
B
G
R
B
G
B
G
R
B
G
R
B
G
R
G
R
B
HSW267
R
B
G
R
B
R
B
G
B
G
R
B
G
B
G
R
G
R
B
G
R
G
R
B
HSW2
R
B
G
R
B
R
B
G
B
G
R
B
Vline224
B
G
R
G
R
B
Vline3
HSW1
R
G
1
– 42 –
VST/VD1
EN
(PAL)
CLR
VCK2
VCK1
SH3
(Internal pulse)
SH1
(Internal pulse)
SH4
(Internal pulse)
SH2
(Internal pulse)
FRP
(Internal pulse)
HCK2
HCK1
HST
HD
(BLK)
SYNC
MCK
5fH
3.0µs (33fH)
4.5µs (50fH)
ODD LINE
EVEN FIELD
2.0µs (22fH)
4.7µs (52fH)
0.5µs (6fH)
19.5fH
22.5fH
13fH
Unless otherwise specified, serial settings are the default values.
RGT: H (Normal scan)
702fH
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
ODD FIELD
4.7µs (52fH)
LCX005BK/BKB Horizontal Direction Timing Chart
NTSC/PAL
CXA2503AR
– 43 –
VST/VD1
EN
(PAL)
CLR
VCK2
VCK1
SH3
(Internal pulse)
SH1
(Internal pulse)
SH4
(Internal pulse)
SH2
(Internal pulse)
FRP
(Internal pulse)
HCK2
HCK1
HST
HD
(BLK)
SYNC
MCK
5fH
3.0µs (33fH)
4.5µs (50fH)
EVEN LINE
EVEN FIELD
2.0µs (22fH)
4.7µs (52fH)
13fH
0.5µs (6fH)
18.0fH
21.0fH
Unless otherwise specified, serial settings are the default values.
RGT: H (Normal scan)
702fH
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
ODD FIELD
4.7µs (52fH)
LCX005BK/BKB Horizontal Direction Timing Chart
NTSC/PAL
CXA2503AR
– 44 –
VST/VD1
EN
(PAL)
CLR
VCK2
VCK1
SH3
(Internal pulse)
SH1
(Internal pulse)
SH4
(Internal pulse)
SH2
(Internal pulse)
FRP
(Internal pulse)
HCK2
HCK1
HST
HD
(BLK)
SYNC
MCK
5fH
3.0µs (34fH)
4.5µs (50fH)
ODD LINE
EVEN FIELD
2.0µs (22fH)
4.7µs (52fH)
0.5µs (5fH)
18.0fH
22.0fH
13fH
Unless otherwise specified, serial settings are the default values.
RGT: L (Reverse scan)
702fH
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
ODD FIELD
4.7µs (52fH)
LCX005BK/BKB Horizontal Direction Timing Chart
NTSC/PAL
CXA2503AR
– 45 –
VST/VD1
EN
(PAL)
CLR
VCK2
VCK1
SH3
(Internal pulse)
SH1
(Internal pulse)
SH4
(Internal pulse)
SH2
(Internal pulse)
FRP
(Internal pulse)
HCK2
HCK1
HST
HD
(BLK)
SYNC
MCK
5fH
3.0µs (34fH)
4.5µs (50fH)
EVEN LINE
EVEN FIELD
2.0µs (22fH)
4.7µs (52fH)
0.5µs (5fH)
19.5fH
23.5fH
13fH
Unless otherwise specified, serial settings are the default values.
RGT: L (Reverse scan)
702fH
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
ODD FIELD
4.7µs (52fH)
LCX005BK/BKB Horizontal Direction Timing Chart
NTSC/PAL
CXA2503AR
– 46 –
VST/VD1
EN
(PAL)
CLR
VCK2
VCK1
SH3
(Internal pulse)
SH1
(Internal pulse)
SH4
(Internal pulse)
SH2
(Internal pulse)
FRP
(Internal pulse)
HCK2
HCK1
HST
HD
(BLK)
SYNC
MCK
2.0µs (33fH)
3.0µs (50fH)
ODD LINE
EVEN FIELD
4.5µs (73fH)
4.7µs (78fH)
0.5µs (8fH)
44.5fH
22.5fH
12fH
Unless otherwise specified, serial settings are the default values.
RGT: H (Normal scan)
1050fH
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
1fH
ODD FIELD
4.7µs (78fH)
LCX009AK/AKB Horizontal Direction Timing Chart
NTSC/PAL
CXA2503AR
– 47 –
VST/VD1
EN
(PAL)
CLR
VCK2
VCK1
SH3
(Internal pulse)
SH1
(Internal pulse)
SH4
(Internal pulse)
SH2
(Internal pulse)
FRP
(Internal pulse)
HCK2
HCK1
HST
HD
(BLK)
SYNC
MCK
2.0µs (33fH)
3.0µs (50fH)
EVEN LINE
EVEN FIELD
4.5µs (73fH)
4.7µs (78fH)
0.5µs (8fH)
43.0fH
21.0fH
12fH
Unless otherwise specified, serial settings are the default values.
RGT: H (Normal scan)
1050fH
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
1fH
ODD FIELD
4.7µs (78fH)
LCX009AK/AKB Horizontal Direction Timing Chart
NTSC/PAL
CXA2503AR
– 48 –
VST/VD1
EN
(PAL)
CLR
VCK2
VCK1
SH3
(Internal pulse)
SH1
(Internal pulse)
SH4
(Internal pulse)
SH2
(Internal pulse)
FRP
(Internal pulse)
HCK2
HCK1
HST
HD
(BLK)
SYNC
MCK
2.0µs (33fH)
3.0µs (51fH)
ODD LINE
EVEN FIELD
4.5µs (73fH)
4.7µs (78fH)
0.5µs (7fH)
43.0fH
22.0fH
12fH
Unless otherwise specified, serial settings are the default values.
RGT: L (Reverse scan)
1050fH
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
1fH
ODD FIELD
4.7µs (78fH)
LCX009AK/AKB Horizontal Direction Timing Chart
NTSC/PAL
CXA2503AR
– 49 –
VST/VD1
EN
(PAL)
CLR
VCK2
VCK1
SH3
(Internal pulse)
SH1
(Internal pulse)
SH4
(Internal pulse)
SH2
(Internal pulse)
FRP
(Internal pulse)
HCK2
HCK1
HST
HD
(BLK)
SYNC
MCK
2.0µs (33fH)
3.0µs (51fH)
EVEN LINE
EVEN FIELD
4.5µs (73fH)
4.7µs (78fH)
0.5µs (7fH)
44.5fH
23.5fH
12fH
Unless otherwise specified, serial settings are the default values.
RGT: L (Reverse scan)
1050fH
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
1fH
ODD FIELD
4.7µs (78fH)
LCX009AK/AKB Horizontal Direction Timing Chart
NTSC/PAL
CXA2503AR
– 50 –
VD2
HD
VD1
FLD OUT
FRP
(Internal pulse)
CLR
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
SYNC
(VD)
596fH
ODD FIELD
596fH
Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
(1F inversion)
LCX005BK/BKB Vertical Direction Timing Chart
NTSC
CXA2503AR
– 51 –
VD2
HD
VD1
FLD OUT
FRP
(Internal pulse)
CLR
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
SYNC
(VD)
246fH
EVEN FIELD
246fH
Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
(1F inversion)
LCX005BK/BKB Vertical Direction Timing Chart
NTSC
CXA2503AR
– 52 –
VD2
HD
VD1
FLD OUT
(1F inversion)
596fH
ODD FIELD
596fH
Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
FRP
(Internal pulse)
CLR
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
SYNC
(VD)
LCX005BK/BKB Vertical Direction Timing Chart
PAL
CXA2503AR
– 53 –
(1F inversion)
246fH
EVEN FIELD
246fH
Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
VD2
HD
VD1
FLD OUT
FRP
(Internal pulse)
CLR
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
SYNC
(VD)
LCX005BK/BKB Vertical Direction Timing Chart
PAL
CXA2503AR
– 54 –
VD2
HD
VD1
FLD OUT
FRP
(Internal pulse)
CLR
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
SYNC
(VD)
714fH
ODD FIELD
714fH
Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
(1F inversion)
LCX009AK/AKB Vertical Direction Timing Chart
NTSC
CXA2503AR
– 55 –
VD2
HD
VD1
FLD OUT
FRP
(Internal pulse)
CLR
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
SYNC
(VD)
314fH
EVEN FIELD
314fH
Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
(1F inversion)
LCX009AK/AKB Vertical Direction Timing Chart
NTSC
CXA2503AR
– 56 –
(1F inversion)
714fH
ODD FIELD
714fH
Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
VD2
HD
VD1
FLD OUT
FRP
(Internal pulse)
CLR
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
SYNC
(VD)
LCX009AK/AKB Vertical Direction Timing Chart
PAL
CXA2503AR
– 57 –
(1F inversion)
314fH
EVEN FIELD
314fH
Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
VD2
HD
VD1
FLD OUT
FRP
(Internal pulse)
CLR
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
SYNC
(VD)
LCX009AK/AKB Vertical Direction Timing Chart
PAL
CXA2503AR
– 58 –
SBLK
(Internal pulse)
VD2
HD
VD1
FLD OUT
FRP
(Internal pulse)
CLR
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
SYNC
(VD)
596fH
ODD FIELD
596fH
163-line display area
1/4 pulse elimination
Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
(1F inversion)
LCX005BK/BKB Vertical Direction Timing Chart
NTSC WIDE
CXA2503AR
– 59 –
SBLK
(Internal pulse)
VD2
HD
VD1
FLD OUT
FRP
(Internal pulse)
CLR
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
SYNC
(VD)
246fH
EVEN FIELD
246fH
163-line display area
1/4 pulse elimination
Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
(1F inversion)
LCX005BK/BKB Vertical Direction Timing Chart
NTSC WIDE
CXA2503AR
– 60 –
SBLK
(Internal pulse)
VD2
HD
VD1
FLD OUT
FRP
(Internal pulse)
CLR
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
SYNC
(VD)
ODD FIELD
596fH
596fH
163-line display area
Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
(1F inversion)
LCX005BK/BKB Vertical Direction Timing Chart
PAL WIDE
CXA2503AR
– 61 –
SBLK
(Internal pulse)
VD2
HD
VD1
FLD OUT
EVEN FIELD
246fH
246fH
163-line display area
Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
FRP
(Internal pulse) (1F inversion)
CLR
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
SYNC
(VD)
LCX005BK/BKB Vertical Direction Timing Chart
PAL WIDE
CXA2503AR
– 62 –
SBLK
(Internal pulse)
VD2
HD
VD1
FLD OUT
FRP
(Internal pulse)
CLR
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
SYNC
(VD)
714fH
ODD FIELD
714fH
169-line display area
1/4 pulse elimination
Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
(1F inversion)
LCX009AK/AKB Vertical Direction Timing Chart
NTSC WIDE
CXA2503AR
– 63 –
SBLK
(Internal pulse)
VD2
HD
VD1
FLD OUT
FRP
(Internal pulse)
CLR
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
SYNC
(VD)
314fH
EVEN FIELD
314fH
169-line display area
1/4 pulse elimination
Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
(1F inversion)
LCX009AK/AKB Vertical Direction Timing Chart
NTSC WIDE
CXA2503AR
– 64 –
SBLK
(Internal pulse)
VD2
HD
VD1
FLD OUT
FRP
(Internal pulse)
CLR
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
SYNC
(VD)
ODD FIELD
714fH
714fH
169-line display area
Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
(1F inversion)
LCX009AK/AKB Vertical Direction Timing Chart
PAL WIDE
CXA2503AR
– 65 –
SBLK
(Internal pulse)
VD2
HD
VD1
FLD OUT
FRP
(Internal pulse)
CLR
EN
HST
FRP
(Internal pulse)
VCK2
VCK1
VST
(BLK)
SYNC
(VD)
EVEN FIELD
314fH
314fH
169-line display area
Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
(1F inversion)
LCX009AK/AKB Vertical Direction Timing Chart
PAL WIDE
CXA2503AR
CXA2503AR
Application Circuit (NTSC/PAL, COMP and Y/C input)
+12V
To LCD panel
+4.5V
0.1µ
47µ
To Serial controller
0.47µ
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VCC2
FB R
R OUT
FB G
G OUT
FB B
B OUT
GND2
RGT
TEST4
TEST3
TEST2
LOAD
DATA
SCLK
0.47µ
47
+4.5V
49 VCC1
0.1µ
0.47µ
48
SIG.CENTER
0.01µ
47µ
VSS2 32
50 B-Y IN
VD2 31
51 R-Y IN
VD1 30
52 C OUT
EN 29
0.01µ
+4.5V
0.01µ
47k
0.01µ
53 BLK LIM
VCK1 28
54 APC
VCK2 27
∗1
15k
0.068µ
55 VXO OUT
VST 26
0.22µ
∗2
+4.5V
1µ
56 VXO IN
TEST1 25
57 V REG
FLD IN 24
To LCD panel
FLD OUT 23
58 START UP
Y/C
C IN
COMP
59 C IN
HD 22
∗6 82k
+4.5V
60 F0 ADJ
HCK1 21
61 GND3
HCK2 20
62 Y IN
HST 19
63 PIC
CLR 18
GND1
SYNC IN
H.FIL OUT
S.SEP IN
EXT R
EXT G
EXT B
VCO ADJ
RPD
VSS1
CKI
CKO
VDD1
64 TEST0
TRAP
0.01µ
VD IN
47k
PWRST
1µ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0.01µ
VDD2 17
∗4
750
0.47µ
COMP/Y IN
3V
220p
1k
68p
47µ
0.1µ
0.033µ
33k
10k
3300p
∗5
∗3
3.3µ
10k
∗1 Used crystal: KINSEKI CX-5F
Frequency deviation: within ±30ppm, frequency temperature
characteristics: within ±30ppm, load capacity: 16pF
NTSC: 3.579545MHz
PAL: 4.433619MHz
∗2 NTSC: none, PAL: 18pF
∗3 Varicap diode: 1T369 (SONY)
∗4 L value: 8.2µH during LCX005 mode
3.9µH during LCX009 mode
∗5 Trap (TDK), open during Y/C input
NTSC: NLT4532-S3R6B
PAL: NLT4532-S4R4
∗6 Resistance value variation: ±2%,
temperature coefficient: ±200ppm or less
Connect to +4.5V during Y/C input
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 66 –
CXA2503AR
Application Circuit (NTSC/PAL, Y/color difference input)
+12V
To LCD panel
+4.5V
0.1µ
47µ
To Serial controller
0.47µ
49 VCC1
B-Y IN
45
44
43
42
41
40
39
38
37
36
35
34
33
R OUT
FB G
G OUT
FB B
B OUT
GND2
RGT
TEST4
TEST3
TEST2
LOAD
DATA
SCLK
47µ
0.1µ
0.47µ
46
FB R
+4.5V
0.47µ
47
SIG.CENTER
48
VCC2
0.01µ
VSS2 32
50 B-Y IN
VD2 31
51 R-Y IN
VD1 30
52 C OUT
EN 29
0.1µ
R-Y IN
0.1µ
+4.5V
53
47k
VCK1 28
BLK LIM
0.01µ
VCK2 27
54 APC
55 VXO OUT
+4.5V
1µ
VST 26
56 VXO IN
TEST1 25
57 V REG
FLD IN 24
To LCD panel
FLD OUT 23
58 START UP
59 C IN
+4.5V
+4.5V
HD 22
60 F0 ADJ
HCK1 21
61 GND3
HCK2 20
62 Y IN
HST 19
63 PIC
CLR 18
GND1
SYNC IN
H.FIL OUT
S.SEP IN
EXT R
EXT G
EXT B
VCO ADJ
RPD
VSS1
CKI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0.01µ
VDD1
15
16
3V
∗2
750
0.47µ
Y IN
VDD2 17
CKO
64 TEST0
TRAP
0.01µ
VD IN
47k
PWRST
1µ
68p
220p
1k
47µ
0.1µ
0.033µ
33k
10k
3300p
∗1
3.3µ
10k
∗1 Varicap diode: 1T369 (SONY)
∗2 L value: 8.2µH during LCX005 mode
3.9µH during LCX009 mode
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 67 –
CXA2503AR
Example of Representative Characteristics
HUE adjustment characteristics
COLOR adjustment characteristics
50
10
30
0
20
10
Gain [dB]
HUE adjustment angle [deg]
40
0
–10
–20
–10
–20
–30
–30
–40
–50
–60
–40
0
30
60
90
0C0
0F0
0
30
DAC value
0C0
0F0
CONTRAST adjustment characteristics
8
14
7
13
6
12
5
11
4
10
3
9
2
8
1
7
0
6
–1
5
10
5
0
Output gain [dB]
Inverted output black level [V]
Non-inverted output black level [V]
90
DAC value
BRIGHT adjustment characteristics
–5
–10
–15
–20
–2
–25
4
0
30
60
90
0C0
0F0
0
30
Non-inverted black
Inverted black
DAC value
60
90
0C0
0F0
DAC value
SUB-BRIGHT adjustment characteristics
PLL adjustment voltage
1.0
10
0.5
9
Pin 11 output voltage [V]
Voltage change with respect to G output [V]
60
0
–0.5
–1.0
8
7
6
–1.5
5
0
30
60
90
0C0
0F0
0
DAC value
30
60
90
DAC value
– 68 –
0C0
0F0
CXA2503AR
Color difference balance adjustment
Black level limiter adjustment characteristics
10
5
9
Limiter level [Vp-p]
Gain [dB]
3
1
–1
–3
8
7
6
5
4
–5
0
30
60
90
DAC value
0C0
1.0
0F0
1.5
2.0
2.5
3.0
Pin voltage [V]
B-Y output
R-Y output
– 69 –
3.5
4.0
CXA2503AR
Sharpness characteristics (COMP, NTSC, 005)
Sharpness characteristics (COMP, NTSC, 009)
15
10
10
5
5
0
Gain [dB]
Gain [dB]
0
–5
–10
–10
–15
–15
–20
–20
–25
–25
–30
–30
0
2
4
6
8
Frequency [MHz]
10
0
2
4
6
8
Frequency [MHz]
0V
2.25V
4V
Sharpness characteristics (COMP, PAL, 005)
10
0V
2.25V
4V
Sharpness characteristics (COMP, PAL, 009)
15
10
10
5
5
0
Gain [dB]
0
Gain [dB]
–5
–5
–10
–5
–10
–15
–15
–20
–20
–25
–25
–30
–30
0
2
4
6
8
Frequency [MHz]
10
0
2
4
6
8
Frequency [MHz]
0V
2.25V
4V
Sharpness characteristics (Y/C, 005)
10
0V
2.25V
4V
Sharpness characteristics (Y/C, 009)
15
20
15
10
10
5
Gain [dB]
Gain [dB]
5
0
–5
0
–5
–10
–10
–15
–15
–20
–20
0
2
4
6
Frequency [MHz]
8
10
0
2
4
6
Frequency [MHz]
0V
2.25V
4V
– 70 –
8
10
0V
2.25V
4V
CXA2503AR
Notes on Operation
The CXA2503AR contains digital circuits, so the set board pattern must be designed in consideration of
undesired radiation, interference to analog circuits, etc. Care should also be taken for the following items when
designing the pattern.
• Make the IC power supply and GND patterns as plain as possible. In particular, GND and VSS should not be
separated and should be connected to the same GND pattern as close to the pins as possible.
• Connect the by-pass capacitors between the power supplies and GND as close to the pins as possible.
• The trap connected to Pin 3 should be located as close to the pin as possible. Also, take care not to pass
other signal lines close to this pin or the connected trap.
• The wiring for the crystal and capacitor connected to Pins 55 and 56 should be as short as possible in order
to prevent floating capacitance. Take care not to pass other signal lines close to these pins in order to
prevent interference such as color unevenness. In addition, the APC pull-in characteristics vary significantly
according to the characteristics of the used crystal and the wiring pattern, so be sure to thoroughly
investigate these items before using the set.
• The resistor connected to Pin 60 should be located as close to the pin as possible. Also, take care not to
pass other signal lines close to this pin.
The composite/Y signal and the external R-Y and B-Y signals are clamped at the inputs using the capacitors
connected to the input pins, so these signals should be input at sufficiently low impedance. The C signal is
received by the internal capacitor, so an appropriate DC bias should be applied to this signal from an external
source and this signal should be input at low impedance.
The smoothing capacitor of the DC level control feedback circuit in the output block should have a leak current
with a small absolute value and variance.
This IC has a MOS structure which is easily damaged by static electricity, so thorough measures should be
taken to prevent electrostatic discharge.
– 71 –
CXA2503AR
Package Outline
Unit: mm
64PIN LQFP (PLASTIC)
12.0 ± 0.2
10.0 ± 0.2
0.15 ± 0.05
48
0.1
33
49
32
A
64
17
1
1.25
16
+ 0.08
0.18 – 0.03
0.5
1.7 MAX
0.1
M
0° to 10°
0.5 ± 0.2
(0.5)
0.1 ± 0.1
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
LQFP-64P-L061
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LQFP064-P-1010-AY
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
0.3g
JEDEC CODE
– 72 –