KAI 01050 D

KAI-01050
1024 (H) x 1024 (V) Interline
CCD Image Sensor
Description
The KAI−01050 Image Sensor is a 1−megapixel CCD in a 1/2”
optical format. Based on the TRUESENSE 5.5 micron Interline
Transfer CCD Platform, the sensor features broad dynamic range,
excellent imaging performance, and a flexible readout architecture
that enables use of 1, 2, or 4 outputs for full resolution readout up to
120 frames per second. A vertical overflow drain structure suppresses
image blooming and enables electronic shuttering for precise exposure
control. Other features include low dark current, negligible lag, and
low smear.
The sensor shares common pin−out and electrical configurations
with other devices based on the TRUESENSE 5.5 micron Interline
Transfer CCD Platform, allowing a single camera design to support
multiple members of this sensor family.
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Table 1. GENERAL SPECIFICATIONS
Parameter
Typical Value
Figure 1. KAI−01050 Interline CCD
Image Sensor
Architecture
Interline CCD, Progressive Scan
Total Number of Pixels
1084 (H) × 1064 (V)
Number of Effective Pixels
1040 (H) × 1040 (V)
Number of Active Pixels
1024 (H) × 1024 (V)
Features
Pixel Size
5.5 mm (H) × 5.5 mm (V)
Active Image Size
5.632 mm (H) × 5.632 mm (V)
7.96 mm (diagonal), 1/2″ Optical Format
Aspect Ratio
1:1
Number of Outputs
1, 2, or 4
Charge Capacity
20,000 electrons
Output Sensitivity
34 mV/e−
Quantum Efficiency
Monochrome
(−ABA)
R, G, B
(−FBA)
R, G, B
(−CBA)
44%
31%, 37%, 38%
29%, 37%, 39%
•
•
•
•
•
•
•
•
Read Noise (f = 40 MHz)
12 e− rms
Dark Current
Photodiode / VCCD
7 / 140 e−/s
Dark Current Doubling Temp
Photodiode / VCCD
7°C / 9°C
Dynamic Range
64 dB
Charge Transfer Efficiency
0.999999
Blooming Suppression
> 300 X
Smear
−100 dB
Image Lag
< 10 electrons
Maximum Pixel Clock Speed
40 MHz
Maximum Frame Rate
Quad / Dual / Single Output
120 / 60 / 30 fps
Package
68 Pin PGA
64 Pin CLCC
Cover Glass
AR Coated, 2-Sides
Color or Monochrome Configurations
Progressive Scan Readout
Flexible Readout Architecture
High Frame Rate
High Sensitivity
Low Noise Architecture
Excellent Smear Performance
Package Pin Reserved for Device
Identification
Applications
• Industrial Imaging
• Medical Imaging
• Security
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
NOTE: All Parameters are specified at T = 40°C unless otherwise noted.
© Semiconductor Components Industries, LLC, 2015
July, 2015 − Rev. 5
1
Publication Order Number:
KAI−01050/D
KAI−01050
ORDERING INFORMATION
Standard Devices
See full datasheet for ordering information associated with devices no longer recommended for new designs.
Table 2. ORDERING INFORMATION − STANDARD DEVICES
Part Number
Description
KAI−01050−ABA−JD−BA
Monochrome, Telecentric Microlens, PGA Package, Clear Cover Glass with AR
Coating (Both Sides), Standard Grade
KAI−01050−ABA−JD−AE
Monochrome, Telecentric Microlens, PGA Package, Clear Cover Glass with AR
Coating (Both Sides), Engineering Grade
KAI−01050−ABA−FD−BA
Monochrome, Telecentric Microlens, CLCC Package, Sealed Clear Cover Glass
with AR Coating (Both Sides), Standard Grade
KAI−01050−ABA−FD−AE
Monochrome, Telecentric Microlens, CLCC Package, Sealed Clear Cover Glass
with AR Coating (Both Sides), Engineering Grade
KAI−01050−FBA−JD−BA
Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package, Clear Cover Glass
with AR Coating (Both Sides), Standard Grade
KAI−01050−FBA−JD−AE
Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package, Clear Cover Glass
with AR Coating (Both Sides), Engineering Grade
KAI−01050−FBA−FD−BA
Gen2 Color (Bayer RGB), Telecentric Microlens, CLCC Package, Sealed Clear
Cover Glass with AR Coating (Both Sides), Standard Grade
KAI−01050−FBA−FD−AE
Gen2 Color (Bayer RGB), Telecentric Microlens, CLCC Package, Sealed Clear
Cover Glass with AR Coating (Both Sides), Engineering Grade
Marking Code
KAI−01050−ABA
Serial Number
KAI−01050−FBA
Serial Number
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
Not Recommended for New Designs
Table 3. ORDERING INFORMATION − NOT RECOMMENDED FOR NEW DESIGNS
Part Number
Description
KAI−01050−CBA−JD−BA
Gen1 Color (Bayer RGB), Telecentric Microlens, PGA Package, Clear Cover Glass
with AR Coating (Both Sides), Standard Grade
KAI−01050−CBA−JD−AE
Gen1 Color (Bayer RGB), Telecentric Microlens, PGA Package, Clear Cover Glass
with AR Coating (Both Sides), Engineering Grade
KAI−01050−CBA−FD−BA
Gen1 Color (Bayer RGB), Telecentric Microlens, CLCC Package, Sealed Clear
Cover Glass with AR Coating (Both Sides), Standard Grade
KAI−01050−CBA−FD−AE
Gen1 Color (Bayer RGB), Telecentric Microlens, CLCC Package, Sealed Clear
Cover Glass with AR Coating (Both Sides), Engineering Grade
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2
Marking Code
KAI−01050−CBA
Serial Number
KAI−01050
DEVICE DESCRIPTION
Architecture
H2Bd
H2Sd
H1Bd
H1Sd
SUB
H2Bc
H2Sc
H1Bc
H1Sc
RDc
Rc
VDDc
VOUTc
RDd
Rd
VDDd
VOUTd
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
1 10 22 8
512
512
8 22 10 1
1 Dummy
12
8
GND
OGc
H2SLc
GND
OGd
H2SLd
V1T
V2T
V3T
V4T
V1T
V2T
V3T
V4T
DevID
ESD
V1B
V2B
V3B
V4B
RDa
Ra
VDDa
VOUTa
8 22
BG
G R
8 Buffer
12 Dark
1 Dummy
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
1 10 22 8
ESD
V1B
V2B
V3B
V4B
(Last VCCD Phase = V1 → H1S)
512
512
H2Bb
H2Sb
H1Bb
H1Sb
SUB
H2Ba
H2Sa
H1Ba
H1Sa
GND
OGa
H2SLa
1024 (H) × 1024 (V)
5.5 mm × 5.5 mm Pixels
22 8
8 22 10 1
RDb
Rb
VDDb
VOUTb
GND
OGb
H2SLb
Figure 2. Block Diagram
Dark Reference Pixels
pixels are light sensitive but are not tested for defects and
non-uniformities.
There are 12 dark reference rows at the top and 12 dark
rows at the bottom of the image sensor. The dark rows are not
entirely dark and so should not be used for a dark reference
level. Use the 22 dark columns on the left or right side of the
image sensor as a dark reference.
Under normal circumstances use only the center 20
columns of the 22 column dark reference due to potential
light leakage.
Image Acquisition
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron-hole pairs within the individual silicon
photodiodes. These photoelectrons are collected locally by
the formation of potential wells at each photosite. Below
photodiode saturation, the number of photoelectrons
collected at each pixel is linearly dependent upon light level
and exposure time and non-linearly dependent on
wavelength. When the photodiodes charge capacity is
reached, excess electrons are discharged into the substrate to
prevent blooming.
Dummy Pixels
Within each horizontal shift register there are 11 leading
additional shift phases. These pixels are designated as
dummy pixels and should not be used to determine a dark
reference level.
In addition, there is one dummy row of pixels at the top
and bottom of the image.
ESD Protection
Adherence to the power-up and power-down sequence is
critical. Failure to follow the proper power-up and
power-down sequences may cause damage to the sensor. See
Power-Up and Power-Down Sequence section.
Active Buffer Pixels
8 unshielded pixels adjacent to any leading or trailing dark
reference regions are classified as active buffer pixels. These
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3
KAI−01050
Physical Description
PGA Pin Description and Device Orientation
67
65
63
61
59
57
55
53
51
49
47
45
43
41
39
37
35
V3T
V1T
VDDc
GND
Rc
H2SLc
H1Bc
H2Sc
N/C
H2Sd
H1Bd
H2SLd
Rd
GND
VDDd
V1T
V3T
68
66
64
62
60
58
56
54
52
50
48
46
44
42
40
38
36
ESD
V4T
V2T
VOUTc
RDc
OGc
H2Bc
H1Sc
SUB
H1Sd
H2Bd
OGd
RDd
VOUTd
V2T
V4T
DevID
Pixel
(1,1)
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
V4B
V2B
VOUTa
RDa
OGa
H2Ba
H1Sa
SUB
H1Sb
H2Bb
OGb
RDb
VOUTb
V2B
V4B
ESD
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
V3B
V1B
VDDa
GND
Ra
H2SLa
H1Ba
H2Sa
N/C
H2Sb
H1Bb
H2SLb
Rb
GND
VDDb
V1B
V3B
Figure 3. PGA Package Pin Designations − Top View
Table 4. PGA PACKAGE PIN DESCRIPTION
Pin
Name
1
V3B
Vertical CCD Clock, Phase 3, Bottom
3
V1B
Vertical CCD Clock, Phase 1, Bottom
4
V4B
Vertical CCD Clock, Phase 4, Bottom
5
VDDa
Output Amplifier Supply, Quadrant a
6
V2B
Vertical CCD Clock, Phase 2, Bottom
7
GND
Ground
8
VOUTa
9
Ra
Reset Gate, Quadrant a
10
RDa
Reset Drain, Quadrant a
11
H2SLa
Description
Video Output, Quadrant a
Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant a
12
OGa
Output Gate, Quadrant a
13
H1Ba
Horizontal CCD Clock, Phase 1, Barrier, Quadrant a
14
H2Ba
Horizontal CCD Clock, Phase 2, Barrier, Quadrant a
15
H2Sa
Horizontal CCD Clock, Phase 2, Storage, Quadrant a
16
H1Sa
Horizontal CCD Clock, Phase 1, Storage, Quadrant a
17
N/C
No Connect
18
SUB
Substrate
19
H2Sb
Horizontal CCD Clock, Phase 2, Storage, Quadrant b
20
H1Sb
Horizontal CCD Clock, Phase 1, Storage, Quadrant b
21
H1Bb
Horizontal CCD Clock, Phase 1, Barrier, Quadrant b
22
H2Bb
Horizontal CCD Clock, Phase 2, Barrier, Quadrant b
23
H2SLb
Horizontal CCD Clock, Phase 1, Storage, Last Phase, Quadrant b
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KAI−01050
Table 4. PGA PACKAGE PIN DESCRIPTION (continued)
Pin
Name
Description
24
OGb
Output Gate, Quadrant b
25
Rb
Reset Gate, Quadrant b
26
RDb
Reset Drain, Quadrant b
27
GND
Ground
28
VOUTb
29
VDDb
Output Amplifier Supply, Quadrant b
30
V2B
Vertical CCD Clock, Phase 2, Bottom
31
V1B
Vertical CCD Clock, Phase 1, Bottom
32
V4B
Vertical CCD Clock, Phase 4, Bottom
33
V3B
Vertical CCD Clock, Phase 3, Bottom
34
ESD
ESD Protection Disable
35
V3T
Vertical CCD Clock, Phase 3, Top
36
DevID
37
V1T
Vertical CCD Clock, Phase 1, Top
38
V4T
Vertical CCD Clock, Phase 4, Top
39
VDDd
40
V2T
Vertical CCD Clock, Phase 2, Top
41
GND
Ground
42
VOUTd
Video Output, Quadrant b
Device Identification
Output Amplifier Supply, Quadrant d
Video Output, Quadrant d
43
Rd
Reset Gate, Quadrant d
44
RDd
Reset Drain, Quadrant d
45
H2SLd
46
OGd
Output Gate, Quadrant d
47
H1Bd
Horizontal CCD Clock, Phase 1, Barrier, Quadrant d
48
H2Bd
Horizontal CCD Clock, Phase 2, Barrier, Quadrant d
49
H2Sd
Horizontal CCD Clock, Phase 2, Storage, Quadrant d
50
H1Sd
Horizontal CCD Clock, Phase 1, Storage, Quadrant d
Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant d
51
N/C
No Connect
52
SUB
Substrate
53
H2Sc
Horizontal CCD Clock, Phase 2, Storage, Quadrant c
54
H1Sc
Horizontal CCD Clock, Phase 1, Storage, Quadrant c
55
H1Bc
Horizontal CCD Clock, Phase 1, Barrier, Quadrant c
56
H2Bc
Horizontal CCD Clock, Phase 2, Barrier, Quadrant c
57
H2SLc
Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant c
58
OGc
Output Gate, Quadrant c
59
Rc
Reset Gate, Quadrant c
60
RDc
Reset Drain, Quadrant c
61
GND
Ground
62
VOUTc
Video Output, Quadrant c
63
VDDc
Output Amplifier Supply, Quadrant c
64
V2T
Vertical CCD Clock, Phase 2, Top
65
V1T
Vertical CCD Clock, Phase 1, Top
66
V4T
Vertical CCD Clock, Phase 4, Top
67
V3T
Vertical CCD Clock, Phase 3, Top
68
ESD
EDS Protection Disable
1. Liked named pins are internally connected and should have a common drive signal.
2. N/C pins (17, 51) should be left floating.
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KAI−01050
Rc
OGc
H2SLc
H2Bc
H1Bc
H1Sc
H2Sc
SUB
H2Sd
H1Sd
H1Bd
H2Bd
H2SLd
OGd
Rd
RDd
Ceramic Leadless Chip Carrier Pin Description
48
47
46
45
44 43
42
41 40
39
38
37
36
35 34
33
RDc
49
32
GND
GND
50
31
VOUTd
VOUTc
51
30
VDDd
VDDc
52
29
V2T
V2T
53
28
V1T
V1T
54
27
V4T
V4T
55
26
V3T
V3T
56
25
DevID
ESD
57
24
V3B
V3B
58
23
V4B
V4B
59
22
V1B
21
V2B
Pixel
(1,1)
V1B
60
V2B
61
20
VDDb
7
8
9
10
11
12
SUB
H1Sb
H1Bb
13
14
15 16
Rb
6
OGb
5
H2Bb
4
H2SLb
3
H2Sb
RDb
2
H2Sa
17
1
H1Sa
64
H1Ba
GND
H2Ba
GND
H2SLa
VOUTb
18
OGa
19
63
Ra
62
RDa
VDDa
VOUTa
Figure 4. CLCC Package Pin Designations − Top View
Table 5. CLCC PACKAGE PIN DESCRIPTION
Pin
Name
1
RDa
Reset Drain, Quadrant a
2
Ra
Reset Gate, Quadrant a
3
OGa
Output Gate, Quadrant a
4
H2SLa
Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant a
5
H2Ba
Horizontal CCD Clock, Phase 2, Barrier, Quadrant a
6
H1Ba
Horizontal CCD Clock, Phase 1, Barrier, Quadrant a
7
H1Sa
Horizontal CCD Clock, Phase 1, Storage, Quadrant a
8
H2Sa
Horizontal CCD Clock, Phase 2, Storage, Quadrant a
9
SUB
Substrate
10
H2Sb
Horizontal CCD Clock, Phase 2, Storage, Quadrant b
11
H1Sb
Horizontal CCD Clock, Phase 1, Storage, Quadrant b
12
H1Bb
Horizontal CCD Clock, Phase 1, Barrier, Quadrant b
13
H2Bb
Horizontal CCD Clock, Phase 2, Barrier, Quadrant b
14
H2SLb
Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant b
15
OGb
Output Gate, Quadrant b
16
Rb
Reset Gate, Quadrant b
17
RDb
Reset Drain, Quadrant b
18
GND
Ground
19
VOUTb
20
VDDb
Description
Video Output, Quadrant b
Output Amplifier Supply, Quadrant b
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KAI−01050
Table 5. CLCC PACKAGE PIN DESCRIPTION (continued)
Pin
Name
Description
21
V2B
Vertical CCD Clock, Phase 2, Bottom
22
V1B
Vertical CCD Clock, Phase 1, Bottom
23
V4B
Vertical CCD Clock, Phase 4, Bottom
24
V3B
Vertical CCD Clock, Phase 3, Bottom
25
DevID
26
V3T
Vertical CCD Clock, Phase 3, Top
27
V4T
Vertical CCD Clock, Phase 4, Top
28
V1T
Vertical CCD Clock, Phase 1, Top
29
V2T
Vertical CCD Clock, Phase 2, Top
30
VDDd
31
VOUTd
32
GND
Ground
33
RDd
Reset Drain, Quadrant d
34
Rd
Reset Gate, Quadrant d
35
OGd
Output Gate, Quadrant d
36
H2SLd
Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant d
37
H2Bd
Horizontal CCD Clock, Phase 2, Barrier, Quadrant d
38
H1Bd
Horizontal CCD Clock, Phase 1, Barrier, Quadrant d
39
H1Sd
Horizontal CCD Clock, Phase 1, Storage, Quadrant d
40
H2Sd
Horizontal CCD Clock, Phase 2, Storage, Quadrant d
41
SUB
Substrate
42
H2Sc
Horizontal CCD Clock, Phase 2, Storage, Quadrant c
43
H1Sc
Horizontal CCD Clock, Phase 1, Storage, Quadrant c
44
H1Bc
Horizontal CCD Clock, Phase 1, Barrier, Quadrant c
45
H2Bc
Horizontal CCD Clock, Phase 2, Barrier, Quadrant c
46
H2SLc
Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant c
47
OGc
Output Gate, Quadrant c
48
Rc
Reset Gate, Quadrant c
49
RDc
Reset Drain, Quadrant c
50
GND
Ground
51
VOUTc
Video Output, Quadrant c
52
VDDc
Output Amplifier Supply, Quadrant c
53
V2T
Vertical CCD Clock, Phase 2, Top
54
V1T
Vertical CCD Clock, Phase 1, Top
55
V4T
Vertical CCD Clock, Phase 4, Top
56
V3T
Vertical CCD Clock, Phase 3, Top
57
ESD
ESD Protection Disable
58
V3B
Vertical CCD Clock, Phase 3, Bottom
59
V4B
Vertical CCD Clock, Phase 4, Bottom
60
V1B
Vertical CCD Clock, Phase 1, Bottom
61
V2B
Vertical CCD Clock, Phase 2, Bottom
62
VDDa
Output Amplifier Supply, Quadrant a
63
VOUTa
Video Output, Quadrant a
64
GND
Device Identification
Output Amplifier Supply, Quadrant d
Video Output, Quadrant d
Ground
1. Liked named pins are internally connected and should have a common drive signal.
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KAI−01050
IMAGING PERFORMANCE
Table 6. TYPICAL OPERATION CONDITIONS
Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions.
Condition
Description
Notes
Frame Time
71.6 msec
Electronic shutter is not used.
Integration time equals frame time.
Horizontal Clock Frequency
20 MHz
Light Source
Continuous red, green and blue LED illumination centered at
450, 530 and 650 nm respectively
Operation
Nominal operating voltages and timing
For monochrome sensor, only green
LED used.
Table 7. SPECIFICATIONS
Description
Dark Field Global Non−Uniformity
Bright Field Global Peak to Peak
Non−Uniformity
Nom.
Max.
Units
−
−
2.0
mVpp
Die
27, 40
−
2.0
5.0
%rms
Die
27, 40
1
−
5.0
15.0
%pp
Die
27, 40
1
−
1.0
2.0
%rms
Die
27, 40
1
Symbol
Min.
DSNU
Bright Field Global Non−Uniformity
PRNU
Bright Field Center Non−Uniformity
Temperature
Tested At
(5C)
Sampling
Plan
Notes
Maximum Photoresponse
Nonlinearity
NL
−
2
−
%
Design
2
Maximum Gain Difference Between
Outputs
DG
−
10
−
%
Design
2
Maximum Signal Error due to
Nonlinearity Differences
DNL
−
1
−
%
Design
2
Horizontal CCD Charge Capacity
HNe
−
55
−
ke−
Design
Design
Die
Vertical CCD Charge Capacity
VNe
−
45
−
ke−
Photodiode Charge Capacity
PNe
−
20
−
ke−
Horizontal CCD Charge Transfer
Efficiency
HCTE
0.999995
0.999999
−
Die
Vertical CCD Charge Transfer
Efficiency
VCTE
0.999995
0.999999
−
Die
Ipd
−
7
70
e/p/s
Vertical CCD Dark Current
Ivd
−
140
400
Image Lag
Lag
−
−
10
Antiblooming Factor
Xab
300
−
−
Vertical Smear
Smr
−
−100
−
dB
Design
Read Noise
ne−T
−
12
−
e−rms
Design
4
Dynamic Range
DR
−
64
−
dB
Design
4, 5
Output Amplifier DC Offset
Vodc
−
9.4
−
V
Die
Output Amplifier Bandwidth
f−3db
−
250
−
MHz
Die
Output Amplifier Impedance
ROUT
−
127
−
W
Die
−
mV/e−
Design
Photodiode Dark Current
Output Amplifier Sensitivity
DV/DN
−
34
27, 40
Die
40
e/p/s
Die
40
e−
Design
3
Design
27, 40
6
27, 40
1. Per color
2. Value is over the range of 10% to 90% of photodiode saturation.
3. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such
that the photodiode charge capacity is 680 mV.
4. At 40 MHz
5. Uses 20LOG (PNe/ ne−T)
6. Assumes 5 pF load.
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KAI−01050
Table 8. KAI−01050−ABA CONFIGURATIONS
Symbol
Min.
Nom.
Max.
Units
Sampling
Plan
Peak Quantum Efficiency
QEmax
−
44
−
%
Design
Peak Quantum Efficiency
Wavelength
lQE
−
480
−
nm
Design
Description
Temperature
Tested At
(5C)
Notes
Temperature
Tested At
(5C)
Notes
Temperature
Tested At
(5C)
Notes
Table 9. KAI−01050−FBA GEN2 COLOR CONFIGURATIONS WITH MAR GLASS
Description
Symbol
Min.
Nom.
Max.
Units
Sampling
Plan
Peak Quantum Efficiency
Blue
Green
Red
QEmax
−
38
37
31
−
%
Design
Peak Quantum Efficiency
Wavelength
Blue
Green
Red
lQE
−
460
530
605
−
nm
Design
Table 10. KAI−01050−CBA GEN1 COLOR CONFIGURATIONS WITH MAR GLASS
Description
Symbol
Min.
Nom.
Max.
Units
Sampling
Plan
Peak Quantum Efficiency
Blue
Green
Red
QEmax
−
39
37
29
−
%
Design
1
Peak Quantum Efficiency
Wavelength
Blue
Green
Red
lQE
−
470
540
620
−
nm
Design
1
1. This color filter set configuration (Gen1) is not recommended for new designs.
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KAI−01050
TYPICAL PERFORMANCE CURVES
Quantum Efficiency
Monochrome with Microlens
NOTE: The PGA and CLCC versions have different quantum efficiencies due to differences in the cover glass transmission.
See Figure 29: Cover Glass Transmission for more details.
Figure 5. Monochrome with Microlens Quantum Efficiency
Color (Bayer RGB) with Microlens (Gen2 and Gen1 CFA)
Figure 6. Gen2 and Gen1 Color (Bayer) with Microlens Quantum Efficiency
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KAI−01050
Angular Quantum Efficiency
For the curves marked “Horizontal”, the incident light angle is varied in a plane parallel to the HCCD.
For the curves marked “Vertical”, the incident light angle is varied in a plane parallel to the VCCD.
Monochrome with Microlens
100
Relative Quantum Efficiency (%)
90
Vertical
80
70
60
50
Horizontal
40
30
20
10
0
−30
−20
−10
0
10
20
30
Angle (degrees)
Figure 7. Monochrome with Microlens Angular Quantum Efficiency
Dark Current vs. Temperature
10000
Dark Current (e/s)
1000
VCCD
100
10
Photodiode
1
0.1
1000/T (K)
2.9
3.0
3.1
3.2
3.3
3.4
T (°C)
72
60
50
40
30
21
Figure 8. Dark Current vs. Temperature
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11
KAI−01050
Power-Estimated
0.70
Power Dissipation (W)
0.60
0.50
Quad
0.40
Dual
Single
0.30
0.20
0.10
0.00
10
15
20
25
30
35
40
HCCD Frequency (MHz)
Figure 9. Power
Frame Rates
140
120
Frame Rate (fps)
100
Single
80
Dual
60
Quad
40
20
0
10
15
20
25
30
HCCD Frequency (MHz)
Figure 10. Frame Rates
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12
35
40
KAI−01050
DEFECT DEFINITIONS
Table 11. OPERATION CONDITIONS
Description
Condition
Notes
Frame Time
71.6 ms
Electronic shutter is not used.
Integration time equals frame time.
Horizontal Clock Frequency
20 MHz
Light Source
Continuous Red, Green and Blue LED Illumination centered at
450, 530 and 650 nm respectively
Operation
For monochrome sensor, only green
LED is used.
Nominal operating voltages and timing
Table 12. SPECIFICATIONS
Description
Definition
Standard Grade
Notes
Major Dark Field Defective Bright Pixel
Defect ≥ 25 mV
10
2
Major Bright Field Defective Dark Pixel
Defect ≥ 11%
10
2
Minor Dark Field Defective Bright Pixel
Cluster Defect
Column Defect
Defect ≥ 12 mV
100
3
A group of 2 contiguous major defective pixels.
0
1, 2
A group of 3 to 10 contiguous major defective pixels.
0
A group of more than 10 contiguous major defective pixels
along a single column.
0
1, 2
1. Column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects)
2. Tested at 27°C and 40°C.
3. Tested at 40°C.
Defect Map
The defect map supplied with each sensor is based upon
testing at an ambient (27°C) temperature. Minor point
defects are not included in the defect map. All defective
pixels are reference to pixel 1, 1 in the defect maps. See
Figure 11: Regions of Interest for the location of pixel 1, 1.
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13
KAI−01050
TEST DEFINITIONS
Test Regions of Interest
Overclocking
Image Area ROI:
Active Area ROI:
Center ROI:
The test system timing is configured such that the sensor
is overclocked in both the vertical and horizontal directions.
See Figure 11 for a pictorial representation of the regions.
Pixel (1, 1) to Pixel (1040, 1040)
Pixel (9, 9) to Pixel (1032, 1032)
Pixel (471, 471) to Pixel (570, 570)
Only the Active Area ROI pixels are used for performance
and defect tests.
Vertical Overclock
12 dark rows
8 buffer rows
9, 9
Horizontal Overclock
22 dark columns
8 buffer columns
8 buffer columns
22 dark columns
Pixel
1024 x 1024
Active Pixels
Pixel
1, 1
8 buffer rows
12 dark rows
VOUTa
Figure 11. Regions of Interest
Tests
as the maximum signal found minus the minimum signal
level found.
Dark Field Global Non-Uniformity
This test is performed under dark field conditions.
The sensor is partitioned into 64 sub regions of interest, each
of which is 128 by 128 pixels in size. See Figure 12: Test Sub
Regions of Interest. The average signal level of each of the
64 sub regions of interest is calculated. The signal level of
each of the sub regions of interest is calculated using the
following formula:
Global Non-Uniformity
This test is performed with the imager illuminated to a level
such that the output is at 70% of saturation (approximately
476 mV). Prior to this test being performed the substrate
voltage has been set such that the charge capacity of the
sensor is 680 mV. Global non-uniformity is defined as
Signal of ROI[i] + (ROI Average in Counts *
* Horizontal Overclock Average in Counts) @
Global Non−Uniformity + 100 @
@ mV per Count
ǒ
Active Area Standard Deviation
Active Area Signal
Ǔ
Units : % rms
Active Area Signal = Active Area Average − Dark Column Average
Units : mVpp (millivolts Peak to Peak)
Global Peak to Peak Non-Uniformity
This test is performed with the imager illuminated to
a level such that the output is at 70% of saturation
Where i = 1 to 64. During this calculation on the 64 sub
regions of interest, the maximum and minimum signal levels
are found. The dark field global uniformity is then calculated
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14
KAI−01050
region of interest, a pixel is marked defective if it is greater
than or equal to the median value of that region of interest
plus the defect threshold specified in the “Defect
Definitions” section.
(approximately 476 mV). Prior to this test being performed
the substrate voltage has been set such that the charge
capacity of the sensor is 680 mV. The sensor is partitioned
into 64 sub regions of interest, each of which is 128 by 128
pixels in size. See Figure 12: Test Sub Regions of Interest.
The average signal level of each of the 64 sub regions of
interest (ROI) is calculated. The signal level of each of the
sub regions of interest is calculated using the following
formula:
Bright Field Defect Test
This test is performed with the imager illuminated to
a level such that the output is at approximately 476 mV.
Prior to this test being performed the substrate voltage has
been set such that the charge capacity of the sensor is
680 mV. The average signal level of all active pixels is
found. The bright and dark thresholds are set as:
Signal of ROI[i] + (ROI Average in Counts *
* Horizontal Overclock Average in Counts) @
@ mV per Count
Dark Defect Threshold = Active Area Signal @ Threshold
Where i = 1 to 64. During this calculation on the 64 sub
regions of interest, the maximum and minimum signal levels
are found. The global peak to peak uniformity is then
calculated as:
Global Uniformity + 100 @
ǒ
Bright Defect Threshold = Active Area Signal @ Threshold
The sensor is then partitioned into 64 sub regions of
interest, each of which is 128 by 128 pixels in size. In each
region of interest, the average value of all pixels is found.
For each region of interest, a pixel is marked defective if it
is greater than or equal to the median value of that region of
interest plus the bright threshold specified or if it is less than
or equal to the median value of that region of interest minus
the dark threshold specified.
Example for major bright field defective pixels:
• Average value of all active pixels is found to be 476 mV.
• Dark defect threshold: 476 mV ⋅ 11 % = 52 mV.
• Bright defect threshold: 476 mV ⋅ 11 % = 52 mV.
• Region of interest #1 selected. This region of interest is
pixels 9, 9 to pixels 136, 136.
♦ Median of this region of interest is found to be
470 mV.
♦ Any pixel in this region of interest that is
≥ (470 + 52 mV) 522 mV in intensity will be marked
defective.
♦ Any pixel in this region of interest that is
≤ (470 − 52 mV) 418 mV in intensity will be marked
defective.
• All remaining 64 sub regions of interest are analyzed
for defective pixels in the same manner.
Ǔ
Max. Signal * Min. Signal
Active Area Signal
Units : % pp
Center Non-Uniformity
This test is performed with the imager illuminated to
a level such that the output is at 70% of saturation
(approximately 476 mV). Prior to this test being performed
the substrate voltage has been set such that the charge
capacity of the sensor is 680 mV. Defects are excluded for
the calculation of this test. This test is performed on the
center 100 by 100 pixels of the sensor. Center uniformity is
defined as:
Center ROI Uniformity + 100 @
ǒ
Center ROI Standard Deviation
Center ROI Signal
Ǔ
Units : % rms
Center ROI Signal = Center ROI Average − Dark Colum Average
Dark Field Defect Test
This test is performed under dark field conditions.
The sensor is partitioned into 64 sub regions of interest, each
of which is 128 by 128 pixels in size. In each region of
interest, the median value of all pixels is found. For each
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15
KAI−01050
Test Sub Regions of Interest
Pixel
(1032,1032)
57
58
59
60
61
62
63
64
49
50
51
52
53
54
55
56
41
42
43
44
45
46
47
48
33
34
35
36
37
38
39
40
25
26
27
28
29
30
31
32
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
Pixel
(9,9)
VOUTa
Figure 12. Test Sub Regions of Interest
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16
KAI−01050
OPERATION
Absolute Maximum Ratings
description. If the level or the condition is exceeded,
the device will be degraded and may be damaged. Operation
at these values will reduce MTTF.
Absolute maximum rating is defined as a level or
condition that should not be exceeded at any time per the
Table 13. ABSOLUTE MAXIMUM RATINGS
Description
Symbol
Minimum
Maximum
Unit
Notes
Operating Temperature
TOP
−50
70
°C
1
Humidity
RH
−5
90
%
2
Output Bias Current
IOUT
−
60
mA
3
CL
−
10
pF
Off-Chip Load
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Noise performance will degrade at higher temperatures.
2. T = 25°C. Excessive humidity will degrade MTTF.
3. Total for all outputs. Maximum current is −15 mA for each output. Avoid shorting output pins to ground or any low impedance source during
operation. Amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivity).
Table 14. ABSOLUTE MAXIMUM VOLTAGE RATINGS BETWEEN PINS AND GROUND
Description
Minimum
Maximum
Unit
Notes
VDDa, VOUTa
−0.4
17.5
V
1
RDa
−0.4
15.5
V
1
V1B, V1T
ESD − 0.4
ESD + 24.0
V
V2B, V2T, V3B, V3T, V4B, V4T
ESD − 0.4
ESD + 14.0
V
H1Sa, H1Ba, H2Sa, H2Ba, H2SLa, Ra, OGa
ESD − 0.4
ESD + 14.0
V
ESD
−10.0
0.0
V
SUB
−0.4
40.0
V
1. a denotes a, b, c or d.
2. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions
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17
1
2
KAI−01050
Power-Up and Power-Down Sequence
Adherence to the power-up and power-down sequence is critical. Failure to follow the proper power-up and power-down
sequences may cause damage to the sensor.
Do Not Pulse the Electronic Shutter until ESD is Stable
V+
VDD
SUB
Time
ESD
V−
VCCD
Low
HCCD
Low
Activate All Other Biases when ESD is Stable and Sub is above 3 V
Notes:
1. Activate all other biases when ESD is stable and SUB is above 3 V.
2. Do not pulse the electronic shutter until ESD is stable.
3. VDD cannot be +15 V when SUB is 0 V.
4. The image sensor can be protected from an accidental improper ESD voltage by current limiting the SUB current to less than 10 mA. SUB
and VDD must always be greater than GND. ESD must always be less than GND. Placing diodes between SUB, VDD, ESD and ground
will protect the sensor from accidental overshoots of SUB, VDD and ESD during power on and power off. See the figure below.
Figure 13. Power-Up and Power-Down Sequence
The VCCD clock waveform must not have a negative overshoot more than 0.4 V below the ESD voltage.
0.0 V
ESD
ESD − 0.4 V
All VCCD Clock Absolute
Maximum Overshoot of 0.4 V
Figure 14. VCCD Clock Waveform
Example of external diode protection for SUB, VDD and ESD.a denotes a, b, c or d.
VDDa
SUB
GND
ESD
Figure 15. Example of External Diode Protection
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18
KAI−01050
DC Bias Operating Conditions
Table 15. DC BIAS OPERATING CONDITIONS
Pins
Symbol
Min.
Nom.
Max.
Unit
Max. DC
Current
Notes
Reset Drain
RDa
RD
11.8
12.0
12.2
V
10 mA
1
Output Gate
OGa
OG
−2.2
−2.0
−1.8
V
10 mA
1
Output Amplifier Supply
VDDa
VDD
14.5
15.0
15.5
V
11.0 mA
1, 2
Ground
GND
GND
0.0
0.0
0.0
V
−1.0 mA
Substrate
SUB
VSUB
5.0
VAB
VDD
V
50 mA
3, 8
ESD Protection Disable
ESD
ESD
−9.5
−9.0
Vx_L
V
50 mA
6, 7, 9
VOUTa
IOUT
−3.0
−7.0
−10.0
mA
−
1, 4, 5
Description
Output Bias Current
VDDa
RDa
Ra
1. a denotes a, b, c or d.
2. The maximum DC current is for one output. IDD = IOUT + ISS. See Figure 16.
3. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such
that the photodiode charge capacity is the nominal PNe (see Specifications).
4. An output load sink must be applied to each VOUT pin to activate each output amplifier.
5. Nominal value required for 40 MHz operation per output. May be reduced for slower data rates and lower noise.
6. Adherence to the power-up and power-down sequence is critical. See Power Up and Power Down Sequence section.
7. ESD maximum value must be less than or equal to V1_L + 0.4 V and V2_L + 0.4 V.
8. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
9. Where Vx_L is the level set for V1_L, V2_L, V3_L, or V4_L in the application.
IDD
HCCD
Floating
Diffusion
IOUT
OGa
VOUTa
ISS
Source
Follower
#1
Figure 16. Output Amplifier
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19
Source
Follower
#2
Source
Follower
#3
KAI−01050
AC Operating Conditions
Table 16. CLOCK LEVELS
Description
Pins
(Note 1)
Symbol
Level
Min.
Nom.
Max.
Unit
Vertical CCD Clock, Phase 1
V1B, V1T
V1_L
Low
−8.2
−8.0
−7.8
V
V1_M
Mid
−0.2
0.0
0.2
6 nF
(Note 6)
V1_H
High
11.5
12.0
12.5
V2_L
Low
−8.2
−8.0
−7.8
V
V2_H
High
−0.2
0.0
0.2
6 nF
(Note 6)
V3_L
Low
−8.2
−8.0
−7.8
V
V3_H
High
−0.2
0.0
0.2
6 nF
(Note 6)
V4_L
Low
−8.2
−8.0
−7.8
V
V4_H
High
−0.2
0.0
0.2
6 nF
(Note 6)
H1S_L
Low
−5.2
(Note 7)
−4.0
−3.8
V
90 pF
(Note 6)
H1S_A
Amplitude
3.8
4.0
5.2
(Note 7)
H1B_L
Low
−5.2
(Note 7)
−4.0
−3.8
V
60 pF
(Note 6)
H1B_A
Amplitude
3.8
4.0
5.2
(Note 7)
H2S_L
Low
−5.2
(Note 7)
−4.0
−3.8
V
90 pF
(Note 6)
H2S_A
Amplitude
3.8
4.0
5.2
(Note 7)
H2B_L
Low
−5.2
(Note 7)
−4.0
−3.8
V
60 pF
(Note 6)
H2B_A
Amplitude
3.8
4.0
5.2
(Note 7)
H2SL_L
Low
−5.2
−5.0
−4.8
V
H2SL_A
Amplitude
4.8
5.0
5.2
20 pF
(Note 6)
R_L
(Note 4)
Low
−3.5
−2.0
−1.5
V
16 pF
(Note 6)
R_H
High
2.5
3.0
4.0
VES
High
29.0
30.0
40.0
V
800 pF
(Note 6)
Vertical CCD Clock, Phase 2
Vertical CCD Clock, Phase 3
Vertical CCD Clock, Phase 4
Horizontal CCD Clock,
Phase 1 Storage
Horizontal CCD Clock,
Phase 1 Barrier
Horizontal CCD Clock,
Phase 2 Storage
Horizontal CCD Clock,
Phase 2 Barrier
Horizontal CCD Clock,
Phase 2 Last Phase (Note 3)
Reset Gate
Electronic Shutter (Note 5)
1.
2.
3.
4.
5.
6.
7.
V2B, V2T
V3B, V3T
V4B, V4T
H1Sa
H1Ba
H2Sa
H2Ba
H2SLa
Ra
SUB
Capacitance
(Note 2)
a denotes a, b, c or d.
Capacitance is total for all like named pins.
Use separate clock driver for improved speed performance.
Reset low should be set to –3 V for signal levels greater than 40,000 electrons.
Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
Capacitance values are estimated.
If the minimum horizontal clock low level is used (–5.2 V), then the maximum horizontal clock amplitude should be used (5.2 V amplitude)
to create a –5.2 V to 0.0 V clock. If a 5 V clock driver is used, the horizontal low level should be set to –5.0 V and the high level should be
a set to 0.0 V.
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20
KAI−01050
The figure below shows the DC bias (VSUB) and AC clock (VES) applied to the SUB pin. Both the DC bias and AC clock
are referenced to ground.
VES
VSUB
GND
GND
Figure 17. DC Bias and AC Clock Applied to the SUB Pin
Device Identification
The device identification pin (DevID) may be used to determine which Truesense Imaging 5.5 micron pixel interline CCD
sensor is being used.
Table 17.
Description
Device Identification
Pins
Symbol
DevID
DevID
Min.
Nom.
Max.
∞
Unit
Max. DC
Current
Notes
W
n/a
1, 2
1. For the KAI−01050, the DevID pin is not connected internally to the device. Thus the resistance on the pin is infinity.
2. If the Device Identification is not used, it may be left disconnected.
Recommended Circuit
Note that V1 must be a different value than V2.
V1
V2
R_external
DevID
ADC
GND
KAI−01050
Figure 18. Device Identification Recommended Circuit
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21
KAI−01050
TIMING
Table 18. REQUIREMENTS AND CHARACTERISTICS
Description
Symbol
Min.
Nom.
Max.
Unit
Photodiode Transfer
tPD
1.0
−
−
ms
VCCD Leading Pedestal
t3P
4.0
−
−
ms
VCCD Trailing Pedestal
t3D
4.0
−
−
ms
VCCD Transfer Delay
tD
1.0
−
−
ms
VCCD Transfer
tV
1.0
−
−
ms
VVCR
75
−
100
%
tVR, tVF
5
−
10
%
tHS
0.2
−
−
ms
HCCD Transfer
te
25.0
−
−
ns
Shutter Transfer
tSUB
1.0
−
−
ms
Shutter Delay
tHD
1.0
−
−
ms
Reset Pulse
tR
2.5
−
−
ns
Reset − Video Delay
tRV
−
2.2
−
ns
H2SL − Video Delay
tHV
−
3.1
−
ns
tLINE
15.53
−
−
ms
29.35
−
−
8.26
−
−
16.52
−
−
Dual HCCD Readout
31.23
−
−
Single HCCD Readout
VCCD Clock Cross-Over
VCCD Rise, Fall Times
HCCD Delay
Line Time
Frame Time
tFRAME
22
2, 3
Dual HCCD Readout
Single HCCD Readout
ms
1. Refer to timing diagrams as shown in Figure 19, Figure 20, Figure 21, Figure 22 and Figure 23.
2. Refer to Figure 23: VCCD Clock Edge Alignment.
3. Relative to the pulse width.
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Notes
Quad HCCD Readout
KAI−01050
Timing Diagrams
The timing sequence for the clocked device pins may be
represented as one of seven patterns (P1−P7) as shown in the
table below. The patterns are defined in Figure 19 and
Figure 20. Contact ON Semiconductor Application
Engineering for other readout modes.
Table 19. TIMING DIAGRAMS
Device Pin
Quad Readout
Dual Readout
VOUTa, VOUTb
Dual Readout
VOUTa, VOUTc
Single Readout
VOUTa
V1T
P1T
P1B
P1T
P1B
V2T
P2T
P4B
P2T
P4B
V3T
P3T
P3B
P3T
P3B
V4T
P4T
P2B
P4T
P2B
V1B
P1B
V2B
P2B
V3B
P3B
V4B
P4B
H1Sa
P5
H1Ba
P5
H2Sa (Note 2)
P6
H2Ba
P6
Ra
P7
H1Sb
P5
P5
H1Bb
P5
P6
H2Sb (Note 2)
P6
P6
H2Bb
P6
P5
Rb
P7
P7 (Note 1) or Off (Note 3)
P7 (Note 1) or Off (Note 3)
H1Sc
P5
P5 (Note 1) or Off (Note 3)
P5
P5 (Note 1) or Off (Note 3)
H1Bc
P5
P5 (Note 1) or Off (Note 3)
P5
P5 (Note 1) or Off (Note 3)
H2Sc (Note 2)
P6
P6 (Note 1) or Off (Note 3)
P6
P6 (Note 1) or Off (Note 3)
H2Bc
P6
P6 (Note 1) or Off (Note 3)
P6
P6 (Note 1) or Off (Note 3)
Rc
P7
P7 (Note 1) or Off (Note 3)
P7
P7 (Note 1) or Off (Note 3)
H1Sd
P5
P5 (Note 1) or Off (Note 3)
P5
P5 (Note 1) or Off (Note 3)
H1Bd
P5
P5 (Note 1) or Off (Note 3)
P6
P5 (Note 1) or Off (Note 3)
H2Sd (Note 2)
P6
P6 (Note 1) or Off (Note 3)
P6
P6 (Note 1) or Off (Note 3)
H2Bd
P6
P6 (Note 1) or Off (Note 3)
P5
P6 (Note 1) or Off (Note 3)
Rd
P7
P7 (Note 1) or Off (Note 3)
P7 (Note 1) or Off (Note 3)
P7 (Note 1) or Off (Note 3)
#Lines/Frame
(Minimum)
532
1064
532
1064
#Pixels/Line
(Minimum)
553
1106
1. For optimal performance of the sensor. May be clocked at a lower frequency. If clocked at a lower frequency, the frequency selected should
be a multiple of the frequency used on the a and b register.
2. H2SLx follows the same pattern as H2Sx For optimal speed performance, use a separate clock driver.
3. Off = +5 V. Note that there may be operating conditions (high temperature and/or very bright light sources) that will cause blooming from the
unused c/d register into the image area.
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23
KAI−01050
Photodiode Transfer Timing
A row of charge is transferred to the HCCD on the falling
edge of V1 as indicated in the P1 pattern below. Using this
timing sequence, the leading dummy row or line is
combined with the first dark row in the HCCD. The “Last
Line” is dependent on readout mode – either 532 or 1064
minimum counts required. It is important to note that, in
Pattern
1
td
2
t 3p
3
4
t pd
t 3d
5
6
general, the rising edge of a vertical clock (patterns P1−P4)
should be coincident or slightly leading a falling edge at the
same time interval. This is particularly true at the point
where P1 returns from the high (3rd level) state to the
mid-state when P4 transitions from the low state to the high
state.
td
tv
tv
P1T
t v /2
t v /2
P2T
t v /2
t v /2
P3T
P4T
tv
tv
P1B
t v /2
t v /2
P2B
P3B
P4B
t hs
P5
Last Line
t hs
L1 + Dummy Line
L2
P6
P7
Figure 19. Photodiode Transfer Timing
P6 pattern). The number of pixels in a row is dependent on
readout mode – either 553 or 1106 minimum counts
required.
Line and Pixel Timing
Each row of charge is transferred to the output, as
illustrated below, on the falling edge of H2SL (indicated as
Pattern
tline
tv
P1T
tv
P1B
ths
t e/2
P5
te
P6
tr
P7
VOUT
Pixel
1
Pixel
34
Pixel
n
Figure 20. Line and Pixel Timing
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24
KAI−01050
Pixel Timing Detail
P5
P6
P7
VOUT
trv
thv
Figure 21. Pixel Timing Detail
Frame/Electronic Shutter Timing
The SUB pin may be optionally clocked to provide
electronic shuttering capability as shown below. The
resulting photodiode integration time is defined from the
falling edge of SUB to the falling edge of V1 (P1 pattern).
Pattern
t frame
P1T/B
SUB
P6
t hd
t int
t sub
t hd
Figure 22. Frame/Electronic Shutter Timing
VCCD Clock Edge Alignment
VVCR
tV
90%
10%
tVR
tVF
tV
tVF
tVR
Figure 23. VCCD Clock Edge Alignment
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25
KAI−01050
Line and Pixel Timing − Vertical Binning by 2
tv
tv
tv
ths
P1T
P2T
P3T
P4T
P1B
P2B
P3B
P4B
ths
P5
P6
P7
VOUT
Pixel
1
Pixel
n
Pixel
34
Figure 24. Line and Pixel Timing − Vertical Binning by 2
www.onsemi.com
26
KAI−01050
STORAGE AND HANDLING
Table 20. STORAGE CONDITIONS
Description
Symbol
Minimum
Maximum
Units
Notes
Storage Temperature
TST
−55
80
°C
1
Humidity
RH
5
90
%
2
1. Long-term storage toward the maximum temperature will accelerate color filter degradation.
2. T = 25°C. Excessive humidity will degrade MTTF.
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on environmental exposure, please
download the Using Interline CCD Image Sensors in High
Intensity Lighting Conditions Application Note
(AND9183/D) from www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference
Manual
(SOLDERRM/D)
from
www.onsemi.com.
www.onsemi.com
27
KAI−01050
MECHANICAL INFORMATION
PGA Completed Assembly
Notes:
1. See Ordering Information for marking code.
2. No materials to interfere with clearance through guide holes.
3. The center of the active image is nominally at the center of the package.
4. Die rotation < 0.5 degrees.
5. Glass rotation < 1.5 degrees
6. Internal traces may be exposed on sides of package. Do not allow metal to contact sides of ceramic package.
7. Recommended mounting screws:
a.) 1.6 × 0.35 mm (ISO Standard)
b.) 0–80 (Unified Fine Thread Standard).
8. Units: IN [MM]
Figure 25. PGA Completed Assembly
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28
KAI−01050
CLCC Completed Assembly
Notes:
1. See Ordering Information for marking code.
2. Die rotation < 0.5 degrees.
3. Units: millimeters.
Figure 26. CLCC Completed Assembly
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29
KAI−01050
PGA Cover Glass
Notes:
1. Dust/Scratch Count – 12 micron maximum
2. Units: IN [MM]
3. Reflectance Specification
a. 420 nm to 435 nm < 2.0%
b. 435 nm to 630 nm < 0.8%
c. 630 nm to 680 nm < 2.0%
Figure 27. PGA Cover Glass
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30
KAI−01050
CLCC MAR Cover Glass
Notes:
1. Dust/Scratch Count – 12 micron maximum
2. Units: millimeter
3. Reflectance Specification
a. 420 nm to 435 nm < 2.0%
b. 435 nm to 630 nm < 0.8%
c. 630 nm to 680 nm < 2.0%
Figure 28. CLCC MAR Cover Glass
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31
KAI−01050
Cover Glass Transmission
100
90
Transmission (%)
80
70
60
50
40
30
20
10
0
200
300
400
500
600
700
800
900
Wavelength (nm)
PGA MAR
CLCC MAR
NOTE: PGA and CLCC MAR transmission data differ due to in-spec differences from glass vendor.
Figure 29. Cover Glass Transmission
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
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ON Semiconductor Website: www.onsemi.com
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For additional information, please contact your local
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KAI−01050/D