ENA1916 D

Ordering number : ENA1916
LC450029PKB
CMOS IC
1/4 and 1/3-Duty General-Purpose
LCD Display Driver
http://onsemi.com
Overview
The LC450029PKB is 1/4 duty and 1/3 duty general-purpose microcontroller-controlled LCD drivers that can be
used in applications such as frequency display in products with electronic tuning. In addition to being capable to
drive up to 208 segments directly. The internal oscillation circuit helps to reduce the number of external resistors and
capacitors required. The chip shape is slim for COG (Chip-On-Glass) implementation. The operating temperature
range is from -40°C to +105°C
Application
• Car or general consumer electronic LCD display equipment.
Features
• Selectable 1/4-duty or 1/3-duty drive by the serial control data
When 1/4-duty: Capable of driving up to 208 segments
When 1/3-duty: Capable of driving up to 159 segments
• 1/3-bias only
• Serial data input supports CCB* format communication with the system controller. (For 5V operation only)
• The power-saving mode is selectable by the serial control data, and supports low power consumption.
• Adjustable the frame frequency of the common and segment output waveforms by the serial control data
• Selectable the internal oscillator operating or external clock operating mode by the serial control data
• High generality, since display data is displayed directly without the intervention of a decoder circuit.
• The INH pad allows all LCD segments to be forced to the off state.
• With a built-in oscillator circuit (External resistors and capacitors are unnecessary.)
• The stability of the LCD bias voltage is high by a built-in LCD bias generator with voltage-follower buffers.
• Shipping form: Chip with Au bumps in tray.
• Allowable operating voltage (VDD, VDDI)
: +4.5V to +6.0V
• Allowable wide operating temperature ranges
: -40°C to +105°C
•
CCB is ON Semiconductor® ’s original format. All addresses are managed
by ON Semiconductor® for this format.
•
CCB is a registered trademark of Semiconductor Components Industries, LLC.
Semiconductor Components Industries, LLC, 2013
July, 2013
21611HKIM 20101217-S00007 No.A1916-1/25
LC450029PKB
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0V
Parameter
Maximum supply voltage
Symbol
Conditions
VDD max,
Ratings
VDD=VDDI
-0.3 to +6.5
VDDI max
Input voltage
Unit
V
VIN1
CE, CL, DI, INH
VIN2
OSCI
-0.3 to VDDI+0.3
Output voltage
VOUT
S1 to S53, COM1 to COM4
-0.3 to VDD+0.3
V
Output current
IOUT1
S1 to S53
300
μA
IOUT2
COM1 to COM4
3
mA
-0.3 to +6.5
V
Operating temperature
Topr
-40 to +105
°C
Storage temperature
Tstg
-55 to +125
°C
(Note) Power supply pads (VDD, VDDI) should connect all pads to the same power supply.
(See sample applications circuits)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating Ranges at Ta = -40 to +105°C, VSS = 0V
Parameter
Symbol
Ratings
Conditions
min
Supply voltage
VDD,
VDD=VDDI
Input low-level voltage
Unit
max
4.5
VDDI
Input high-level voltage
typ
6.0
VIH1
CE, CL, DI, INH
0.8VDD
6.0
VIH2
OSCI: External clock operating mode
0.8VDD
VDDI
VIL1
CE, CL, DI, INH
0
0.2VDDI
VIL2
OSCI: External clock operating mode
0
0.2VDDI
External clock operating frequency
fCK
OSCI: External clock operating mode [Figure 4]
10
300
600
External clock duty cycle
DCK
OSCI: External clock operating mode [Figure 4]
30
50
70
Data setup time
tds
Data hold time
tdh
CE wait time
tcp
CE setup time
tcs
CE hold time
CL, DI
V
V
V
kHz
%
[Figure 2][Figure 3]
160
ns
CL, DI
[Figure 2][Figure 3]
160
ns
CE, CL
[Figure 2][Figure 3]
160
ns
CE, CL
[Figure 2][Figure 3]
160
ns
tch
CE, CL
[Figure 2][Figure 3]
160
ns
High-level clock pulse width
tφH
CL
[Figure 2][Figure 3]
160
ns
Low-level clock pulse width
tφL
CL
[Figure 2][Figure 3]
160
ns
Rise time
tr
CE, CL, DI
[Figure 2][Figure 3]
160
Fall time
tf
CE, CL, DI
[Figure 2][Figure 3]
160
INH switching time
tc
INH, CE
[Figure 5][Figure 6]
10
ns
ns
μs
(Note) Power supply pads (VDD, VDDI) should connect all pads to the same power supply.
(See sample applications circuits)
No.A1916-2/25
LC450029PKB
Electrical Characteristics for the Allowable Operating Ranges
Parameter
Symbol
Pin
Ratings
Conditions
min
Hysteresis
Input high-level current
Input low-level current
Output high-level voltage
Unit
max
VH1
CE, CL, DI, INH
VH2
OSCI
IIH1
CE, CL, DI, INH
VI = 6.0V
5.0
IIH2
OSCI
VI = VDDI, External clock operating mode
5.0
IIL1
CE, CL, DI, INH
VI = 0V
-5.0
IIL2
OSCI
VI = 0V, External clock operating mode
-5.0
0.1VDDI
External clock operating mode
VOH1
S1 to S53
IO = -20μA
VOH2
COM1
IO = -100μA
VOL1
S1 to S53
IO = 20μA
VOL2
COM1
IO = 100μA
V
0.1VDDI
μA
V
VDD-0.9
0.9
V
0.9
to COM4
Output middle-level
VMID1
S1 to S53
IO = ±20μA
2/3VDD
voltage *1
IO = ±20μA
1/3VDD
-0.9
+0.9
VMID3
COM1
IO = ±100μA
2/3VDD
2/3VDD
-0.9
+0.9
VMID4
COM1
IO = ±100μA
1/3VDD
1/3VDD
-0.9
+0.9
fosc
Internal
Internal oscillator operating mode
oscillator circuit
IDD1
VDD, VDDI
< Power-saving mode >
VDD, VDDI
VDD=VDDI=6.0V
< Internal oscillator operating mode >
(Total value of
VDD and VDDI)
+0.9
1/3VDD
S1 to S53
to COM4
Current drain
2/3VDD
-0.9
VMID2
to COM4
Oscillator frequency
IDD2
210
VDD=VDDI=6.0V
Driver outputs are open.
IDD3
VDD, VDDI
μA
VDD-0.9
to COM4
Output low-level voltage
typ
300
390
40
100
200
400
V
kHz
μA
< External clock operating mode >
VDD=VDDI=6.0V
fCK=300kHz
170
340
Driver outputs are open.
*1: Excluding the amount of voltage drop of the LCD BIAS GENERATOR which generates VDD1 and VDD2.
(See Figure 1.)
VDD
Excluding the amount of voltage drop of the LCD BIAS GENERATOR
LCD BIAS
GENERATOR
To Common drivers and Segment drivers
VSS
VDD1 VDD2
[Figure 1]
No.A1916-3/25
LC450029PKB
(1) When CL is stopped at the low level
≈
VIH1
CE
CL
≈ ≈
tφH
tφL
tf
DI
tcp
≈ ≈
VIH1
VIL1
tds
≈ ≈ ≈
VIH1
50%
VIL1
tr
VIL1
tcs
tch
tdh
[Figure 2]
(2) When CL is stopped at the high level
≈
VIH1
CE
≈
VIL1
tφH
≈
tφL
tf
tr
tcp
tcs
≈ ≈
≈ ≈ ≈
VIH1
50%
VIL1
CL
VIH1
DI
VIL1
tds
tch
tdh
[Figure 3]
(3) OSCI pad clock timing in external clock operating mode
tCKH
OSCI
VIH2
50%
VIL2
tCKL
fCK=
1
tCKH+ tCKL
[kHz]
tCKH
×100[%]
DCK=
tCKH+ tCKL
[Figure 4]
No.A1916-4/25
LC450029PKB
COMMON
DRIVER
S1
S2
S3
S5
S4
S53
COM3
COM4
COM2
COM1
Block Diagram
SEGMENT DRIVER & LATCH
INH
CONTROL
REGISTER
CLOCK
GENERATOR
OSCI
VDD
SHIFT REGISTER
LCD BIAS
GENERATOR
CCB INTERFACE
+
+
-
VSS
VDDI
CE
CL
DI
VLOGIC
VDD2
VDD1
REGULATOR
No.A1916-5/25
LC450029PKB
Pad Functions
Handling
Symbol
Pad No.
Function
Active
I/O
when
unused
Common driver outputs.
COM1 to
COM4
2 to 5
The frame frequency is fo[Hz].
-
O
OPEN
-
O
OPEN
L
I
H
I
-
I
COM4 pad outputs the VSS level in 1/3-duty.
Segment outputs for displaying the display data transferred by serial data input.
S1 to S53
6 to 58
S51 pad outputs the VSS level in 1/4-duty.
S52 pad and S53 pad output the VSS level at the control data DN=“0”.
S53 pad outputs the VSS level at external clock operating mode.
Display off control input
• INH = low (VSS) ...Display forced off (VSS level Output)
S1 to S53 = low (VSS)
COM1 to COM4 = low (VSS)
The internal oscillator stops.
Stops inputting external clock.
Serial data transfer can be used.
INH
61
• INH = high (VDD)...Display on
Enables the internal oscillator circuit.
GND
(VSS)
(Internal oscillator operating mode)
Enables external clock input.
(External clock operating mode)
While display on, LCD outputs force off (VSS level output)
by the control data BU=“1”.
While display on, LCD outputs off (off waveforms output)
by the control data SC=“1”.
CE
62
DI
63
CL
64
VLOGIC
65
Serial data transfer inputs. Must be connected to the controller.
CE: Chip enable
DI: Transfer data
I
CL: Synchronization clock
Used to monitor pad for the power supply voltage of the logic circuit.
Power supply pad. A power voltage of 4.5 to 6.0V must be applied to these
GND
(VSS)
-
O
OPEN
-
-
-
-
I
VDDI
66 to 71
OSCI
72
VSS
73 to 90
Ground pad. Must be connected to ground.
-
-
-
VDD2
91
Used to monitor pad for the LCD drive bias voltage (1/3 VDD).
-
O
OPEN
VDD1
92
Used to monitor pad for the LCD drive bias voltage (2/3 VDD).
-
O
OPEN
VDD
93 to 105
-
-
-
-
OPEN
OPEN
pads.
This pad can also be used as the external clock input pad when the external
clock operating mode is selected by control data.
This pad must be connected to GND at internal oscillator operating mode.
DUMMY
1, 59,
60, 106
Power supply pad. A power voltage of 4.5 to 6.0V must be applied to these
pads.
Dummy pad. Must not be used.
GND
(VSS)
(Note)
• Power supply pads (VDD, VDDI) should connect all pads to the same power supply.
(See sample applications circuits)
• GND pad (VSS) should connect all pads to the GND.
• When logic input pads (INH, CE, DI, CL, OSCI) are not used, must be fixed to GND (VSS).
• Must not use monitor pads (VLOGIC, VDD1, VDD2) in an external circuit.
• Must not connect dummy pad (DUMMY) mutually. Moreover, never use it in an external circuit.
No.A1916-6/25
LC450029PKB
Serial Data Input
1. 1/4 duty
(1) When CL is stopped at the low level
CE
CL
DI
1
0
0
0
0
0
1
0
D1 D2
D47 D48 D49 D50 D51 D52 0
0
0
0
0
0 EXF 0
0
0 DT DN FC0 FC1 FC2 OC SC BU 0
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
0
0
Control data
18 bits
Display data
52 bits
CCB address
8 bits
1
0 D53 D54
D99 D100 D101 D102 D103 D104 0
0
0
0
0
0
0
0
0
0
0
DD
2 bits
0
0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
1
0
0
0
0
0
Display data
52 bits
1
0 D105 D106
D151 D152 0
Fixed data
18 bits
0
0
0
0
0
0
0
0
0
0
0
0
0
DD
2 bits
0
0
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
1
0
0
0
0
0
Display data
48 bits
1
0 D153 D154
Fixed data
22 bits
D199 D200 D201 D202 D203 D204 D205 D206 D207 D208 0
0
0
0
0
DD
2 bits
0
0
0
0
0
0
0
0
0
1
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
56 bits
Fixed data
14 bits
DD
2 bits
Note: DD is the direction data.
No.A1916-7/25
LC450029PKB
(2) When CL is stopped at the high level
CE
CL
DI
1
0
0
0
0
0
1
0
D1 D2
D47 D48 D49 D50 D51 D52 0
0
0
0
0
0 EXF 0
0
0 DT DN FC0 FC1 FC2 OC SC BU 0
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
0
0
Control data
18 bits
Display data
52 bits
CCB address
8 bits
1
0
D53 D54
D99 D100 D101 D102 D103 D104 0
0
0
0
0
0
0
0
0
0
0
DD
2 bits
0
0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
1
0
0
0
0
0
Display data
52 bits
1
0
D105 D106
D151 D152 0
Fixed data
18 bits
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DD
2 bits
0
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
1
0
0
0
0
0
Display data
48 bits
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
D153 D154
Fixed data
22 bits
D199 D200 D201 D202 D203 D204 D205 D206 D207 D208 0
Display data
56 bits
0
0
0
DD
2 bits
0
0
0
0
0
0
0
0
0
0
Fixed data
14 bits
1
1
DD
2 bits
Note: DD is the direction data.
• CCB address .......... “41H”
• D1 to D208 ............ Display data
• EXF ....................... Ratio of dividing frequency in external clock operating mode setting control data
• DT ......................... 1/4-duty drive or 1/3-duty drive switching control data
• DN ......................... The number of the maximum display segments setting control data
• FC0 to FC2 ............ Common/segment output waveform frame frequency control data
• OC ......................... Internal oscillator operating mode/external clock operating mode switching control data
• SC .......................... Segment on/off (off waveform output) control data
• BU ......................... Normal mode/power-saving mode control data
No.A1916-8/25
LC450029PKB
2. 1/3 duty
(1) When CL is stopped at the low level
CE
CL
DI
1
0
0
0
0
0
1
0
D1 D2
D47 D48 D49 D50 D51 D52 D53 D54 0
0
0
0 EXF 0
0
0 DT DN FC0 FC1 FC2 OC SC BU 0
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
0
0
Control data
16 bits
Display data
54 bits
CCB address
8 bits
1
0 D55 D56
D101 D102 D103 D104 D105 D106 D107 D108 0
0
0
0
0
0
0
0
0
0
DD
2 bits
0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
1
0
0
0
0
0
Display data
54 bits
1
0
D109 D110
D155 D156 D157 D158 D159 0
Fixed data
16 bits
0
0
0
0
0
0
0
0
0
0
0
0
DD
2 bits
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
51 bits
Fixed data
19 bits
DD
2 bits
Note: DD is the direction data.
No.A1916-9/25
LC450029PKB
(2) When CL is stopped at the high level
CE
CL
DI
1
0
0
0
0
0
1
0
D1 D2
D47 D48 D49 D50 D51 D52 D53 D54 0
0
0
0 EXF 0
0
0 DT DN FC0 FC1 FC2 OC SC BU 0
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
0
0
Control data
16 bits
Display data
54 bits
CCB address
8 bits
1
0
D55 D56
D101 D102 D103 D104 D105 D106 D107 D108 0
0
0
0
0
0
0
0
0
0
DD
2 bits
0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
1
0
0
0
0
0
Display data
54 bits
1
0
D109 D110
D155 D156 D157 D158 D159 0
Fixed data
16 bits
0
0
0
0
0
0
0
0
0
0
0
DD
2 bits
0
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
51 bits
Fixed data
19 bits
DD
2 bits
Note: DD is the direction data.
• CCB address .......... “41H”
• D1 to D208 ............ Display data
• EXF ....................... Ratio of dividing frequency in external clock operating mode setting control data
• DT ......................... 1/4-duty drive or 1/3-duty drive switching control data
• DN ......................... The number of the maximum display segments setting control data
• FC0 to FC2 ............ Common/segment output waveform frame frequency control data
• OC ......................... Internal oscillator operating mode/external clock operating mode switching control data
• SC .......................... Segment on/off (off waveform output) control data
• BU ......................... Normal mode/power-saving mode control data
No.A1916-10/25
LC450029PKB
Serial Data Transfer Example
1. 1/4 duty
• When 153 or more segments are used
All 320 bits (include CCB address) of serial data must be sent.
8 bits
1
0
0
0
0
72 bits
0
1
0
D1 D2
D47 D48 D49 D50 D51 D52 0
0
0
0
0
0 EXF 0
0
0 DT DN FC0 FC1 FC2 OC SC BU 0
0
D53 D54
D99 D100 D101 D102 D103 D104 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
D105 D106
D151 D152 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
D153 D154
D199 D200 D201 D202 D203 D204 D205 D206 D207 D208 0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
0
0
1
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
• When fewer than 153 segments are used
One of 80, 160 and 240 bits of serial data must be sent, depending on the number of segments to be used.
However, the serial data shown below (the D1 to D52 display data, the control data and DD=“00”) must always
be sent.
8 bits
1
0
0
0
0
72 bits
0
1
0
D1 D2
D47 D48 D49 D50 D51 D52 0
0
0
0
0
0 EXF 0
0
0 DT DN FC0 FC1 FC2 OC SC BU 0
0
B0 B1 B2 B3 A0 A1 A2 A3
2. 1/3 duty
• When 109 or more segments are used
All 240 bits (include CCB address) of serial data must be sent.
8 bits
1
0
0
0
0
72 bits
0
1
0
D1 D2
D47 D48 D49 D50 D51 D52 D53 D54 0
0
0
0 EXF 0
0
0 DT DN FC0 FC1 FC2 OC SC BU 0
0
D55 D56
D101 D102 D103 D104 D105 D106 D107 D108 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
D109 D110
D155 D156 D157 D158 D159 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
0
0
1
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
• When fewer than 109 segments are used
Either 80 or 160 bits of serial data must be sent, depending on the number of segments to be used.
However, the serial data shown below (the D1 to D54 display data, the control data and DD=“00”) must always
be sent.
8 bits
1
0
0
0
0
72 bits
0
1
0
D1 D2
D47 D48 D49 D50 D51 D52 D53 D54 0
0
0
0 EXF 0
0
0 DT DN FC0 FC1 FC2 OC SC BU 0
0
B0 B1 B2 B3 A0 A1 A2 A3
No.A1916-11/25
LC450029PKB
Control Data Functions
(1) EXF … Ratio of dividing frequency in external clock operating mode setting control data
This control data sets the ratio of dividing frequency of the external clock which input into the OSCI pad, when the
external clock operating mode (OC=“1”) is set. However, this data is effective only when external clock operating
mode (OC= “1”) is set. The frame frequency is adjustable by setting EXF, FC0 to FC2 and OC.
EXF
Ratio of dividing frequency in external clock operating mode
0
fCK / 8
1
fCK
(2) DT …1/4-duty drive or 1/3-duty drive switching control data
This control data bit selects either 1/4-duty drive or 1/3-duty drive.
DT
Drive scheme
S51 pad’s state
0
1/4-duty drive
Low (VSS) level output
1
1/3-duty drive
S51 (segment output)
(3) DN …The number of the maximum display segments setting control data
This control data bit sets the number of the maximum display segments.
The number of the maximum display segments
DN
Pad’s state
1/4 duty
1/3 duty
S52
S53
0
Up to 200 segments
Up to 153 segments
“L” (VSS)
“L” (VSS)
1
Up to 208 segments
Up to 159 segments
S52 (segment output)
S53 (segment output)
(Note) S53 pad outputs VSS level in external clock operating mode.
(4) FC0 to FC2 …Common/segment output waveform frame frequency control data
These control data bits set the frame frequency of the common and segment output waveforms. The frame frequency
is adjustable by setting EXF, FC0 to FC2 and OC.
Control data
Frame frequency fo[Hz]
Internal oscillator operating mode
FC0
FC1
FC2
External clock operating mode
(The control data OC=“0”,
fosc=300[kHz]typ)
0
0
0
fosc/6144 =48.8[Hz]typ
0
0
1
fosc/4608 =65.1[Hz]typ
0
1
0
fosc/3072 =97.7[Hz]typ
0
1
1
fosc/2304 =130.2[Hz]typ
1
0
0
fosc/1536 =195.3[Hz]typ
1
0
1
fosc/1152 =260.4[Hz]typ
1
1
0
fosc/768 =390.6[Hz]typ
1
1
1
fosc/3072 =97.7[Hz]typ
External clock operating mode
(The control data
(The control data
OC=“1”, EXF=“0”)
OC=“1”, EXF=“1”)
Case is fCK=300[kHz].
Case is fCK=38[kHz].
fCK/6144 =48.8[Hz]
fCK/4608 =65.1[Hz]
fCK/768 =49.5[Hz]
fCK/3072 =97.7[Hz]
fCK/2304 =130.2[Hz]
fCK/384 =99.0[Hz]
fCK/288 =131.9[Hz]
fCK/1536 =195.3[Hz]
fCK/1152 =260.4[Hz]
fCK/192 =197.9[Hz]
fCK/768 =390.6[Hz]
fCK/3072 =97.7[Hz]
fCK/96 =395.8[Hz]
fCK/576 =66.0[Hz]
fCK/144 =263.9[Hz]
fCK/384 =99.0[Hz]
(5) OC …Internal oscillator operating mode/external clock operating mode switching control data
This control data bit selects either the internal oscillator operating mode or external clock operating mode.
OC
Fundamental clock operating mode
S53 pad’s state
0
Internal oscillator operating mode
S53 (segment output)
1
External clock operating mode
Low (VSS) level output
(6) SC … Segment on/off (off waveform output) control data
This control data bit controls the on/off (off waveform output) state of all the segments.
SC
Display state
0
On
1
Off of all the segments (off waveform output)
(7) BU … Normal mode/power-saving mode control data
This control data bit selects either normal mode or power-saving mode.
BU
0
Mode
Normal mode
Power-saving mode
1
All of the common and segment output pads output the VSS level.
In this mode, the internal oscillator circuit stops oscillation if the IC is in the internal oscillator operating mode
(OC=0), and the IC stops receiving external clock signals if the IC is in the external clock operating mode (OC=1).
No.A1916-12/25
LC450029PKB
Display Data and Output Pad Correspondence (1/4 Duty)
Output pad
COM1
COM2
COM3
COM4
Output pad
COM1
COM2
COM3
COM4
S1
D1
D2
D3
D4
S28
D109
D110
D111
D112
S2
D5
D6
D7
D8
S29
D113
D114
D115
D116
S3
D9
D10
D11
D12
S30
D117
D118
D119
D120
S4
D13
D14
D15
D16
S31
D121
D122
D123
D124
S5
D17
D18
D19
D20
S32
D125
D126
D127
D128
S6
D21
D22
D23
D24
S33
D129
D130
D131
D132
S7
D25
D26
D27
D28
S34
D133
D134
D135
D136
S8
D29
D30
D31
D32
S35
D137
D138
D139
D140
S9
D33
D34
D35
D36
S36
D141
D142
D143
D144
S10
D37
D38
D39
D40
S37
D145
D146
D147
D148
S11
D41
D42
D43
D44
S38
D149
D150
D151
D152
S12
D45
D46
D47
D48
S39
D153
D154
D155
D156
S13
D49
D50
D51
D52
S40
D157
D158
D159
D160
S14
D53
D54
D55
D56
S41
D161
D162
D163
D164
S15
D57
D58
D59
D60
S42
D165
D166
D167
D168
S16
D61
D62
D63
D64
S43
D169
D170
D171
D172
S17
D65
D66
D67
D68
S44
D173
D174
D175
D176
S18
D69
D70
D71
D72
S45
D177
D178
D179
D180
S19
D73
D74
D75
D76
S46
D181
D182
D183
D184
S20
D77
D78
D79
D80
S47
D185
D186
D187
D188
S21
D81
D82
D83
D84
S48
D189
D190
D191
D192
S22
D85
D86
D87
D88
S49
D193
D194
D195
D196
S23
D89
D90
D91
D92
S50
D197
D198
D199
D200
S24
D93
D94
D95
D96
S51
-
-
-
-
S25
D97
D98
D99
D100
S52
D201
D202
D203
D204
S26
D101
D102
D103
D104
S53
D205
D206
D207
D208
S27
D105
D106
D107
D108
(Note) In external clock operating mode, S53 pad outputs VSS level. When DN is “0”, S52 pad and S53 pad output
VSS level. When duty is 1/4, S51 pad outputs VSS level.
For example, the table below lists the output states for the S21 output pad.
Display data
Output pad (S21) state
D81
D82
D83
D84
0
0
0
0
The LCD segments corresponding to COM1, COM2, COM3, and COM4 are off.
0
0
0
1
The LCD segment corresponding to COM4 is on.
0
0
1
0
The LCD segment corresponding to COM3 is on.
0
0
1
1
The LCD segments corresponding to COM3 and COM4 are on.
0
1
0
0
The LCD segment corresponding to COM2 is on.
0
1
0
1
The LCD segments corresponding to COM2 and COM4 are on.
0
1
1
0
The LCD segments corresponding to COM2 and COM3 are on.
0
1
1
1
The LCD segments corresponding to COM2, COM3, and COM4 are on.
1
0
0
0
The LCD segment corresponding to COM1 is on.
1
0
0
1
The LCD segments corresponding to COM1 and COM4 are on.
1
0
1
0
The LCD segments corresponding to COM1 and COM3 are on.
1
0
1
1
The LCD segments corresponding to COM1, COM3, and COM4 are on.
1
1
0
0
The LCD segments corresponding to COM1 and COM2 are on.
1
1
0
1
The LCD segments corresponding to COM1, COM2, and COM4 are on.
1
1
1
0
The LCD segments corresponding to COM1, COM2, and COM3 are on.
1
1
1
1
The LCD segments corresponding to COM1, COM2, COM3, and COM4 are on.
No.A1916-13/25
LC450029PKB
Display Data and Output Pad Correspondence (1/3 Duty)
Output pad
COM1
COM2
COM3
Output pad
COM1
COM2
COM3
S1
D1
D2
D3
S28
D82
D83
D84
S2
D4
D5
D6
S29
D85
D86
D87
S3
D7
D8
D9
S30
D88
D89
D90
S4
D10
D11
D12
S31
D91
D92
D93
S5
D13
D14
D15
S32
D94
D95
D96
S6
D16
D17
D18
S33
D97
D98
D99
S7
D19
D20
D21
S34
D100
D101
D102
S8
D22
D23
D24
S35
D103
D104
D105
S9
D25
D26
D27
S36
D106
D107
D108
S10
D28
D29
D30
S37
D109
D110
D111
S11
D31
D32
D33
S38
D112
D113
D114
S12
D34
D35
D36
S39
D115
D116
D117
S13
D37
D38
D39
S40
D118
D119
D120
S14
D40
D41
D42
S41
D121
D122
D123
S15
D43
D44
D45
S42
D124
D125
D126
S16
D46
D47
D48
S43
D127
D128
D129
S17
D49
D50
D51
S44
D130
D131
D132
S18
D52
D53
D54
S45
D133
D134
D135
S19
D55
D56
D57
S46
D136
D137
D138
S20
D58
D59
D60
S47
D139
D140
D141
S21
D61
D62
D63
S48
D142
D143
D144
S22
D64
D65
D66
S49
D145
D146
D147
S23
D67
D68
D69
S50
D148
D149
D150
S24
D70
D71
D72
S51
D151
D152
D153
S25
D73
D74
D75
S52
D154
D155
D156
S26
D76
D77
D78
S53
D157
D158
D159
S27
D79
D80
D81
(Note) In external clock operating mode, S53 pad outputs VSS level. When DN is “0”, S52 pad and S53 pad output
VSS level.
For example, the table below lists the output states for the S21 output pad.
Display data
Output pad (S21) state
D61
D62
D63
0
0
0
The LCD segments corresponding to COM1, COM2, and COM3 are off.
0
0
1
The LCD segment corresponding to COM3 is on.
0
1
0
The LCD segment corresponding to COM2 is on.
0
1
1
The LCD segments corresponding to COM2 and COM3 are on.
1
0
0
The LCD segment corresponding to COM1 is on.
1
0
1
The LCD segments corresponding to COM1 and COM3 are on.
1
1
0
The LCD segments corresponding to COM1 and COM2 are on.
1
1
1
The LCD segments corresponding to COM1, COM2, and COM3 are on.
No.A1916-14/25
LC450029PKB
Output Waveforms (1/4-Duty 1/3-Bias Drive Scheme)
Frame frequency fo[Hz]
COM1
COM2
COM3
COM4
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3, and
COM4 are off.
LCD driver output when only LCD segments
corresponding to COM1 are on.
LCD driver output when only LCD segments
corresponding to COM2 are on.
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
LCD driver output when only LCD segments
corresponding to COM3 are on.
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
LCD driver output when LCD segments
corresponding to COM1, COM2, and COM3
are on.
LCD driver output when only LCD segments
corresponding to COM4 are on.
LCD driver output when LCD segments
corresponding to COM2 and COM4 are on.
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3, and
COM4 are on.
VDD
VDD1
VDD2
VSS
VDD
VDD1
VDD2
VSS
VDD
VDD1
VDD2
VSS
VDD
VDD1
VDD2
VSS
VDD
VDD1
VDD2
VSS
VDD
VDD1
VDD2
VSS
VDD
VDD1
VDD2
VSS
VDD
VDD1
VDD2
VSS
VDD
VDD1
VDD2
VSS
VDD
VDD1
VDD2
VSS
VDD
VDD1
VDD2
VSS
VDD
VDD1
VDD2
VSS
VDD
VDD1
VDD2
VSS
VDD
VDD1
VDD2
VSS
VDD
VDD1
VDD2
VSS
(Note) The frame frequency fo[Hz] is adjustable by setting control data (EXF, FC0 to FC2 and OC).
(See “Control Data Functions” for details)
No.A1916-15/25
LC450029PKB
Output Waveforms (1/3-Duty 1/3-Bias Drive Scheme)
Frame frequency fo[Hz]
COM1
VDD
VDD1
VDD2
VSS
COM2
VDD
VDD1
VDD2
VSS
COM3
VDD
VDD1
VDD2
VSS
LCD driver output when all LCD segments
corresponding to COM1, COM2, and COM3
are off.
VDD
VDD1
VDD2
VSS
LCD driver output when only LCD segments
corresponding to COM1 are on.
VDD
VDD1
VDD2
VSS
LCD driver output when only LCD segments
corresponding to COM2 are on.
VDD
VDD1
VDD2
VSS
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
VDD
VDD1
VDD2
VSS
LCD driver output when only LCD segments
corresponding to COM3 are on.
VDD
VDD1
VDD2
VSS
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
VDD
VDD1
VDD2
VSS
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
VDD
VDD1
VDD2
VSS
LCD driver output when all LCD segments
corresponding to COM1, COM2, and COM3
are on.
VDD
VDD1
VDD2
VSS
(Note) The frame frequency fo[Hz] is adjustable by setting control data (EXF, FC0 to FC2 and OC).
(See “Control Data Functions” for details)
No.A1916-16/25
LC450029PKB
Display Control and the INH Pad
Since the LSI internal data (1/4 duty : the display data D1 to D208 and the control data, 1/3 duty : the display data D1 to
D159 and the control data) is undefined when power is first applied. Applications should set the INH pad low at the
same time as power is applied to turn off the display (This sets the S1 to S53 and COM1 to COM4 pads the VSS level.)
and during this period send serial data from the controller. The controller should then set the INH pad high after the data
transfer has completed. This procedure prevents meaningless display at power on. VDD and VDDI are connected with
the same power supply. The timing of turn on and turn off for VDD and VDDI should be same time.
(See from Figure 5 to Figure 8)
• 1/4 duty
t2
t1
VDD=VDDI
tc
INH
VIL1
VIL1
CE
S1 to S53
COM1 to COM4
Update display data
Initialization of display data
and control data
OFF (VSS level output)
ON
OFF (VSS level output)
(Note) The wait time (t1) which power supply turn on should be 1ms or more.
The discharge time (t2) of LCD panel’s electric charge should be decided the optimum value according to the
characteristic of the LCD panel.
The switching time (tc) of INH should be 10μs or more.
[Figure 5]
• 1/3 duty
t2
t1
VDD=VDDI
tc
INH
CE
S1 to S53
COM1 to COM4
VIL1
VIL1
Update display data
Initialization of display data
and control data
OFF (VSS level output)
ON
OFF (VSS level output)
(Note) The wait time (t1) which power supply turn on should be 1ms or more.
The discharge time (t2) of LCD panel’s electric charge should be decided the optimum value according to the
characteristic of the LCD panel.
The switching time (tc) of INH should be 10μs or more.
[Figure 6]
No.A1916-17/25
LC450029PKB
• In external clock operating mode
t2
t1
VDD=VDDI
OSCI
tc
VIL1
INH
VIL1
CE
S1 to S53
COM1 to COM4
Update display data
Initialization of display data
and control data (OC=1)
OFF (VSS level output)
OFF (VSS level output)
ON
(Note) The wait time (t1) which power supply turn on should be 1ms or more.
The discharge time (t2) of LCD panel’s electric charge should be decided the optimum value according to the
characteristic of the LCD panel.
The switching time (tc) of INH should be 10μs or more.
OSCI pad should be input an external clock at INH is high level.
[Figure 7]
• All segments off (off waveforms output)
VDD=VDDI
INH
CE
SC=1
SC=0
Initialization of display data
and control data (SC=0)
COM1
VSS
VSS
S1
VSS
VSS
OFF (VSS level output)
ON
OFF
(off waveforms output)
ON
OFF
(VSS level output)
[Figure 8]
• Power-saving mode
VDD=VDDI
INH
CE
BU=1
Initialization of display data
and control data (BU=0)
S1 to S53
COM1 to COM4
OFF
(VSS level output)
ON
BU=0
OFF
(VSS level output)
ON
OFF
(VSS level output)
Power-saving mode
[Figure 9]
No.A1916-18/25
LC450029PKB
Notes on Controller Transfer of Display Data
When using the LC450029PKB in 1/4 duty, applications transfer the display data (D1 to D208) in four operations, and
in 1/3 duty, they transfer the display data (D1 to D159) in three operations. In either case, applications should transfer
all of the display data within 30ms to maintain the quality of displayed image.
About peripheral circuit of the input pad
(1) Processing of unused OSCI pad
When OSCI pad is not to be used, select the internal oscillator operating mode (control data OC=“0”), and OSCI pad
is connected to GND.
OSCI
No.A1916-19/25
LC450029PKB
Sample Applications Circuit1
1/4 duty, Display data (D1 to D208), Internal oscillator operating mode
C
VDDI
*2
OSCI *4
VDD
C *2
(OPEN)
VDD1
(OPEN)
VDD2
VSS
(OPEN)
VLOGIC
S50
S51
S52
S53
INH
CE
CL
DI
Controller
COM1
COM2
COM3
COM4
S1
S2
S3
S4
S5
LCD panel
+5V
(OPEN) *3
Sample Applications Circuit2
1/4 duty, Display data (D1 to D204), External clock operating mode
C
VDDI
*2
VDD
C *2
(OPEN)
VDD1
(OPEN)
VDD2
VSS
(OPEN)
COM1
COM2
COM3
COM4
S1
S2
S3
S4
S5
VLOGIC
INH
Controller
OSCI
LCD panel
+5V
CE
CL
DI
S50
S51
S52
S53
(OPEN) *3
(OPEN) *5
*2 Connect capacitors between a power supply line and GND for noise removal and power supply stabilization.
Determine the value of a capacitor, after an actual circuit board estimates.
*3 In 1/4 duty, S51 pad outputs VSS level.
*4 When OSCI pad is not to be used, select the internal oscillator operating mode (control data OC=“0”),
and OSCI pad is connected to GND.
*5 In external clock operating mode, S53 pad outputs VSS level.
No.A1916-20/25
LC450029PKB
Sample Applications Circuit3
1/3 duty, Display data (D1 to D159), Internal oscillator operating mode
+5V
C
VDDI
*2
OSCI
COM1
COM2
COM3
VDD
C *2
COM4
(OPEN) *6
S1
(OPEN)
VDD1
S2
(OPEN)
VDD2
VSS
(OPEN)
S5
VLOGIC
INH
Controller
S4
LCD panel
S3
CE
CL
S50
S51
S52
S53
DI
*2 Connect capacitors between a power supply line and GND for noise removal and power supply stabilization.
Determine the value of a capacitor, after an actual circuit board estimates.
*6 In 1/3 duty, COM4 pad outputs VSS level.
No.A1916-21/25
LC450029PKB
The Notes on Use
Important things for stability operation of IC are shown as follows. The contents indicated below do not guarantee IC
operation and the characteristic. Moreover, the example of an application circuit written in these specifications is for
explaining internal operation and usage. Therefore, please perform the design in consideration of the specification of
operation and terms and conditions in the actual LCD panel.
(1) The design of power supply
All power supply pads are connected to the power supply, and do not set open.
(2) ITO (Indium Tin Oxide) wiring
By designing the wire of power supply (VDD, VDDI, VSS) wide and short, make the parasitic resistance of ITO
wiring into the minimum.
(3) Signal wiring and connection
The DUMMY pad does not connect to anywhere, and sets open.
(4) Processing of unused input pad
For CMOS process, if an input pad is in open state, operation of IC may become unstable, or unnecessary power
supply current may flow through it. Please be sure to connect the empty pad of a logic input to VSS.
(5) The measure against shading
The optical irradiation to IC causes the mis-operation of IC. When IC is implemented, take the measures against
shading about the surface, back and side of IC.
No.A1916-22/25
LC450029PKB
MODEL NAME
(0, 0)
Alignment Mark #3
(C-Type)
Y
Alignment Mark #2
(B-Type)
VDD
←
VDD
PAD No.105
PAD No.93 ←
VSS
PAD No.90 ←
VSS
PAD No.73 ←
PAD No.91 ← VDD2
PAD No.92 ← VDD1
VDDI
OSCI
PAD No.71 ←
PAD No.72 ←
CL
VLOGIC
PAD No.66 ← VDDI
DI
CE
INH
PAD No.60 ← DUMMY
X
PAD No.106 ← DUMMY
Alignment Mark #1
(A-Type)
DUMMY → PAD No.1
COM1
COM2
COM3
COM4
S1
S2
S3
S7
S6
S5
S4
→ PAD No.10
PAD No.58
→
S53
S52
S51
DUMMY → PAD No.59
• PAD Locations (Bump Side View)
• Chip dimensions (X, Y, S are based on the dicing center.)
X=1.00mm Y=4.08mm S=4.08mm2 Wafer thickness=400μm (typ)
• Au Bump dimensions (typ)
Size
Item
PAD No.
Bump Size
Min. Bump Pitch
X [μm]
Y [μm]
S [μm2]
1 to 59
108
27
2916
60 to 106
68
42
2856
10 to 58
50
-
1 to 9, 59 to 106
-
-
23
-
-
-
17
-
10 to 58, 66 to 71,
73 to 90, 93 to 105
Min. Bump Clearance
1 to 9, 59 to 65, 72,
91 to 92, 106
Bump Height
All pads
• Alignment marks
(1) A-Type
(3) C-Type
20
50
80
80
50
60
30
10
(2) B-Type
10
30
60
50
80
20
50
80
Unit: μm
No.A1916-23/25
LC450029PKB
• Center coordinates of PADs
(All x/y coordinates represent the position of the center of each PAD)
PAD
PAD
X
Y
PAD
PAD
X
Y
PAD
PAD
X
Y
No.
Name
[μm]
[μm]
No.
Name
[μm]
[μm]
No.
Name
[μm]
[μm]
1
DUMMY
-380
1950
41
S36
-380
-943
81
VSS
400
10
2
COM1
-380
1369
42
S37
-380
-993
82
VSS
400
75
3
COM2
-380
1276
43
S38
-380
-1043
83
VSS
400
140
4
COM3
-380
1183
44
S39
-380
-1093
84
VSS
400
205
5
COM4
-380
1090
45
S40
-380
-1143
85
VSS
400
270
6
S1
-380
932
46
S41
-380
-1193
86
VSS
400
335
7
S2
-380
856
47
S42
-380
-1243
87
VSS
400
400
8
S3
-380
780
48
S43
-380
-1293
88
VSS
400
465
9
S4
-380
704
49
S44
-380
-1343
89
VSS
400
530
10
S5
-380
607
50
S45
-380
-1393
90
VSS
400
595
11
S6
-380
557
51
S46
-380
-1443
91
VDD2
400
668
12
S7
-380
507
52
S47
-380
-1493
92
VDD1
400
739
13
S8
-380
457
53
S48
-380
-1543
93
VDD
400
811
14
S9
-380
407
54
S49
-380
-1593
94
VDD
400
876
15
S10
-380
357
55
S50
-380
-1643
95
VDD
400
941
16
S11
-380
307
56
S51
-380
-1693
96
VDD
400
1006
17
S12
-380
257
57
S52
-380
-1743
97
VDD
400
1071
18
S13
-380
207
58
S53
-380
-1793
98
VDD
400
1136
19
S14
-380
157
59
DUMMY
-380
-1950
99
VDD
400
1201
20
S15
-380
107
60
DUMMY
400
-1943
100
VDD
400
1266
21
S16
-380
57
61
INH
400
-1665
101
VDD
400
1331
22
S17
-380
7
62
CE
400
-1525
102
VDD
400
1396
23
S18
-380
-43
63
DI
400
-1385
103
VDD
400
1461
24
S19
-380
-93
64
CL
400
-1245
104
VDD
400
1526
25
S20
-380
-143
65
VLOGIC
400
-1161
105
VDD
400
1591
26
S21
-380
-193
66
VDDI
400
-1071
106
DUMMY
400
1943
27
S22
-380
-243
67
VDDI
400
-1006
28
S23
-380
-293
68
VDDI
400
-941
29
S24
-380
-343
69
VDDI
400
-876
30
S25
-380
-393
70
VDDI
400
-811
31
S26
-380
-443
71
VDDI
400
-746
32
S27
-380
-493
72
OSCI
400
-650
33
S28
-380
-543
73
VSS
400
-510
34
S29
-380
-593
74
VSS
400
-445
35
S30
-380
-643
75
VSS
400
-380
36
S31
-380
-693
76
VSS
400
-315
37
S32
-380
-743
77
VSS
400
-250
38
S33
-380
-793
78
VSS
400
-185
39
S34
-380
-843
79
VSS
400
-120
40
S35
-380
-893
80
VSS
400
-55
• Center coordinates of alignment marks
(All x/y coordinates represent the position of the center of each alignment mark)
Alignment mark
TYPE
X [μm]
Y [μm]
-1800
1
A
400
2
B
400
1790
3
C
-380
1800
No.A1916-24/25
LC450029PKB
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number
of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at
www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use
as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in
which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for
any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or
death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the
part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PS No.A1916-25/25