Ordering number : ENA1953 CMOS IC LC75839PW 1/4 and 1/3-Duty General-Purpose LCD Display Driver Overview The LC75839PW is 1/4 duty and 1/3 duty general-purpose microprocessor-controlled LCD driver that can be used in applications such as frequency display in products with electronic tuning. In addition to being able to drive up to 208 segments directly, the LC75839PW can also control up to 4 general-purpose output ports. Because it has the PWM output of a maximum of 3 ch, the brightness control of the LED backlight of RGB can be done. Incorporation of an oscillation circuit helps to reduce the number of external resistors and capacitors required. Features • Support for 1/4-duty 1/3-bias or 1/3-duty 1/3-bias drive techniques under serial data control. When 1/4-duty: Capable of driving up to 208 segments When 1/3-duty: Capable of driving up to 159 segments • Serial data input supports CCB format communication with the system controller. (Support 3.3V and 5V operation) • Serial data control of the power-saving mode based backup function and the all segments forced off function. • Serial data control of switching between the segment output port and general-purpose output port function. (Support for up to 4 general-purpose output ports) • Support for the PWM output function of a maximum of 3ch. (It can output from the general-purpose output port ). • Support for clock output function of 1ch. • Serial data control of the frame frequency of the common and segment output waveforms. • Serial data control of switching between the internal oscillator operating mode and external clock operating mode. • High generality, since display data is displayed directly without the intervention of a decoder circuit. • The INH pin allows the display to be forced to the off state. • Incorporation of an oscillator circuit. (Incorporation of resistor and capacitor for an oscillation) • • CCB is a registered trademark of SANYO Semiconductor Co., Ltd. CCB is SANYO Semiconductor's original bus format. All bus addresses are managed by SANYO Semiconductor for this format. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 62911HKPC 20110412-S00001 No.A1953-1/27 LC75839PW Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0V Parameter Symbol Maximum supply voltage Conditions VDD max Input voltage Ratings VDD Unit -0.3 to +6.5 V VIN1 CE, CL, DI, INH VIN2 OSCI, VDD1, VDD2 -0.3 to VDD+0.3 Output voltage VOUT S1 to S53, COM1 to COM4, P1 to P4 -0.3 to VDD+0.3 V Output current IOUT1 S1 to S52 300 μA IOUT2 COM1 to COM4, S53 3 IOUT3 P1 to P4 5 Pd max Ta=85°C Allowable power dissipation -0.3 to +6.5 V mA 200 mW Operating temperature Topr -40 to +85 °C Storage temperature Tstg -55 to +125 °C Allowable Operating Ranges at Ta = -40 to +85°C, VSS = 0V Parameter Symbol Ratings Conditions min typ Unit max Supply voltage VDD VDD Input voltage VDD1 VDD1 2/3VDD VDD VDD2 VDD2 1/3VDD VDD VIH1 CE, CL, DI, INH 0.4VDD 6.0 VIH2 OSCI: External clock operating mode 0.4VDD VDD Input high-level voltage Input low-level voltage 4.5 6.0 V V V VIL1 CE, CL, DI, INH 0 0.2VDD VIL2 OSCI: External clock operating mode 0 0.2VDD External clock operating frequency fCK OSCI: External clock operating mode [Figure 4] 10 300 600 kHz External clock duty cycle DCK OSCI: External clock operating mode [Figure 4] 30 50 70 % V Data setup time tds CL, DI [Figure 2][Figure 3] 160 ns Data hold time tdh CL, DI [Figure 2][Figure 3] 160 ns CE wait time tcp CE, CL [Figure 2][Figure 3] 160 ns CE setup time tcs CE, CL [Figure 2][Figure 3] 160 ns CE hold time tch CE, CL [Figure 2][Figure 3] 160 ns High-level clock pulse width tφH CL [Figure 2][Figure 3] 160 ns Low-level clock pulse width tφL CL [Figure 2][Figure 3] 160 ns Rise time tr CE, CL, DI [Figure 2][Figure 3] 160 Fall time tf CE, CL, DI [Figure 2][Figure 3] 160 INH switching time tc INH, CE [Figure 5][Figure 6] 10 ns ns μs No.A1953-2/27 LC75839PW Electrical Characteristics for the Allowable Operating Ranges Parameter Symbol Pin Ratings Conditions min typ Unit max Hysteresis VH CE, CL, DI, INH Input high-level current IIH1 CE, CL, DI, INH VI = 6.0V 5.0 IIH2 OSCI VI = VDD: External clock operating mode 5.0 IIL1 CE, CL, DI, INH VI = 0V -5.0 IIL2 OSCI VI = 0V: External clock operating mode -5.0 Input low-level current Output high-level voltage 0.03VDD VOH1 S1 to S53 IO = -20μA VOH2 COM1 IO = -100μA VOH3 P1 to P4 IO = -1mA VOL1 S1 to S53 IO = 20μA VOL2 COM1 IO = 100μA μA V VDD-0.9 VDD-0.9 0.9 0.9 to COM4 Output middle-level VOL3 P1 to P4 IO =1mA VMID1 S1 to S53 1/3 bias IO = ±20μA 2/3VDD -0.9 +0.9 VMID2 S1 to S53 1/3 bias IO = ±20μA 1/3VDD 1/3VDD -0.9 +0.9 VMID3 COM1 1/3 bias IO = ±100μA 2/3VDD 2/3VDD -0.9 +0.9 VMID4 COM1 1/3 bias IO = ±100μA 1/3VDD 1/3VDD -0.9 +0.9 to COM4 to COM4 fosc Internal Internal oscillator operating mode oscillator circuit Current drain V 0.9 voltage *1 Oscillator frequency μA VDD-0.9 to COM4 Output low-level voltage V IDD1 VDD Power-saving mode IDD2 VDD VDD = 6.0V Output open 240 2/3VDD 300 360 V kHz 100 800 1600 Internal oscillator operating mode IDD3 VDD VDD = 6.0V Output open μA External clock operating mode fCK = 300kHz 800 1600 VIH2 = 0.5VDD VIL2 = 0.1VDD Note: *1 Excluding the bias voltage generation divider resistors built in the VDD1 and VDD2. (See Figure 1.) VDD VDD1 To the common and segment drivers VDD2 Except these resistors. VSS [Figure 1] No.A1953-3/27 LC75839PW 1. When CL is stopped at the low level ≈ VIH1 CE CL ≈ ≈ tφH tφL tf DI tcp ≈ ≈ VIH1 VIL1 tds ≈ ≈ ≈ VIH1 50% VIL1 tr VIL1 tcs tch tdh [Figure 2] 2. When CL is stopped at the high level ≈ VIH1 CE ≈ VIL1 tφH ≈ tφL tf tr tcp tcs ≈ ≈ ≈ ≈ ≈ VIH1 50% VIL1 CL VIH1 DI VIL1 tds tch tdh [Figure 3] 3. OSCI pin clock timing in external clock operating mode tCKH OSCI VIH2 50% VIL2 tCKL fCK= 1 tCKH+ tCKL [kHz] tCKH ×100[%] DCK= tCKH+ tCKL [Figure 4] No.A1953-4/27 LC75839PW Package Dimensions unit : mm (typ) 3190A 12.0 0.5 10.0 33 32 64 17 10.0 49 1 12.0 48 16 0.5 0.15 0.18 0.1 1.7max (1.5) (1.25) SANYO : SQFP64(10X10) S34 S33 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 Pin Assignment 48 33 49 32 S49 S32 S50 S31 S51/COM4 S30 COM3 COM2 S29 S28 COM1 S27 S26 S52 LC75839PW (SQFP64) VDD VDD1 S25 S24 S23 VDD2 VSS S53/OSCI INH S22 CE S19 CL DI S18 S17 S21 S20 64 17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 P4/S4 P2/S2 P3/S3 16 P1/S1 1 Top view No.A1953-5/27 LC75839PW COMMON DRIVER S1/P1 S2/P2 S3/P3 S4/P4 S5 S50 S52 COM3 COM4/S51 COM2 COM1 Block Diagram SEGMENT DRIVER & LATCH INH S53/OSCI CLOCK GENERATOR CONTROL REGISTER VDD SHIFT REGISTER VDD1 VDD2 CCB INTERFACE CE CL DI VSS No.A1953-6/27 LC75839PW Pin Functions Handling Symbol Pin No. Function Active I/O when unused S1/P1 to S4/P4 1 to 4 S5 to S50 5 to 50 S52 55 COM1 to COM3 54 to 52 COM4/S51 51 S53/OSCI 60 CE 62 CL 63 DI 64 Segment outputs for displaying the display data transferred by serial data input. The S1/P1 to S4/P4 pins can be used as general-purpose output ports under serial data control. - O OPEN - O OPEN - I/O OPEN Common driver outputs The frame frequency is fo[Hz]. The COM4/S51 pin can be used as a segment output in 1/3 duty. Segment output. This pin can also be used as the external clock input pin when the external clock operating mode is selected by control data. Serial data transfer inputs. Must be connected to the controller. H CE: Chip enable CL: Synchronization clock DI: Transfer data I I GND - I L I GND Display off control input • INH = low (VSS) ...Display forced off S1/P1 to S4/P4 = low (VSS) (These pins are forcibly set to the general-purpose output port function and held at the VSS level.) S5 to S50, S52=low (VSS) COM1 to COM3=low (VSS) COM4/S51=low (VSS) S53/OSCI=low (VSS) INH 61 (These pins are forcibly set to the segment output port function and held at the VSS level.) Stops the internal oscillator. Inhibits external clock input. • INH = high (VDD)...Display on Enables the internal oscillator circuit. (Internal oscillator operating mode) Enables external clock input. (External clock operating mode) However, serial data transfer is possible when the display is forced off. VDD1 57 Used to apply the LCD drive 2/3 bias voltage externally. - I OPEN VDD2 58 Used to apply the LCD drive 1/3 bias voltage externally. - I OPEN VDD 56 Power supply pin. A power voltage of 4.5 to 6.0V must be applied to this pin. - - - VSS 59 Ground pin. Must be connected to ground. - - - No.A1953-7/27 LC75839PW Serial Data Input 1. 1/4 duty (1) When CL is stopped at the low level CE CL DI 1 0 0 0 1 0 1 0 D1 D2 D47 D48 D49 D50 D51 D52 0 0 0 0 PS10 PS11 EXF P0 P1 P2 DT DN FC0 FC1 FC2 OC SC BU 0 0 B0 B1 B2 B3 A0 A1 A2 A3 1 0 0 0 1 0 Control data 18 bits Display data 52 bits CCB address 8 bits 1 0 D53 D54 D99 D100 D101 D102 D103 D104 0 0 0 0 0 0 0 0 0 0 DD 2 bits 0 PS2 PS3 PS4 PF0 PF1 PF2 PF3 0 1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits 1 0 0 0 1 0 Display data 52 bits 1 0 D105 D106 D151 D152 0 Control data 18 bits 0 0 DD 2 bits 0 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 1 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits 1 0 0 0 1 0 Display data 48 bits 1 0 D153 D154 Control data 22 bits D199 D200 D201 D202 D203 D204 D205 D206 D207 D208 0 0 0 0 0 DD 2 bits 0 0 0 0 0 0 0 0 0 1 1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits Display data 56 bits Fixed data 14 bits DD 2 bits Note: DD is the direction data. No.A1953-8/27 LC75839PW (2) When CL is stopped at the high level CE CL DI 1 0 0 0 1 0 1 0 D1 D2 D47 D48 D49 D50 D51 D52 0 0 0 0 PS10 PS11 EXF P0 P1 P2 DT DN FC0 FC1 FC2 OC SC BU 0 0 B0 B1 B2 B3 A0 A1 A2 A3 1 0 0 0 1 0 Control data 18 bits Display data 52 bits CCB address 8 bits 1 0 D53 D54 D99 D100 D101 D102 D103 D104 0 0 0 0 0 0 0 0 0 0 DD 2 bits 0 PS2 PS3 PS4 PF0 PF1 PF2 PF3 0 1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits 1 0 0 0 1 0 Display data 52 bits 1 0 D105 D106 D151 D152 0 DD 2 bits Control data 18 bits 0 0 0 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 1 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits 1 0 0 0 1 0 Display data 48 bits 1 0 D153 D154 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits Note: DD is the direction data. • CCB address ......................... • D1 to D208 ........................... • PS10, PS11, PS2 to PS4 ........ • EXF ...................................... • P0 to P2 ................................ • DT ........................................ • DN ........................................ • FC0 to FC2 ........................... • OC ........................................ • SC ......................................... • BU ........................................ • PF0 to PF3 ............................ • W10 to W15, W20 to W25,... W30 to W35 Control data 22 bits D199 D200 D201 D202 D203 D204 D205 D206 D207 D208 0 Display data 56 bits 0 0 0 0 DD 2 bits 0 0 0 Fixed data 14 bits 0 0 0 0 0 0 1 1 DD 2 bits “51H” Display data General-purpose output port (P1 to P4) function setting control data External clock operating frequency setting control data Segment output port/general-purpose output port switching control data 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data S52 pin and S53/OSCI pin state setting control data Common/segment output waveform frame frequency control data Internal oscillator operating mode/external clock operating mode switching control data Segment on/off control data Normal mode/power-saving mode control data PWM output waveform frame frequency setting control data PWM data of the PWM output No.A1953-9/27 LC75839PW 2. 1/3 duty (1) When CL is stopped at the low level CE CL DI 1 0 0 0 1 0 1 0 D1 D2 D47 D48 D49 D50 D51 D52 D53 D54 0 0 PS10 PS11 EXF P0 P1 P2 DT DN FC0 FC1 FC2 OC SC BU 0 0 B0 B1 B2 B3 A0 A1 A2 A3 1 0 0 0 1 0 Control data 16 bits Display data 54 bits CCB address 8 bits 1 0 D55 D56 D101 D102 D103 D104 D105 D106 D107 D108 0 0 0 0 0 0 0 0 DD 2 bits 0 PS2 PS3 PS4 PF0 PF1 PF2 PF3 0 1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits 1 0 0 0 1 0 Display data 54 bits 1 0 D109 D110 Control data 16 bits DD 2 bits D155 D156 D157 D158 D159 0 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 1 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits Display data 51 bits Control data 19 bits DD 2 bits Note: DD is the direction data. No.A1953-10/27 LC75839PW (2) When CL is stopped at the high level CE CL DI 1 0 0 0 1 0 1 0 D1 D2 D47 D48 D49 D50 D51 D52 D53 D54 0 0 PS10 PS11 EXF P0 P1 P2 DT DN FC0 FC1 FC2 OC SC BU 0 0 B0 B1 B2 B3 A0 A1 A2 A3 1 0 0 0 1 0 Control data 16 bits Display data 54 bits CCB address 8 bits 1 0 D55 D56 D101 D102 D103 D104 D105 D106 D107 D108 0 0 0 0 0 0 0 0 DD 2 bits 0 PS2 PS3 PS4 PF0 PF1 PF2 PF3 0 1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits 1 0 0 0 1 0 Display data 54 bits 1 0 D109 D110 Control data 16 bits DD 2 bits D155 D156 D157 D158 D159 0 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 1 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits Note: DD is the direction data. • CCB address ......................... • D1 to D159 ........................... • PS10, PS11, PS2 to PS4 ........ • EXF ...................................... • P0 to P2 ................................ • DT ........................................ • DN ........................................ • FC0 to FC2 ........................... • OC ........................................ • SC ......................................... • BU ........................................ • PF0 to PF3 ............................ • W10 to W15, W20 to W25,... W30 to W35 Display data 51 bits Control data 19 bits DD 2 bits “51H” Display data General-purpose output port (P1 to P4) function setting control data External clock operating frequency setting control data Segment output port/general-purpose output port switching control data 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data S52 pin and S53/OSCI pin state setting control data Common/segment output waveform frame frequency control data Internal oscillator operating mode/external clock operating mode switching control data Segment on/off control data Normal mode/power-saving mode control data PWM output waveform frame frequency setting control data PWM data of the PWM output No.A1953-11/27 LC75839PW Serial Data Transfer Example 1. 1/4 duty • When 153 or more segments are used All 288 bits of serial data must be sent. 8 bits 1 0 0 0 1 72 bits 0 1 0 D1 D2 D47 D48 D49 D50 D51 D52 0 0 0 0 PS10 PS11 EXF P0 P1 P2 DT DN FC0 FC1 FC2 OC SC BU 0 0 D53 D54 D99 D100 D101 D102 D103 D104 0 0 0 0 0 PS2 PS3 PS4 PF0 PF1 PF2 PF3 0 1 D105 D106 D151 D152 0 0 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 1 0 D153 D154 D199 D200 D201 D202 D203 D204 D205 D206 D207 D208 0 B0 B1 B2 B3 A0 A1 A2 A3 1 0 0 0 1 0 1 0 0 0 0 0 0 0 B0 B1 B2 B3 A0 A1 A2 A3 1 0 0 0 1 0 1 0 0 0 B0 B1 B2 B3 A0 A1 A2 A3 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 B0 B1 B2 B3 A0 A1 A2 A3 • When fewer than 153 segments are used 216 bits of serial data shown below (the D1 to D152 display data and the control data) must always be sent. 8 bits 1 0 0 0 1 72 bits 0 1 0 D1 D2 D47 D48 D49 D50 D51 D52 0 0 0 0 PS10 PS11 EXF P0 P1 P2 DT DN FC0 FC1 FC2 OC SC BU 0 0 D53 D54 D99 D100 D101 D102 D103 D104 0 0 0 0 0 PS2 PS3 PS4 PF0 PF1 PF2 PF3 0 1 D105 D106 D151 D152 0 0 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 1 0 B0 B1 B2 B3 A0 A1 A2 A3 1 0 0 0 1 0 1 0 0 0 0 0 0 0 B0 B1 B2 B3 A0 A1 A2 A3 1 0 0 0 1 0 1 0 0 0 B0 B1 B2 B3 A0 A1 A2 A3 2. 1/3 duty All 216 bits of serial data must be sent. 8 bits 1 0 0 0 1 72 bits 0 1 0 D1 D2 D47 D48 D49 D50 D51 D52 D53 D54 0 0 PS10 PS11 EXF P0 P1 P2 DT DN FC0 FC1 FC2 OC SC BU 0 0 D55 D56 D101 D102 D103 D104 D105 D106 D107 D108 0 0 0 PS2 PS3 PS4 PF0 PF1 PF2 PF3 0 1 D109 D110 D155 D156 D157 D158 D159 0 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 1 0 B0 B1 B2 B3 A0 A1 A2 A3 1 0 0 0 1 0 1 0 0 0 0 0 0 0 B0 B1 B2 B3 A0 A1 A2 A3 1 0 0 0 1 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 No.A1953-12/27 LC75839PW Control Data Functions (1) PS10 and PS11, PS2 to PS4 … General-purpose output port (P1 to P4) function setting control data These control data bits set the general-purpose output function (High or low level output), clock output function or PWM output function of the P1 output pin, and the general-purpose output function (High or low level output) or PWM output function of the P2 to P4 output pins. However, be careful of being unable to set a PWM output function when the external clock operating frequency is set the fCK2=38[kHz] typ (EXF="1") in external clock operating mode (OC= "1"). PS10 PS11 General-purpose output port (P1) function 0 0 General-purpose output function (High or low level output) 1 0 Clock output function (Clock frequency : fosc/2, fCK/2) 0 1 Clock output function (Clock frequency : fosc/8, fCK/8) 1 1 PWM output function (Support for PWM data W10 to W15) PS2 General-purpose output port (P2) function 0 General-purpose output function (High or low level output) 1 PWM output function (Support for PWM data W20 to W25) PS3 General-purpose output port (P3) function 0 General-purpose output function (High or low level output) 1 PWM output function (Support for PWM data W30 to W35) PS4 General-purpose output port (P4) function 0 General-purpose output function (High or low level output) 1 PWM output function (Support for PWM data W10 to W15) (2) EXF … External clock operating frequency setting control data This control data sets the operating frequency of the external clock which input into the OSCI pin, when the external clock operating mode (OC=”1”) is set. However, this control data is effective only when external clock operating mode (OC= "1") is set. EXF External clock operating frequency fCK[kHz] 0 fCK1=300[kHz]typ 1 fCK2=38[kHz]typ No.A1953-13/27 LC75839PW (3) P0 to P2 … Segment output port/general-purpose output port switching control data These control data bits switch the segment output port/general-purpose output port functions of the S1/P1 to S4/P4 output pins. Control data Output pin state P0 P1 P2 S1/P1 S2/P2 S3/P3 S4/P4 0 0 0 S1 S2 S3 S4 0 0 1 P1 S2 S3 S4 0 1 0 P1 P2 S3 S4 0 1 1 P1 P2 P3 S4 1 0 0 P1 P2 P3 P4 Note: Sn (n=1 to 4): Segment output ports Pn (n=1 to 4): General-purpose output ports Note: When are setting (P0,P1,P2)=(1,0,1), (1,1,0), and (1,1,1), the all P1/S1 to P4/S4 output pins selects the segment output port. The table below lists the correspondence between the display data and the output pins when these pins are selected to be general-purpose output ports. Correspondence display data Output pin 1/4 duty 1/3 duty S1/P1 D1 D1 S2/P2 D5 D4 S3/P3 D9 D7 S4/P4 D13 D10 For example, if the circuit is operated in 1/4 duty and the S4/P4 output pin is selected to be a general-purpose output port, the S4/P4 output pin will output a high level when the display data D13 is 1, and will output a low level when D13 is 0. (4) DT … 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data This control data bit selects either 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive. DT Drive scheme The COM4/S51 pin state 0 1/4-duty 1/3-bias drive COM4 1 1/3-duty 1/3-bias drive S51 Note: COM4: Common output S51 : Segment output (5) DN … S52 pin and S53/OSCI pin state setting control data This control data bit sets state of the S52 pin and the S53/OSCI pin. Number of display segments DN Pin state 1/4 duty 1/3 duty S52 S53/OSCI 0 Up to 200 segments Up to 153 segments “L” (VSS) “L” (VSS)/OSCI 1 Up to 208 segments Up to 159 segments S52 S53/OSCI Note: “L” (VSS) : Low (VSS) level output S52 : Segment output “L” (VSS)/OSCI : Low (VSS) level output in internal oscillator operating mode (OC=0) : External clock input in external clock operating mode (OC=1) S53/OSCI : Segment output in internal oscillator operating mode (OC=0) External clock input in external clock operating mode (OC=1) No.A1953-14/27 LC75839PW (6) FC0 to FC2 … Common/segment output waveform fram frequency control data These control data bits set the frame frequency of the common and segment output waveforms. Control data FC0 FC1 Frame frequency fo[Hz] FC2 Internal oscillator operating mode External clock operating mode (The control data OC is 0, (The control data OC is 1 External clock operating mode (The control data OC is 1 fosc=300[kHz]typ) and EXF is 0, fCK1=300[kHz]typ) and EXF is 1, fCK2=38[kHz]typ) 0 0 0 fosc/6144 fCK1/6144 fCK2/768 0 0 1 fosc/4608 fCK1/4608 fCK2/576 0 1 0 fosc/3072 fCK1/3072 fCK2/384 0 1 1 fosc/2304 fCK1/2304 fCK2/288 1 0 0 fosc/1536 fCK1/1536 fCK2/192 1 0 1 fosc/1152 fCK1/1152 fCK2/144 1 1 0 fosc/768 fCK1/768 fCK2/96 Note: When is setting (FC0,FC1,FC2)=(1,1,1), the frame frequency is same as frame frequency at the time of the (FC0,FC1,FC2)=(0,1,0) setting (fosc/3072, fCK1/3072, fCK2/384). (7) OC … Internal oscillator operating mode/external clock operating mode switching control data This control data bit selects either the internal oscillator operating mode or external clock operating mode. I/O pin (S53/OSCI) state OC Fundamental clock operating mode 0 Internal oscillator operating mode S53 1 External clock operating mode OSCI Note: S53: Segment output OSCI: External clock input (8) SC … Segment on/off control data This control data bit controls the on/off state of the segments. SC Display state 0 On 1 Off Note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off waveforms from the segment output pins. (9) BU … Normal mode/power-saving mode control data This control data bit selects either normal mode or power-saving mode. BU 0 Mode Normal mode Power saving mode In this mode, the internal oscillator circuit stops oscillation (the S53/OSCI pin is configured for segment output) if the IC is in the internal oscillator operating mode (OC=0) and the IC stops receiving external 1 clock signals (the S53/OSCI pin is configured for external clock input) if the IC is in the external clock operating mode (OC=1). The common and segment output pins go to the VSS level. However, the S1/P1 to S4/P4 output pins can be used as general-purpose output ports under the control of the data bits P0 to P2. (The general-purpose output port P1 to P4 can not be used as clock output or PWM output.) No.A1953-15/27 LC75839PW (10) PF0 to PF3 … PWM output waveform frame frequency setting control data These control data bits set the frame frequency of the PWM output waveforms. However, when the PWM output function isn’t used, these control data bits become invalid. In addition, when the external clock operating frequency is set the fCK2=38[kHz]typ (EXF="1") in external clock operating mode (OC= "1"), these control data bits become invalid. Control data PF0 PF1 PF2 PWM output waveform frame frequency fp[Hz] PF3 Internal oscillator operating mode External clock operating mode (The control data OC is 0, (The control data OC is 1 and EXF is 0, fosc=300[kHz] typ) fCK1=300[kHz] typ) 0 0 0 0 fosc/1536 fCK1/1536 1 0 0 0 fosc/1408 fCK1/1408 0 1 0 0 fosc/1280 fCK1/1280 1 1 0 0 fosc/1152 fCK1/1152 0 0 1 0 fosc/1024 fCK1/1024 1 0 1 0 fosc/896 fCK1/896 0 1 1 0 fosc/768 fCK1/768 1 1 1 0 fosc/640 fCK1/640 0 0 0 1 fosc/512 fCK1/512 1 0 0 1 fosc/384 fCK1/384 0 1 0 1 fosc/256 fCK1/256 Note: When is setting (PF0,PF1,PF2,PF3)=(1,1,0,1) and (X,X,1,1), the frame frequency is same as frame frequency at the time of the (PF0,PF1,PF2,PF3)=(1,0,1,0) setting (fosc/896, fCK1/896). X: don’t care No.A1953-16/27 LC75839PW (11) W10 to W15, W20 to W25, W30 to W35 … PWM data of the PWM output These control data bits set the pulse width of the PWM output P1 to P4. However, when the PWM output function isn’t used, these control data bits become invalid. In addition, when the external clock operating frequency is set the fCK2=38[kHz]typ (EXF="1") in external clock operating mode (OC= "1"), these control data bits become invalid. Wn0 Wn1 Wn2 Wn3 Wn4 Wn5 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 1 1 0 1 0 1 1 0 Pulse width of Pulse width of Wn0 Wn1 Wn2 Wn3 Wn4 Wn5 (1/64)×Tp 0 0 0 0 0 1 (33/64)×Tp (2/64)×Tp 1 0 0 0 0 1 (34/64)×Tp 0 (3/64)×Tp 0 1 0 0 0 1 (35/64)×Tp 0 0 (4/64)×Tp 1 1 0 0 0 1 (36/64)×Tp 0 0 0 (5/64)×Tp 0 0 1 0 0 1 (37/64)×Tp 0 0 0 (6/64)×Tp 1 0 1 0 0 1 (38/64)×Tp 1 0 0 0 (7/64)×Tp 0 1 1 0 0 1 (39/64)×Tp 1 1 0 0 0 (8/64)×Tp 1 1 1 0 0 1 (40/64)×Tp 0 0 1 0 0 (9/64)×Tp 0 0 0 1 0 1 (41/64)×Tp 1 0 0 1 0 0 (10/64)×Tp 1 0 0 1 0 1 (42/64)×Tp 0 1 0 1 0 0 (11/64)×Tp 0 1 0 1 0 1 (43/64)×Tp 1 1 0 1 0 0 (12/64)×Tp 1 1 0 1 0 1 (44/64)×Tp 0 0 1 1 0 0 (13/64)×Tp 0 0 1 1 0 1 (45/64)×Tp 1 0 1 1 0 0 (14/64)×Tp 1 0 1 1 0 1 (46/64)×Tp 0 1 1 1 0 0 (15/64)×Tp 0 1 1 1 0 1 (47/64)×Tp 1 1 1 1 0 0 (16/64)×Tp 1 1 1 1 0 1 (48/64)×Tp 0 0 0 0 1 0 (17/64)×Tp 0 0 0 0 1 1 (49/64)×Tp 1 0 0 0 1 0 (18/64)×Tp 1 0 0 0 1 1 (50/64)×Tp 0 1 0 0 1 0 (19/64)×Tp 0 1 0 0 1 1 (51/64)×Tp 1 1 0 0 1 0 (20/64)×Tp 1 1 0 0 1 1 (52/64)×Tp 0 0 1 0 1 0 (21/64)×Tp 0 0 1 0 1 1 (53/64)×Tp 1 0 1 0 1 0 (22/64)×Tp 1 0 1 0 1 1 (54/64)×Tp 0 1 1 0 1 0 (23/64)×Tp 0 1 1 0 1 1 (55/64)×Tp 1 1 1 0 1 0 (24/64)×Tp 1 1 1 0 1 1 (56/64)×Tp 0 0 0 1 1 0 (25/64)×Tp 0 0 0 1 1 1 (57/64)×Tp 1 0 0 1 1 0 (26/64)×Tp 1 0 0 1 1 1 (58/64)×Tp 0 1 0 1 1 0 (27/64)×Tp 0 1 0 1 1 1 (59/64)×Tp 1 1 0 1 1 0 (28/64)×Tp 1 1 0 1 1 1 (60/64)×Tp 0 0 1 1 1 0 (29/64)×Tp 0 0 1 1 1 1 (61/64)×Tp 1 0 1 1 1 0 (30/64)×Tp 1 0 1 1 1 1 (62/64)×Tp 0 1 1 1 1 0 (31/64)×Tp 0 1 1 1 1 1 (63/64)×Tp 1 1 1 1 1 0 (32/64)×Tp 1 1 1 1 1 1 (64/64)×Tp PWM output Note: W10 to W15 … PWM data of the output pin S1/P1 and S4/P4 W20 to W25 … PWM data of the output pin S2/P2 W30 to W35 … PWM data of the output pin S3/P3 PWM output n=1 to 3 Tp= 1 fp No.A1953-17/27 LC75839PW Display Data and Output Pin Correspondence (1/4 Duty) Output pin COM1 COM2 COM3 COM4 Output pin COM1 COM2 COM3 COM4 S1/P1 D1 D2 D3 D4 S27 D105 D106 D107 D108 S2/P2 D5 D6 D7 D8 S28 D109 D110 D111 D112 S3/P3 D9 D10 D11 D12 S29 D113 D114 D115 D116 S4/P4 D13 D14 D15 D16 S30 D117 D118 D119 D120 S5 D17 D18 D19 D20 S31 D121 D122 D123 D124 S6 D21 D22 D23 D24 S32 D125 D126 D127 D128 S7 D25 D26 D27 D28 S33 D129 D130 D131 D132 S8 D29 D30 D31 D32 S34 D133 D134 D135 D136 S9 D33 D34 D35 D36 S35 D137 D138 D139 D140 S10 D37 D38 D39 D40 S36 D141 D142 D143 D144 S11 D41 D42 D43 D44 S37 D145 D146 D147 D148 S12 D45 D46 D47 D48 S38 D149 D150 D151 D152 S13 D49 D50 D51 D52 S39 D153 D154 D155 D156 S14 D53 D54 D55 D56 S40 D157 D158 D159 D160 S15 D57 D58 D59 D60 S41 D161 D162 D163 D164 S16 D61 D62 D63 D64 S42 D165 D166 D167 D168 S17 D65 D66 D67 D68 S43 D169 D170 D171 D172 S18 D69 D70 D71 D72 S44 D173 D174 D175 D176 S19 D73 D74 D75 D76 S45 D177 D178 D179 D180 S20 D77 D78 D79 D80 S46 D181 D182 D183 D184 S21 D81 D82 D83 D84 S47 D185 D186 D187 D188 S22 D85 D86 D87 D88 S48 D189 D190 D191 D192 S23 D89 D90 D91 D92 S49 D193 D194 D195 D196 S24 D93 D94 D95 D96 S50 D197 D198 D199 D200 S25 D97 D98 D99 D100 S52 D201 D202 D203 D204 S26 D101 D102 D103 D104 S53/OSCI D205 D206 D207 D208 Note: This table assumes that pins S1/P1 to S4/P4 and S53/OSCI are configured for segment output. For example, the table below lists the output states for the S21 output pin. Display data Output pin (S21) state D81 D82 D83 D84 0 0 0 0 The LCD segments corresponding to COM1, COM2, COM3, and COM4 are off. 0 0 0 1 The LCD segment corresponding to COM4 is on. 0 0 1 0 The LCD segment corresponding to COM3 is on. 0 0 1 1 The LCD segments corresponding to COM3 and COM4 are on. 0 1 0 0 The LCD segment corresponding to COM2 is on. 0 1 0 1 The LCD segments corresponding to COM2 and COM4 are on. 0 1 1 0 The LCD segments corresponding to COM2 and COM3 are on. 0 1 1 1 The LCD segments corresponding to COM2, COM3, and COM4 are on. 1 0 0 0 The LCD segment corresponding to COM1 is on. 1 0 0 1 The LCD segments corresponding to COM1 and COM4 are on. 1 0 1 0 The LCD segments corresponding to COM1 and COM3 are on. 1 0 1 1 The LCD segments corresponding to COM1, COM3, and COM4 are on. 1 1 0 0 The LCD segments corresponding to COM1 and COM2 are on. 1 1 0 1 The LCD segments corresponding to COM1, COM2, and COM4 are on. 1 1 1 0 The LCD segments corresponding to COM1, COM2, and COM3 are on. 1 1 1 1 The LCD segments corresponding to COM1, COM2, COM3, and COM4 are on. No.A1953-18/27 LC75839PW Display Data and Output Pin Correspondence (1/3 Duty) Output pin COM1 COM2 COM3 Output pin COM1 COM2 COM3 S1/P1 D1 D2 D3 S28 D82 D83 D84 S2/P2 D4 D5 D6 S29 D85 D86 D87 S3/P3 D7 D8 D9 S30 D88 D89 D90 S4/P4 D10 D11 D12 S31 D91 D92 D93 S5 D13 D14 D15 S32 D94 D95 D96 S6 D16 D17 D18 S33 D97 D98 D99 S7 D19 D20 D21 S34 D100 D101 D102 S8 D22 D23 D24 S35 D103 D104 D105 S9 D25 D26 D27 S36 D106 D107 D108 S10 D28 D29 D30 S37 D109 D110 D111 S11 D31 D32 D33 S38 D112 D113 D114 S12 D34 D35 D36 S39 D115 D116 D117 S13 D37 D38 D39 S40 D118 D119 D120 S14 D40 D41 D42 S41 D121 D122 D123 S15 D43 D44 D45 S42 D124 D125 D126 S16 D46 D47 D48 S43 D127 D128 D129 S17 D49 D50 D51 S44 D130 D131 D132 S18 D52 D53 D54 S45 D133 D134 D135 S19 D55 D56 D57 S46 D136 D137 D138 S20 D58 D59 D60 S47 D139 D140 D141 S21 D61 D62 D63 S48 D142 D143 D144 S22 D64 D65 D66 S49 D145 D146 D147 S23 D67 D68 D69 S50 D148 D149 D150 S24 D70 D71 D72 S51/COM4 D151 D152 D153 S25 D73 D74 D75 S52 D154 D155 D156 S26 D76 D77 D78 S53/OSCI D157 D158 D159 S27 D79 D80 D81 Note: This table assumes that pins S1/P1 to S4/P4, S51/COM4, and S53/OSCI are configured for segment output. For example, the table below lists the output states for the S21 output pin. Display data Output pin (S21) state D61 D62 D63 0 0 0 The LCD segments corresponding to COM1, COM2, and COM3 are off. 0 0 1 The LCD segment corresponding to COM3 is on. 0 1 0 The LCD segment corresponding to COM2 is on. 0 1 1 The LCD segments corresponding to COM2 and COM3 are on. 1 0 0 The LCD segment corresponding to COM1 is on. 1 0 1 The LCD segments corresponding to COM1 and COM3 are on. 1 1 0 The LCD segments corresponding to COM1 and COM2 are on. 1 1 1 The LCD segments corresponding to COM1, COM2, and COM3 are on. No.A1953-19/27 LC75839PW Output waveforms (1/4-Duty 1/3-Bias Drive Scheme) fo[Hz] VDD VDD1 VDD2 0V VDD VDD1 VDD2 0V VDD VDD1 VDD2 0V VDD VDD1 VDD2 0V VDD VDD1 VDD2 0V VDD VDD1 VDD2 0V VDD VDD1 VDD2 0V VDD VDD1 VDD2 0V VDD VDD1 VDD2 0V VDD VDD1 VDD2 0V VDD VDD1 VDD2 0V VDD VDD1 VDD2 0V VDD VDD1 VDD2 0V VDD VDD1 VDD2 0V VDD VDD1 VDD2 0V COM1 COM2 COM3 COM4 LCD driver output when all LCD segments corresponding to COM1, COM2, COM3, and COM4 are off. LCD driver output when only LCD segments corresponding to COM1 are on. LCD driver output when only LCD segments corresponding to COM2 are on. LCD driver output when LCD segments corresponding to COM1 and COM2 are on. LCD driver output when only LCD segments corresponding to COM3 are on. LCD driver output when LCD segments corresponding to COM1 and COM3 are on. LCD driver output when LCD segments corresponding to COM2 and COM3 are on. LCD driver output when LCD segments corresponding to COM1, COM2, and COM3 are on. LCD driver output when only LCD segments corresponding to COM4 are on. LCD driver output when LCD segments corresponding to COM2 and COM4 are on. LCD driver output when all LCD segments corresponding to COM1, COM2, COM3, and COM4 are on. Control data Frame frequency fo[Hz] FC0 FC1 FC2 Internal oscillator operating mode (The control data OC is 0, fosc=300[kHz]typ) 0 0 0 fosc/6144 fCK1/6144 fCK2/768 0 0 1 fosc/4608 fCK1/4608 fCK2/576 0 1 0 fosc/3072 fCK1/3072 fCK2/384 0 1 1 fosc/2304 fCK1/2304 fCK2/288 1 0 0 fosc/1536 fCK1/1536 fCK2/192 1 0 1 fosc/1152 fCK1/1152 fCK2/144 1 1 0 fosc/768 fCK1/768 fCK2/96 External clock operating mode (The control data OC is 1 and EXF is 0, fCK1=300[kHz]typ) External clock operating mode (The control data OC is 1 and EXF is 1, fCK2=38[kHz]typ) Note: When is setting (FC0,FC1,FC2)=(1,1,1), the frame frequency is same as frame frequency at the time of the (FC0,FC1,FC2)=(0,1,0) setting (fosc/3072, fCK1/3072, fCK2/384). No.A1953-20/27 LC75839PW Output waveforms (1/3-Duty 1/3-Bias Drive Scheme) fo[Hz] COM1 VDD VDD1 VDD2 0V COM2 VDD VDD1 VDD2 0V COM3 VDD VDD1 VDD2 0V LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are off. VDD VDD1 VDD2 0V LCD driver output when only LCD segments corresponding to COM1 are on. VDD VDD1 VDD2 0V LCD driver output when only LCD segments corresponding to COM2 are on. VDD VDD1 VDD2 0V LCD driver output when LCD segments corresponding to COM1 and COM2 are on. VDD VDD1 VDD2 0V LCD driver output when only LCD segments corresponding to COM3 are on. VDD VDD1 VDD2 0V LCD driver output when LCD segments corresponding to COM1 and COM3 are on. VDD VDD1 VDD2 0V LCD driver output when LCD segments corresponding to COM2 and COM3 are on. VDD VDD1 VDD2 0V LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are on. VDD VDD1 VDD2 0V Control data Frame frequency fo[Hz] FC0 FC1 FC2 Internal oscillator operating mode (The control data OC is 0, fosc=300[kHz]typ) 0 0 0 fosc/6144 fCK1/6144 fCK2/768 0 0 1 fosc/4608 fCK1/4608 fCK2/576 0 1 0 fosc/3072 fCK1/3072 fCK2/384 0 1 1 fosc/2304 fCK1/2304 fCK2/288 1 0 0 fosc/1536 fCK1/1536 fCK2/192 1 0 1 fosc/1152 fCK1/1152 fCK2/144 1 1 0 fosc/768 fCK1/768 fCK2/96 External clock operating mode (The control data OC is 1 and EXF is 0, fCK1=300[kHz]typ) External clock operating mode (The control data OC is 1 and EXF is 1, fCK2=38[kHz]typ) Note: When is setting (FC0,FC1,FC2)=(1,1,1), the frame frequency is same as frame frequency at the time of the (FC0,FC1,FC2)=(0,1,0) setting (fosc/3072, fCK1/3072, fCK2/384). No.A1953-21/27 LC75839PW PWM output waveforms VDD P1/P4 (56/64)×Tp (1) VSS (56/64)×Tp VDD P2 (48/64)×Tp VSS (48/64)×Tp VDD P3 (40/64)×Tp VSS (40/64)×Tp VDD P1/P4 (8/64)×Tp (2) VSS (8/64)×Tp VDD P2 VSS (16/64)×Tp (16/64)×Tp VDD P3 VSS (24/64)×Tp (24/64)×Tp VDD P1/P4 (32/64)×Tp (3) VSS (32/64)×Tp VDD P2 (32/64)×Tp VSS (32/64)×Tp VDD P3 (32/64)×Tp VSS (32/64)×Tp Tp Tp= Tp 1 fp Control data PWM output W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 waveforms 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 0 1 (1) 1 1 1 0 0 0 1 1 1 1 0 0 1 1 1 0 1 0 (2) 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 (3) Control data PF0 PF1 PF2 PWM output waveform frame frequency fp[Hz] PF3 Internal oscillator operating mode External clock operating mode (The control data OC is 0, (The control data OC is 1 and fosc=300[kHz] typ) EXF is 0, fCK1=300[kHz] typ) 0 0 0 0 fosc/1536 fCK1/1536 1 0 0 0 fosc/1408 fCK1/1408 0 1 0 0 fosc/1280 fCK1/1280 1 1 0 0 fosc/1152 fCK1/1152 0 0 1 0 fosc/1024 fCK1/1024 1 0 1 0 fosc/896 fCK1/896 0 1 1 0 fosc/768 fCK1/768 1 1 1 0 fosc/640 fCK1/640 0 0 0 1 fosc/512 fCK1/512 1 0 0 1 fosc/384 fCK1/384 0 1 0 1 fosc/256 fCK1/256 Note: When is setting (PF0,PF1,PF2,PF3)=(1,1,0,1) and (X,X,1,1), the frame frequency is same as frame frequency at the time of the (PF0,PF1,PF2,PF3)=(1,0,1,0) setting (fosc/896, fCK1/896). X: don’t care No.A1953-22/27 LC75839PW Clock output waveforms Control data P1 Tc/2 1 Tc= fc Tc Clock frequency of clock output P1 PS10 PS11 fc(=1/Tc)[Hz] 1 0 Clock output function (fosc/2, fCK/2) 0 1 Clock output function (fosc/8, fCK/8) No.A1953-23/27 LC75839PW Display Control and the INH Pin Since the LSI internal data (1/4 duty : the display data D1 to D208 and the control data, 1/3 duty : the display data D1 to D159 and the control data) is undefined when power is first applied, applications should set the INH pin low at the same time as power is applied to turn off the display (This sets the S1/P1 to S4/P4, S5 to S50, COM1 to COM3, COM4/S51, S52, and S53/OSCI pins to the VSS level.) and during this period send serial data from the controller. The controller should then set the INH pin high after the data transfer has completed. This procedure prevents meaningless display at power on. (See Figure 5, Figure 6.) (1)1/4 duty t2 t1 VDD INH VIL1 tc CE VIL1 Display data and control data transferred Internal data D1 to D52,PS10,PS11, EXF,P0 to P2,DT,DN, FC0 to FC2,OC,SC,BU Undefined Defined Undefined Internal data D53 to D104,PS2 to PS4, PF0 to PF3 Undefined Defined Undefined Internal data D105 to D152,W10 to W15, W20 to W25, W30 to W35 Undefined Defined Undefined Internal data (D153 to D208) Defined Undefined Undefined Notes: t1>1ms t2>0 tc…10μs min [Figure 5] (2)1/3 duty t2 t1 VDD INH VIL1 tc CE VIL1 Display data and control data transferred Internal data D1 to D54,PS10,PS11, EXF,P0 to P2,DT,DN, FC0 to FC2,OC,SC,BU Undefined Defined Undefined Internal data D55 to D108,PS2 to PS4, PF0 to PF3 Undefined Defined Undefined Internal data D109 to D159,W10 to W15, W20 to W25, W30 to W35 Undefined Defined Undefined Notes: t1>1ms t2>0 tc…10μs min [Figure 6] No.A1953-24/27 LC75839PW Notes on Controller Transfer of Display Data When using the LC75839 in 1/4 duty, applications transfer the display data (D1 to D208) in four operations, and in 1/3 duty, they transfer the display data (D1 to D159) in three operations. In either case, applications should transfer all of the display data within 30 ms to maintain the quality of displayed image. S53/OSCI Pin Peripheral Circuit (1) Internal oscillator operating mode (control data OC=0) Connect the S53/OSCI pin to the LCD panel when the internal oscillator operating mode is selected. OSCI/S53 To LCD panel (2) External clock operating mode (control data OC=1) When the external clock operating mode is selected, insert a current protection resistor Rg (2.2 to 22kΩ) between the S53/OSCI pin and external clock output pin (external oscillator). Determine the value of the resistance according to the allowable current value at the external clock output pin. Also make sure that the waveform of the external clock is not heavily distorted. External clock output pin OSCI/S53 Rg External oscillator Note: Allowable current value at external clock output pin > VDD Rg (3) Unused pin treatment When the S53/OSCI pin is not to be used, select the internal oscillator operating mode (setting control data OC to 0) to keep the pin open. OSCI/S53 OPEN P1 to P4 pin peripheral circuit It is recommended the circuit shown below be used to adjust the brightness of the LED backlight using the PWM output P1 to P4 +5V LED P1 to P4 No.A1953-25/27 LC75839PW Sample Applications Circuit1 1/4 Duty, 1/3 Bias (P1) General-purpose output ports (P2) (P3) (P4) VDD +5V Used for functions such as backlight control COM1 COM2 VDD1 LCD panel (up to 208 segments) COM3 S51/COM4 VDD2 C P1/S1 C P2/S2 VSS P3/S3 P4/S4 S5 C≥0.047μF INH From the controller CE S50 S52 *2 CL DI *3 OSCI/S53 *2 The pins to be connected to the controller (CE, CL, DI, INH) can handle 3.3V or 5V. *3 Connect the S53/OSCI pin to the LCD panel in the internal oscillator operating mode and insert a current protection resistor Rg (2.2 to 22kΩ) between the S53/OSCI pin and external clock output pin (external oscillator) in the external clock operating mode (see “S53/OSCI Pin Peripheral Circuit”). Sample Application Circuit 2 1/3 Duty, 1/3 Bias (P1) General-purpose output ports (P2) (P3) (P4) VDD +5V Used for functions such as backlight control COM1 COM3 P1/S1 C VDD2 P2/S2 VSS P4/S4 C P3/S3 S5 C≥0.047μF S50 INH From the controller CE COM4/S51 *2 S52 CL DI LCD panel (up to 159 segments) COM2 VDD1 *3 OSCI/S53 *2 The pins to be connected to the controller (CE, CL, DI, INH) can handle 3.3V or 5V. *3 Connect the S53/OSCI pin to the LCD panel in the internal oscillator operating mode and insert a current protection resistor Rg (2.2 to 22kΩ) between the S53/OSCI pin and external clock output pin (external oscillator) in the external clock operating mode (see “S53/OSCI Pin Peripheral Circuit”). No.A1953-26/27 LC75839PW SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of June, 2011. Specifications and information herein are subject to change without notice. PS No.A1953-27/27