TCC 226 D

TCC-226
Six-Output PTIC Control IC
Introduction
TCC−226 is a six−output high−voltage digital to analog control IC
specifically designed to control and bias ON Semiconductor’s Passive
Tunable Integrated Circuits (PTICs).
These tunable capacitor control circuits are intended for use in
mobile phones and dedicated RF tuning applications. The
implementation of ON Semiconductor’s tunable circuits in mobile
phones enables significant improvement in terms of antenna radiated
performance.
The tunable capacitors are controlled through a bias voltage ranging
from 1 V to 24 V. The TCC−226 high−voltage PTIC control IC has
been specifically designed to cover this need, providing six
independent high−voltage outputs that control up to six different
tunable PTICs in parallel. The device is fully controlled through a
multi−protocol digital interface.
www.onsemi.com
WLCSP20
PACKAGE CODE COW−S
CASE 567MZ
MARKING DIAGRAM
Key Features
t26a
ALYW
G
• Controls ON Semiconductor’s PTIC Tunable Capacitors
• Compliant with Timing Needs of Cellular and Other Wireless System
Requirements
• Integrated Boost Converter with 6 Programmable DAC Outputs
(up to 24 V)
• Low Power Consumption
• Auto−detection of SPI (30− or 32−bit) or MIPI RFFE Interfaces
•
•
•
•
(1.8 V)
Available in WLCSP (RDL ball arrays)
Compliant with MIPI 26 MHz Read−Back
Footprint Compatible with TCC−303
This is a Pb−Free Device
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information on page 32 of
this data sheet.
Typical Applications
• Multi−band, Multi−standard, Advanced and Simple Mobile Phones
• Tunable Antenna Matching Networks
• Compatible with Closed−loop and Open−loop Antenna Tuner
Applications
© Semiconductor Components Industries, LLC, 2016
June, 2016 − Rev. 0
1
Publication Order Number:
TCC−226/D
TCC−226
Figure 1. Control IC Functional Block Diagram
Figure 2. Die Bump Side View (Left), and Marking Side View (Right)
www.onsemi.com
2
TCC−226
RDL Pin Out
Table 1. PAD DESCRIPTIONS
RDL
Name
Type
Description
A1
OUTD
AOH
High Voltage Output D
A2
OUTE
AOH
High Voltage Output E
A3
OUTF
AOH
High Voltage Output F
A4
GND_BOOST
P
Ground for Booster
B1
OUTC
AOH
High Voltage Output C
B2
VREG
AO
Regulator Output
B3
VHV
AOH / AIH
Boost High Voltage can be Forced Externally
B4
GNDA
P
Analog Ground
C1
OUTB
AOH
High Voltage Output B
C2
ATEST
AO
Analog Test Out (Note 1)
C3
L_BOOST
AOH
Boost Inductor
C4
TRIG
DIO
Trigger Signal Input (Note 2)
D1
OUTA
AOH
High Voltage Output A
D2
GNDIO
P
Digital IO Ground
D3
AVDD
P
Analog Supply
D4
CS
DI
Chip Select for SPI
E1
VIO
P
Digital IO Supply
E2
DATA
DIO
Digital IO (SPI and MIPI RFFE)
E3
CLK
DI
MIPI RFFE / SPI Clock
E4
IDB0
DI
MIPI RFFE ID Bit 0 (Note 3)
1. To be grounded in normal operation.
2. To be grounded when not in use.
3. This pin has to be connected to either GNDIO or VIO level, even if only SPI protocol is used. Never let it float.
Legend: Pad Types
AIH= High Voltage Analog Input
AO= Analog Output
AOH= High Voltage Analog Output
DI= Digital Input
DIO= Digital Input/Output (IO)
P= Power
ELECTRICAL PERFORMANCE SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
Unit
Analog Supply Voltage
−0.3 to +6.0
V
VIO
IO Reference Supply Voltage
−0.3 to +2.5
V
VI/O
Input Voltage Logic Lines (DATA, CLK, CS)
−0.3 to VIO + 0.3
V
−0.3 to 30
V
2,000
V
200
V
−55 to +150
°C
+110
°C
AVDD
V(sub)HVH
Parameter
VHV Maximum Voltage
VESD (HBM)
Human Body Model, JESD22−A114, All I/O
VESD (MM)
Machine Model, JESD22−A115
TSTG
TAMB_OP_MAX
Storage Temperature
Max Operating Ambient Temperature without Damage
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
www.onsemi.com
3
TCC−226
Table 3. RECOMENDED OPERATING CONDITIONS
Rating
Symbol
Parameter
Min
Typ
Max
Unit
TAMB_OP
Operating Ambient Temperature
−30
−
+85
°C
TJ_OP
Operating Junction Temperature
−30
−
+125
°C
AVDD
Analog Supply Voltage
2.3
−
5.5
V
IO Reference Supply Voltage
1.62
−
1.98
V
VIO
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 4. DC CHARACTERISTICS (TA = −30 to +85°C; VOUTX = 15 V for each output; 2.3 V<AVDD< 5.5 V; VIO = 1.8 V; RLOAD =
equivalent series load of 5.6 kW and 2.7 nF; CHV = 22 nF; LBOOST = 15 mH; TRIG pin grounded; unless otherwise specified)
Parameter
Min
Typ
Max
Unit
Comment
AVDD Supply Current
−
−
1.5
mA
VIO Supply is Low
L_BOOST Leakage
−
−
1.5
Battery Current
−
−
2.5
IVIO
VIO Supply Current
−1
−
1
ICLK
CLK Leakage
−1
−
1
IDATA
DATA Leakage
−1
−
1
Average battery current, 3 outputs actively switching 16 V for 1205 ms to 2 V
for 1705 ms to 8 V for 1705 ms and 3
outputs are @ 16 V steady state
−
1,760
2,350
mA
At VHV = 20 V
AVDD = 3.3 V
IBATT_SS0
Average battery current, 6 outputs @
0 V steady state
−
800
1,130
IBAT_SS2
Average battery current, 6 outputs @
2 V steady state
−
850
1,200
IBATT_SS16
Average battery current, 6 outputs @
16 V steady state
−
1,190
1,560
At VHV = 20 V
AVDD = 3.3 V
IL_BOOST
Average inductor current, 3 outputs actively switching 16 V for 1205 ms to 2 V
for 1705 ms to 8 V for 1705 ms and 3
outputs are @ 16 V steady state
−
1,480
2,050
At VHV = 20 V
AVDD = 3.3 V
IL_BOOST_SS0
Average inductor current, 6 outputs @
0 V steady state
−
500
790
At VHV = 20 V
AVDD = 3.3 V
IL_BOOST_SS2
Average inductor current, 6 outputs @
2 V steady state
−
560
850
At VHV = 20 V
AVDD = 3.3 V
IL_BOOST_SS16
Average inductor current, 6 outputs @
16 V steady state
−
930
1,270
At VHV = 20 V
AVDD = 3.3 V
IVIO_INACT
VIO average inactive current
−
−
3
VIO is high, no bus activity
IVIO_ACTIVE
VIO average active current
−
−
250
VIO = 1.8 V, master sending
data at 26 MHz
1.7
−
1.9
Symbol
SHUTDOWN MODE
IAVDD
IL_BOOST
IBATT
ACTIVE MODE
IBATT
VVREG
www.onsemi.com
4
At VHV = 20 V
AVDD = 3.3 V
mA
V
At VHV = 20 V
AVDD = 3.3 V
No external load allowed
TCC−226
Table 4. DC CHARACTERISTICS (TA = −30 to +85°C; VOUTX = 15 V for each output; 2.3 V<AVDD< 5.5 V; VIO = 1.8 V; RLOAD =
equivalent series load of 5.6 kW and 2.7 nF; CHV = 22 nF; LBOOST = 15 mH; TRIG pin grounded; unless otherwise specified)
Symbol
Parameter
Min
Typ
Max
Unit
Comment
AVDD Supply Current
−
−
8
mA
L_BOOST Leakage
−
−
6
Battery Current
−
−
14
IAVDD + IL_BOOST
VIO Supply Current
−
−
3
No bus activity
1.6
−
1.9
LOW POWER MODE
IAVDD
IL_BOOST
IBATT
IVIO
VVREG
V
No external load allowed
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 5. BOOST CONVERTER CHARACTERISTICS
(AVDD from 2.3 V to 5.5 V; VIO = 1.8 V; TA = –30 to +85°C; CHV = 22 nF; LBOOST = 15 mH; unless otherwise specified)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
V
VHV_min
Minimum programmable output voltage (average), DAC Boost = 0h
Active mode
−
13
−
VHV_max
Maximum programmable output voltage (average), DAC Boost = Fh
Active mode
−
28
−
Resolution
Boost voltage resolution
4−bit DAC
−
1
−
−
200
−
IL_BOOST_LIMIT
Inductor current limit
mA
Table 6. ANALOG OUTPUTS (OUT A, OUT B, OUT C, OUT D, OUT E, OUT F)
(AVDD from 2.3 V to 5.5 V; VIO = 1.8 V; VHV = 26 V; TA = –30 to +85°C; Rload = ∞ unless otherwise specified)
Description
Parameter
Min
Typ
Max
Unit
7
−
−
MW
Comment
SHUTDOWN MODE
ZOUT
OUT A, OUT B, OUT C , OUT D,
OUT E,OUT F output impedance
DAC disabled
ACTIVE MODE
VOH
Maximum output voltage
−
23.8
−
V
DAC A, B, C, D, E or F = 7Fh,
DAC Boost = Fh, IOH < 10 mA
VOL
Minimum output voltage
−
−
1
V
DAC A, B C, D, E or F = 01h, DAC
Boost = 0h to Fh, IOH < 10 mA
−
3
10
ms
2 V to 20 V step, measured at
VOUT = 15.2 V,
RLOAD = equivalent series load of
2.7 kW and 5.6 nF, Turbo enabled
OUT A, OUT B, OUT C, OUT D,
OUT E, OUT F set in pull−down
mode
−
−
1000
W
DAC A, B C, D, E or F = 00h, DAC
Boost = 0h to Fh, selected output(s)
is disabled
Voltage resolution (1−bit)
−
188
−
mV
Zero scale, least squared best fit
−1
−
+1
LSB
−3.0
−
+3.0
%VOUT
Over 2 V – 20 V VO range
−0.9
−
+0.9
LSB
Over 2 V – 20 V VO range
Slew Rate
RPD
Resolution
VOFFSET
Error
(1 LSB = 1−bit)
DNL
Differential non−linearity least
squared best fit
INL
Integral non−linearity least squared
best fit
−1
−
+1
LSB
Over 2 V – 20 V VO range
ISC
Over current protection
−
5
65
mA
Any DAC output shorted to ground
Output ripple with all outputs at
steady state
−
−
40
mV RMS
Over 2 V – 20 V for VHV = 23.5 V
VRIPPLE
www.onsemi.com
5
TCC−226
THEORY OF OPERATION
2. Startup Mode: Startup is only a transitory mode.
Startup mode is entered upon a VIO high state. In
startup mode all registers are reset to their default
states, the digital interface is functional, the boost
converter is activated, outputs OUT A, OUT B,
OUT C, OUT D, OUT E and OUT F are disabled
and the DAC outputs are placed in a high Z state.
Control software can request a full hardware and
register reset of the TCC−226 by sending an
appropriate PWR_MODE command to direct the
chip from either the active mode or the low power
mode to the startup mode. From the startup mode
the device automatically proceeds to the active mode.
3. Active Mode: All blocks of the TCC−226 are
activated and the DAC outputs are fully controlled
through the digital interface, DACs remain off
until enabled. The DAC settings can be
dynamically modified and the HV outputs will be
adjusted according to the specified timing
diagrams. Each DAC can be individually
controlled and/or switched off according to
application requirements. Active mode is
automatically entered from the startup mode.
Active mode can also be entered from the low
power mode under control software command.
4. Low Power Mode: In low power mode the serial
interface stays enabled, the DAC outputs are
disabled and are placed in a high Z state and the
boost voltage circuit is disabled. Control software
can request to enter the low power mode from the
active mode by sending an appropriate
PWR_MODE command. The contents of all
registers are maintained in the low power mode.
Overview
The control IC outputs are directly controlled by
programming the six DACs (DAC A, DAC B, DAC C, DAC
D, DAC E and DAC F) through the digital interface.
The DAC stages are driven from a reference voltage,
generating an analog output voltage driving a high−voltage
amplifier supplied from the boost converter (see Figure 1 −
Control IC Functional Block Diagram).
The control IC output voltages are scaled from 0 V to
24 V, with 128 steps of 188 mV ((2 x 24 / 255 V) =
0.188235 V). The nominal control IC output can be
approximated to 188 mV x (DAC value).
For performance optimization the boost output voltage
(VHV) can be programmed to levels between 13 V and 28 V
via the DAC_boost register (4 bits with 1 V steps). The
startup default level for the boosted voltage is VHV = 24 V.
For proper operation and to avoid saturation of the output
devices and noise issues it is recommended to operate the
boosted VHV voltage at least 2 V above the highest
programmed VOUT voltage of any of the six outputs.
Operating Modes
The following operating modes are available:
1. Shutdown Mode: All circuit blocks are off, the
DAC outputs are disabled and placed in high Z
state and current consumption is limited to
minimal leakage current. The shutdown mode is
entered upon initial application of AVDD or upon
VIO being placed in the low state. The contents of
the registers are not maintained in shutdown mode.
Battery insertion
VDDA = 0
VIO = HIGH
Startup
(Registers reset)
Shutdown
PWR_MODE =
0b01
VIO = LOW
PWR_MODE =
0b01
VIO = LOW
automatic
Low Power
(User Defined)
PWR_MODE = 0b00
PWR_MODE = 0b10
Figure 3. Modes of Operation
www.onsemi.com
6
Active
(User Defined)
TCC−226
AVDD Power−On Reset (POR)
VIO Power−On Reset and Startup Conditions
Upon application of AVDD the TCC−226 will be in
shutdown mode. All circuit blocks are off and the chip draws
only minimal leakage current.
A high level on VIO places the chip in startup mode which
provides a POR to the TCC−226. POR resets all registers to
their default settings as described in Table 8. VIO POR also
resets the serial interface circuitry. POR is not a brown−out
detector and VIO needs to be brought back to a low level to
enable the POR to trigger again.
Table 7. VIO POWER−ON RESET AND STARTUP
Register
Default State for
VIO POR
DAC Boost
[1011]
Power Mode
[01]>[00]
Transitions from shutdown to startup and then automatically to active mode
DAC Enable
[000000]
VOUT A, B, C, D, E and F Disabled
Comment
VHV = 24 V
DAC A
Output in High−Z Mode
DAC B
Output in High−Z Mode
DAC C
Output in High−Z Mode
DAC D
Output in High−Z Mode
DAC E
Output in High−Z Mode
DAC F
Output in High−Z Mode
VIO Shutdown
A low level at any time on VIO places the chip in shutdown mode in which all circuit blocks are off. The contents of the
registers are not maintained in shutdown mode.
Table 8. VIO THRESHOLDS (AVDD from 2.3 V to 5.5 V; TA = –30 to +85°C unless otherwise specified)
Parameter
Description
Min
Typ
Max
Unit
VIORST
VIO Low Threshold
−
−
0.2
V
Comments
When VIO is lowered below this threshold level the
chip is reset and placed into the shutdown state
Power Supply Sequencing
The AVDD input is typically directly supplied from the battery and thus is the first on. After AVDD is applied and before VIO
is applied to the chip, all circuits are in the shutdown state and draw minimum leakage currents. Upon application of VIO, the
chip automatically starts up using default settings and is placed in the active state waiting for a command via the serial interface.
Table 9. TIMING (AVDD from 2.3 V to 5.5 V; VIO = 1.8 V; TA = –30 to +85°C; OUT A, OUT B, OUT C, OUT D, OUT E & OUT F; CHV =
22 nF; LBOOST = 15 mH; VHV = 20 V; Turbo−Charge mode off unless otherwise specified)
Parameter
Description
Min
Typ
Max
Unit
Comments
TPOR_VREG
Internal bias settling time from shutdown to active mode
Time to charge CHV @ 95% of set VHV
−
50
120
ms
For info only
−
130
−
ms
For info only
Startup time from shutdown to active mode
−
180
300
ms
TSET+
Output A, B, C, D, E, F positive settling time to within
5% of the delta voltage, equivalent series load of
5.6 kW and 2.7 nF, VOUT from 2 V to 20 V; 0Bh (11d)
to 55h (85d)
−
50
60
ms
Voltage settling time
connected on VOUT
A, B, C, D, E, F
TSET−
Output A, B, C, D, E, F negative settling time to within
5% of the delta voltage, equivalent series load of
5.6 kW and 2.7 nF, VOUT from 20 V to 2 V; 55h (85d)
to 0Bh (11d)
−
50
60
ms
Voltage settling time
connected on VOUT
A, B, C, D, E, F
TSET+
Output A, B, C, D, E, F positive settling time with Turbo
−
35
−
ms
Voltage settling time
connected on VOUT
A, B, C, D, E, F
TSET−
Output A, B, C, D, E, F negative settling time with Turbo
−
35
−
ms
Voltage settling time
connected on VOUT
A, B, C, D, E, F
TBOOST_START
TSD_TO_ACT
www.onsemi.com
7
TCC−226
Figure 4. Output Settling Diagram
Figure 5. Startup Timing Diagram
www.onsemi.com
8
TCC−226
Boost Control
Due to the slow response time of the control loop, the
VHV voltage may drop below the set voltage before the
control loop compensates for it. In the same manner, VHV
can rise higher than the set value. This effect may reduce the
maximum output voltage available. Please refer to Figure 7
below.
The asynchronous control reduces switching losses and
improves the output (VHV) regulation of the DC/DC
converter under light load, particularly in the situation
where the TCC−226 only maintains the output voltages to
fixed values.
The TCC−226 integrates an asynchronous current control
boost converter. It operates in a discontinuous mode and
features spread−spectrum circuitry for Electro−Magnetic
Interference (EMI) reduction. The average boost clock is
2 MHz and the clock is spread between 0.8 MHz and 4 MHz.
Boost Output Voltage (VHV) Control Principle
The asynchronous control starts the boost converter as
soon as the VHV voltage drops below the reference set by
the 4−bit DAC and stops the boost converter when the VHV
voltage rises above the reference again.
CHV
Recharge
Set
VHV
CHV
Discharge
Delay
Delay
VHV
Delay
Time
Boost
Running
Figure 6. VHV Voltage Waveform
High Impedance (High Z) Feature
In shutdown mode the OUT pins are set to a high
impedance mode (high Z). Following is the principle of
operation for the control IC:
1. The DAC output voltage VOUT is defined by:
V OUT +
DAC code
255
24 V
2
(eq. 1)
2. The voltage VHV defines the maximum supply
voltage of the DAC supply output regulator and is
set by a 4−bit control.
3. The maximum DAC DC output voltage VOUT is
limited to (VHV – 2 V).
4. The minimum output DAC voltage VOUT is 1.0 V
max.
Figure 8. DAC Output Range Example B
Digital Interface
The control IC is fully controlled through a digital
interface (DATA, CLK, CS). The digital interface auto−
matically detects and responds to MIPI RFFE interface
commands, 3−wire 30−bit serial interface commands or
3−wire 32−bit serial interface commands. Auto−detection is
accomplished on a frame by frame basis. The digital
interface is described in the following sections of this
document, for detailed programming instructions please
refer to the programming guide, available by contacting
ON Semiconductor.
3−Wire Serial Interface
The 3−wire serial interface operates in a synchronous
write−only 3−wire slave mode. 30−bit or 32−bit message
length is automatically detected for each frame. If CS
changes state before all bits are received then all data bits are
ignored. Data is transmitted most significant bit first and
DATA is latched on the rising edge of CLK. Commands are
latched on the falling edge of CS.
Figure 7. DAC Output Range Example A
www.onsemi.com
9
TCC−226
Table 10. 3−WIRE SERIAL INTERFACE SPECIFICATION
(TA = −30 to +85°C; 2.3 V < AVDD < 5.5 V; VIO = 1.8 V; unless otherwise specified)
Parameter
Description
Min
Typ
Max
Unit
−
−
26
MHz
FCLK
Clock Frequency
TCLK
Clock Period
38.4
−
−
ns
NBIT
Bits Number
−
30/32
−
bits
Comments
Auto−detection 30−bit or
32−bit
THIGH
Clock High Time
13
−
−
ns
TLOW
Clock Low Time
13
−
−
ns
TCSSETUP
CS Set−up Time
5
−
−
ns
70% rising edge of CS to
30% rising edge of first
clock cycle
TCSHOLD
CS Hold Time
5
−
−
ns
30% falling edge of last
clock cycle to 70% falling
edge of CS
TDSETUP
Data Set−up Time
4
−
−
ns
Relative to 30% of CLK
rising edge
TDHOLD
Data Hold Time
4
−
−
ns
relative to 70% of CLK rising edge
TSUCC
CS Low Time Between
Successive Writes
38.4
−
−
ns
70% falling edge of CS to
70% rising edge of CS
TSUCC
CS Low Time Between
Successive DAC Update Writes
1,500
−
−
ns
Time between groups of
DAC update reg [00000] &
[00001] writes
CCLK
Input Capacitance
−
−
5
pF
CLK pin
CDATA
Input Capacitance
−
−
8.3
pF
DATA pin
CCS
Input Capacitance
−
−
5
pF
CS pin
CTRIG
Input Capacitance
−
−
10
pF
TRIG pin
V
DATA, CLK, CS
VIH
Input Logic Level High
0.7 x VIO
−
VIO x 0.3
VIL
Input Logic Level Low
−0.3
−
0.3 x VIO
V
DATA, CLK, CS
IIH_DATA
Input Current High
−2
−
10
mA
DATA
IIL_DATA
Input Current Low
−2
−
1
mA
DATA
IIH_CLK,CS
Input Current High
−1
−
10
mA
CLK, CS
IIL_CLK,CS
Input Current Low
−1
−
1
mA
CLK, CS
VTP_TRIG
Positive Going Threshold Voltage
0.4 x VIO
−
0.7 x VIO
V
TRIG
VTN_TRIG
Negative Going Threshold Voltage
0.3 x VIO
−
0.6 x VIO
V
TRIG
VH_TRIG
Hysteresis Voltage (VTP – VTN)
0.1 x VIO
−
0.4 x VIO
V
TRIG
IIH_TRIG
TRIG Input Current High
−2
−
10
mA
TRIG=0.8 x VIO
IIL_TRIG
TRIG Input Current Low
−2
−
1
mA
TRIG=0.2 x VIO
www.onsemi.com
10
TCC−226
Figure 9. 3−wire Serial Interface Signal Timing
SPI Frame Length Decoding
rising edges while CS is kept high. The TCC−226 will not
respond to a SPI command if the length of the frame is not
exactly 30 bits or 32 bits. SPI registers are write only.
30−bit or 32−bit frame length is automatically detected.
The length of the frame is defined by the number of clock
SPI Frame Structure
Table 11. 32 BITS FRAME: ADDRESS DECODING (1, 2, 3, 4, 5 or 6 OUTPUTS)
H0
H1
1
1
ON Semiconductor Header
R/W
A12
0
1
R/W
A11
A10
A9
0
1
0
Device ID
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
1
0
0
X
X
X
X
X
Specific Device ID
Register Address for Operation
Table 12. 30 BITS FRAME: ADDRESS DECODING (1, 2, 3, 4, 5 or 6 OUTPUTS)
R/W
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
1
0
1
0
0
1
0
0
X
X
X
X
X
R/W
Device ID
Specific Device ID
Register Address for Operation
Table 13. 3−WIRE SERIAL INTERFACE ADDRESS MAP
A4
A3
A2
A1
A0
Data[15:8]
Data[7:0]
0
0
0
0
0
Turbo−Charge Settings for DAC A, B, C
DAC C
0
0
0
0
1
DAC B
DAC A
0
0
0
1
0
Turbo−Charge Settings for DAC D, E, F
DAC F
0
0
0
1
1
DAC E
DAC D
0
0
1
0
0
Turbo−Charge Delay Parameters for DAC A, B, C
Turbo Threshold Delay Settings for A, B, C
0
0
1
0
1
Turbo−Charge Delay Parameters for DAC D, E, F
Turbo Threshold Delay Settings for A, B, C
1
0
0
0
0
1
0
0
1
0
1
1
Mode Select + Control IC Setup
Reserved
to
1
1
1
www.onsemi.com
11
Reserved
TCC−226
Turbo−Charge Mode
The TCC−226 control IC has a Turbo−Charge mode that
significantly shortens the system settling time when
changing programming voltages. In Turbo−Charge mode
the DAC output target voltage is temporarily set to either a
delta voltage above or a delta voltage below the actual
desired target for the TCDLY time. It is recommended that
VHV be set to 26 V when using Turbo−Charge mode.
During glide mode the output voltage of a DAC is either
increased or decreased to its set end point, in max 255 steps,
where each DAC time step can be programmed between
2 ms to 64 ms. For programming the glide mode refer to the
application note (coming soon). A programming input is not
required to maintain a glide transition, all step controls are
maintained by the part. Only the inputs to define the glide
need to be programmed.
Glide Mode
RF Front−End Control Interface (MIPI RFFE Interface)
Unlike turbo mode, which is intended to reduce the
charging time, the glide mode extends the transition time of
each DAC output. Each DAC has an individual control for
turbo mode, glide mode or regular voltage switching. The
glide mode can be enabled for a particular DAC through the
INDEX register, by setting DAC State to ‘1’ when glide
mode is enabled, turbo mode is off for a particular DAC, but
one DAC can be gliding while the other is turbo.
The TCC−226 is a read/write slave device which is fully
compliant to the MIPI Alliance Specification for RF
Front−End Control Interface (RFFE) Version 1.10.00 26
July 2011. This device is rated at full−speed operation for
1.65 V<VIO<1.95 V and at half−speed operation for
1.1 V<VIO<1.65 V. When using the MIPI RFFE interface
the CS pin must be grounded externally.
CLK
TDSETUP
TDSETUP
TDHOLD
TDHOLD
DATA
Figure 10. MIPI−RFFE Signal Timing during Master Writes to PTIC Control IC
CLK
TREAD_ACCESS
TSDATAOTR
CLK
TREAD_ACCESS
TSDATAZ
TSDATAOTR
DATA
DATA
Bus Park Cycle
Figure 11. MIPI−RFFE Signal Timing during Master
Reads from PTIC Control IC
www.onsemi.com
12
Figure 12. Bus Park Cycle Timing
when MIPI−RFFE Master Reads
from PTIC Control IC
TCC−226
Table 14. MIPI RFFE INTERFACE SPECIFICATION
(TA = −30 to +85°C; 2.3 V < AVDD < 5.5 V; 1.1 V < VIO < 1.8 V; unless otherwise specified)
Parameter
Min
Typ
Max
Unit
FSCLK
Clock Full−Speed
Frequency
Description
0.032
−
26
MHz
Full−Speed Operation:
1.65 V < VIO < 1.95 V
Comments
TSCLK
Clock Full−Speed Period
0.038
−
32
ms
Full−Speed Operation:
1.65 V < VIO < 1.95 V
TSCLKIH
CLK Input High Time
11.25
−
−
ns
Full−Speed
TSCLKIL
CLK Input Low Time
11.25
−
−
ns
Full−Speed
VTP
Positive Going Threshold
Voltage
0.4 x VIO
−
0.7 x VIO
V
CLK, DATA, TRIG, 1.2 or 1.8 V Bus
VTN
Negative Going Threshold Voltage
0.3 x VIO
−
0.6 x VIO
V
CLK, DATA, TRIG, 1.2 or 1.8 V Bus
VH
Hysteresis Voltage
(VTP – VTN)
0.1 x VIO
−
0.4 x VIO
V
CLK, DATA, TRIG, 1.2 or 1.8 V Bus
IIH
Input Current High
−2
−
+10
mA
TRIG,SDATA = 0.8 x VIO
−1
−
+10
mA
SCLK = 0.8 x VIO
−2
−
+1
mA
TRIG,SDATA = 0.2 x VIO
−1
−
+1
mA
SCLK = 0.2 x VIO
IIL
Input Current Low
CCLK
Input Capacitance
−
−
5
pF
CLK Pin
CDATA
Input Capacitance
−
−
8.3
pF
DATA Pin
CTRIG
Input Capacitance
−
−
10
pF
TRIG Pin
TDSETUP
Write DATA Setup Time
−
−
1
ns
Full−Speed
TDHOLD
Write DATA Hold Time
−
−
5
ns
Full−Speed
TREAD_ACCESS
Read DATA valid from
CLK rising edge
−
−
7.11
ns
Full Speed at VIO = 1.80 V, +25°C,
and max 15 pF load on DATA pin
TREAD_ACCESS
Read DATA valid from
CLK rising edge
−
−
9.11
ns
Full Speed at VIO = 1.80 V, +25°C,
and max 50 pF load on DATA pin
www.onsemi.com
13
TCC−226
The control IC contains twenty−four 8−bit registers. Register content is described in Table 15. Some additional registers
implemented as provision, are not described in this document.
Table 15. MIPI RFFE ADDRESS MAP
Register
Address
Description
Purpose
Access
Type
Size (bits)
Write Reg0
7
0x00
DAC Configuration (Enable Mask)
High voltage output enable mask
0x01
Turbo Register DAC A, B & C
Turbo−charge configuration DAC A, B & C
Write
8
0x02
DAC A Register
OUT A value [6:0], Turbo Index [7]**
Write
8
0x03
DAC B Register
OUT B value [6:0], Turbo Index [7]**
Write
8
0x04
DAC C Register
OUT C value [6:0], Turbo Index [7]**
Write
8
0x05
Turbo Register DAC D, E & F
Turbo−charge configuration DAC D,E & F
Write
8
0x06
DAC D Register
OUT D value [6:0], Turbo Index [7]**
Write
8
0x07
DAC E Register
OUT E value [6:0], Turbo Index [7]**
Write
8
0x08
DAC F Register
OUT F value [6:0], Turbo Index [7]**
Write
8
0x09
Wake Up
Wake Up Controls
Write
8
0x10
DAC Boost (VHV)
Settings for the boost high voltage
Write
8
0x11
Trigger register
Trigger configuration
Write
8
0x12
Turbo−Charge Delay DAC A, B, C
Turbo−charge delay steps
DAC A, B, C
Write
8
0x13
Turbo−Charge Delay DAC A, B, C
Turbo−charge delay, multiplication
DAC A, B, C
Write
8
0X14
Turbo−Charge Delay DAC D, E, F
Turbo−charge delay steps
DAC D, E, F
Write
8
0X15
Turbo−Charge Delay DAC D, E, F
Turbo−charge delay multiplication
DAC D, E, F
Write
8
0x1A
RFFE_STATUS
RFFE status register
Read/Write
8
0x1B
RFFE_GROUP_SID
Read/Write
8
0x1C
Power Mode and Trigger Register
Power mode & trigger control
PWR_MODE [7:6]
TRIG_REG [5:0]
Read/Write
8
0x1D
Product ID Register
Product number *
Hard coded into ASIC
Read
8
0x1E
Manufacturer ID Register
MN (10 bits long)
Manufacturer ID[7:0]
Hard Coded into ASIC
Read
8
0x1F
Unique Slave Identifier Register (USID)
Spare [7:6]
[5,4] = Manufacturer ID [9:8]
USID [3:0]
Read/Write
8
0x2C
Glide Timer Settings
[6:5] Turbo and glide control / [4:0] Glide timer
setting / Need extended write for this register
Write
8
*The second least significant bit can be programmed in OTP during manufacture
** The details for configuration of Turbo mode should be ascertained from the Programming Guide, available from ON Semiconductor
Configuration Settings
Table 16. DAC CONFIGURATION (ENABLE MASK) at [0x00] Defaults shown as (x)
Bit 6 (1)
Bit 5 (0)
Bit 4 (0)
Bit 3 (0)
Bit 2 (0)
Bit 1 (0)
Bit 0 (0)
SSE
DAC E
DAC F
DAC A
DAC B
DAC C
DAC D
SSE = 0 spread spectrum disabled, SSE = 1 spread spectrum enabled (default), this controls the average boost clock which
is nominally 2 MHz and spread between 0.8 MHz and 3.2 MHz when enabled (default). The hardware does not limit driving
more than three DACs at the same time, however it is recommended to have max three DACs changing outputs at one time,
no restrictions exist as to which three.
www.onsemi.com
14
TCC−226
Table 17. DAC MODE SETUP: DAC ENABLE
Bit3
Bit2
Bit1
DAC A
DAC B
DAC C
0
0
0
Off
Off
Off
0
0
1
Off
Off
Enabled
0
1
0
Off
Enabled
Off
0
1
1
Off
Enabled
Enabled
1
0
0
Enabled
Off
Off
1
0
1
Enabled
Off
Enabled
1
1
0
Enabled
Enabled
Off
1
1
1
Enabled
Enabled
Enabled
DAC D
(Default)
Table 18. DAC MODE SETUP: DAC ENABLE
Bit5
Bit4
Bit0
DAC E
DAC F
0
0
0
Off
Off
Off
0
0
1
Off
Off
Enabled
0
1
0
Off
Enabled
Off
0
1
1
Off
Enabled
Enabled
1
0
0
Enabled
Off
Off
1
0
1
Enabled
Off
Enabled
1
1
0
Enabled
Enabled
Off
1
1
1
Enabled
Enabled
Enabled
(Default)
Table 19. BOOST DAC MODE SETUP (VHV) at [0x10] (Notes 4 and 5)
Bit 7*
Bit 6*
Bit 5*
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VHV (V)
0
0
0
1
0
0
0
0
13
0
0
0
1
0
0
0
1
14
0
0
0
1
0
0
1
0
15
0
0
0
1
0
0
1
1
16
0
0
0
1
0
1
0
0
17
0
0
0
1
0
1
0
1
18
0
0
0
1
0
1
1
0
19
0
0
0
1
0
1
1
1
20
0
0
0
1
1
0
0
0
21
0
0
0
1
1
0
0
1
22
0
0
0
1
1
0
1
0
23
0
0
0
1
1
0
1
1
24 (Default)
0
0
0
1
1
1
0
0
25
0
0
0
1
1
1
0
1
26
0
0
0
1
1
1
1
0
27
0
0
0
1
1
1
1
1
28
*Indicates reserved bits
4. Bit 4 is fixed at logic 1 for reverse software compatibility
5. VHV is recommended to be set at VDac Max + 2 V for non−turbo operation and +4 when turbo is used.* Indicates reserved bits.
www.onsemi.com
15
TCC−226
MIPI RFFE TRIG Operation
improve interfacing options the polarity of external TRIG is
programmable via [0x11] bit 1.
If the external trigger function is not needed in the
application, the TRIG pin should be grounded and the TRIG
function disabled. When TRIG pin is disabled by register
[0x11] ‘TRIG Select’ = ‘1’ (default) and register [0x10]
‘Trigger Mask 0, 1, 2’ = ‘1’:
• The requested DAC voltage levels for DAC A, B, C are
applied to the outputs all together at the same time,
after DAC C value is written. This event will not affect
the outputs of DAC D, E, F.
• The requested DAC voltage levels for DAC D, E, F are
applied to the outputs all together at the same time,
after DAC F value is written. This event will not affect
the outputs of DAC A, B, C.
• Optionally a configuration register can select the last
DAC to be written in order to trigger internally the
update of all six DACs at the same time. For example
the configuration register can select that a write to DAC
B value will trigger internally the update of all six
DACs outputs.
The MIPI RFFE Trigger mode can be used as a
synchronization signal to ensure that new DAC settings are
applied to the outputs at appropriate times in the overall
transceiver system. When the MIPI RFFE TRIG function is
enabled via [0x11] bit 4 the requested DAC voltage levels
are set up in the shadow registers and not transferred to the
destination registers until the trigger condition is met. In this
manner the change in output voltage levels are synchronized
with the MIPI RFFE TRIG command. If multiple DAC
voltage level requests are received before the TRIG event
occurs, only the last fully received DAC output voltage level
will be applied to the outputs.
The trigger configuration also provides for an additional
external TRIG pin to be used as a synchronization signal.
The external TRIG is independent from the built−in triggers
available within the MIPI RFFE interface. When the TRIG
input pin is enabled via [0x11] bit 4 the requested DAC
voltage levels are set up in the shadow registers and are not
transferred to the destination registers until the external
trigger condition is met. In this manner the change in output
voltage levels are synchronized with the external TRIG
event. The external TRIG input is referenced to VIO. To
Table 20. TRIGGER CONFIGURATION at [0x11]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Res*
0
Res*
0
Res*
0
TRIG Select
0 = Ext TRIG Pin
1 = RFFE Trigger
Bit 2
Reserved
0
Bit 1
Bit 0
TRIG Edge
0 = Active Falling
1 = Active Rising
Mask Ext TRIG
1 = Mask Trig Pin
*Reserved bits
Table 21. EXTERNAL TRIGGER CONFIGURATION BIT SETTING AT [0x11]
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Description
0
−
−
X
0
External trigger pin is enabled. Sending the RFFE message will load a ‘shadow’
register only. Only upon an active signal on external TRIG pin are the output registers loaded with the new voltage settings which are then applied to the outputs.
1
−
−
X
X
The MIPI RFFE trigger is enabled (Default)
0
−
−
0
0
External TRIG pin signal is active falling
0
−
−
1
0
External TRIG pin signal is active rising (Default)
X
−
−
X
0
External trigger pin is not masked
X
−
−
X
1
Mask external trigger pin (Default)
Table 22. POWER MODE AND TRIGGER REGISTER [0x1C]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PM1
PM0
Trigger Mask 2
Trigger Mask 1
Trigger Mask 0
Trigger 2
Trigger 1
Trigger 0
Writing a logic one (‘1’) to the bits 0, 1 or 2 (Trigger 0, 1
or 2) moves data from the shadow registers into the
destination registers. Default for bit 0, 1 and 2 is logic low.
If trigger mask bit 0, 1 or 2 is set (‘1’) the trigger 0, 1 or
2 are disabled respectively and the data goes directly to the
destination register. Default for bit 3, 4 and 5 is logic low.
All three triggers behave in the same way as the external
pin TRIG. When each of these triggers is set using the MIPI
RFFE interface the results are the same as when an active
edge is applied to the TRIG pin when external pin TRIG is
selected
www.onsemi.com
16
TCC−226
Table 23. POWER MODE BIT SETTING IN REGISTER [0x1C]
PM1
PM0
State
Description
0
0
Active
Boost Control Active, VHV set by Digital Interface
VOUT A, B, C, D, E, F Enabled and Controlled by Digital Interface (Default)
0
1
Startup
Boost Control Active, VHV set by Digital Interface
VOUT A, B, C, D, E, F Disabled
1
0
Low Power
1
1
Reserved
Digital Interface is Active While All Other Circuits are in Low Power Mode
State of Hardware Does Not Change
Command Sequences
Register 0 Write Command Sequence
• Register 0 Write (used to access the Register 0 DAC
•
•
The Command Sequence starts with a Sequence Start
Condition (SSC) which is followed by the Register 0 Write
Command Frame. This Frame contains the Slave address, a
logic one, and the seven bit word that will be written to
Register 0. The Command Sequence is depicted below.
Configuration − Enable Mask). Register 0 can be also
be accessed using Register Write or/and Extended
Register Write.
Register Write (used to access only one register at the
time)
Extended Register Write (used to access a group of
contiguous registers with one command)
Figure 13. Register 0 Write Command Sequence
Table 24. MIPI RFFE COMMAND FRAME FOR REGISTER 0 WRITE COMMAND SEQUENCE
Description
SSC
SSE & DAC
Configuration
1
0
Command Frame
SA [3,0]
1
SSE
DAC_E
DAC_F
www.onsemi.com
17
DAC_A
BP
DAC_B
DAC_C
DAC_D
P
BP
TCC−226
Register Write Command Sequence
The write register command sequence may be used to access each register (addresses 0−31).
Figure 14. Register Write Command Sequence
Table 25. MIPI RFFE COMMAND FRAME FOR REGISTER WRITE COMMAND SENTENCE
Description
SSC
Command Frame
Data Frame
BP
Turbo−Charge
Settings
1
0
SA
[3,0]
0
1
0
0
0
0
0
1
P
TC_INDX_L [7:0]
P
BP
Register Write
DAC A
1
0
SA
[3,0]
0
1
0
0
0
0
1
0
P
TC_INDX_L [8] & DAC_A
[6:0]
P
BP
Register Write
DAC B
1
0
SA
[3,0]
0
1
0
0
0
0
1
1
P
TC_INDX_L [9] & DAC_B
[6:0]
P
BP
Register Write
DAC C
1
0
SA
[3,0]
0
1
0
0
0
1
0
0
P
TC_INDX_L [10] & DAC_C
[6:0]
P
BP
Table 26. MIPI RFFE COMMAND FRAME FOR REGISTER WRITE COMMAND SENTENCE
Description
SSC
Command Frame
Data Frame
BP
Turbo−Charge
Settings
1
0
SA
[3,0]
0
1
0
0
0
1
0
1
P
TC_INDX_U [7:0]
P
BP
Register Write
DAC D
1
0
SA
[3,0]
0
1
0
0
0
1
1
0
P
TC_INDX_U [8] & DAC_D
[6:0]
P
BP
Register Write
DAC E
1
0
SA
[3,0]
0
1
0
0
0
1
1
1
P
TC_INDX_U [9] & DAC_E
[6:0]
P
BP
Register Write
DAC F
1
0
SA
[3,0]
0
1
0
0
1
0
0
0
P
TC_INDX_U [10] & DAC_F
[6:0]
P
BP
www.onsemi.com
18
TCC−226
Extended Register Write Command Sequence
If more than one byte is to be written, the register address
in the command sequence contains the address of the first
extended register that will be written to and the slave’s local
extended register address shall be automatically
incremented by one for each byte written up to address 0x1F,
starting from the address indicated in the address frame.
In order to access more than one register in one sequence
this message could be used. Most commonly it will be used
for loading three DAC registers at the same time. The four
LSBs of the extended register write command frame
determine the number of bytes that will be written by the
command sequence. A value of 0b0000 would write one
byte and a value of 0b1111 would write 16 bytes.
Figure 15. Extended Register Write Command Sequence
www.onsemi.com
19
TCC−226
Table 27. EXTENDED REGISTER WRITE TO UPDATE DAC A, B, C (Note 6)
Description
Extended Register
Write TC_INDX_L
and DAC A, B, C
SSC
Command Frame
Op Code
1
0
SA [3,0]
Data Frame
0
0
0
Address Frame
<Byte Count>
0
0
0
Data Frame
1
P
1
<Starting Address>
P
0
0
0
Data Frame
0
0
P
0
0
1
Data Frame
P
BP
<Data 8−bit>
P
<Data 8−bit>
P
<Data 8−bit>
P
<Data 8−bit>
P
BP
Turbo−Charge
P
DAC_A [7,0]
P
DAC_B [7,0]
P
DAC_C [7,0]
P
BP
Table 28. EXTENDED REGISTER WRITE TO UPDATE DAC D, E, F (Note 6)
Description
Extended Register
Write TC_INDX_U
and DAC D, E, F
SSC
Command Frame
Op Code
1
0
SA [3,0]
Data Frame
0
0
0
Address Frame
<Byte Count>
0
0
0
Data Frame
1
P
1
<Starting Address>
P
0
0
0
Data Frame
0
0
P
1
0
1
Data Frame
P
BP
<Data 8−bit>
P
<Data 8−bit>
P
<Data 8−bit>
P
<Data 8−bit>
P
BP
Turbo−Charge
P
DAC_D [7,0]
P
DAC_E [7,0]
P
DAC_F [7,0]
P
BP
6. The six DACs can be updated either all together in the same time by using one Extended Register Write command of 8 bytes, or separately
by using two Extended Register Write commands of 4 bytes each, where one command is to update DAC A, B, C and the other command
to update DAC D, E, F.
Figure 16. Register Read Command Sequence
Table 29. REGISTER READ COMMAND
Description
Read
MIPI−RFFE
Status Register
SSC
1
Command Frame
0
SA[3:0]
0
1
Description
Read
MIPI−RFFE
Status Register
(Continued)
1
1
1
0
1
0
P
BP
Data Frame
0
CFPE
CLE
AFPE
DFPE
www.onsemi.com
20
RURE
WURE
BGE
BP
TCC−226
REGISTER DETAILS
Register RFFE:
RFFE_REG_0x00
Address RFFE A[4:0]:
0x00
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
Bits
Reset
6
5
4
3
2
1
0
SS Enable
DAC E
DAC F
DAC A
(1)
DAC B
(1)
DAC C
(1)
DAC D
W−1
W−0
W−0
W−0
W−0
W−0
W−0
(1) When any of the bits [3:1] are written with ‘0’, the corresponding DAC is disabled, but the Turbo−Charge
process which is already started, will not be stopped.
(2) If all bits [3:1] are ‘0’, then incoming DAC messages will be ignored, until at least one of [3:1] is set ‘1’.
Bit 6: Spread Spectrum enable
0: SS disabled
1: SS enabled
Bit [1]: Control DAC E
0: off (default)
1: enabled
Bit [1]: Control DAC F
0: off (default)
1: enabled
Bit [3]: Control DAC A
0: off (default)
1: enabled
Bit [2]: Control DAC B
0: off (default)
1: enabled
Bit [1]: Control DAC C
0: off (default)
1: enabled
Bit [1]: Control DAC D
0: off (default)
1: enabled
Register RFFE:
RFFE_REG_0x01
Address RFFE A[4:0]:
0x01
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
7
6
5
4
Bits
Reset
Register RFFE:
3
2
1
0
W−0
W−0
W−0
TC_INDX_L[7:0]
W−0
W−0
W−0
W−0
W−0
RFFE_REG_0x02
Address RFFE A[4:0]:
0x02
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
7
Bits
Reset
6
5
4
TC_INDX_L
[8]
W−0
3
2
1
0
W−0
W−0
W−0
DAC A value [6:0]
W−0
W−0
W−0
www.onsemi.com
21
W−0
TCC−226
RFFE_REG_0x03
Register RFFE:
0x03
Address RFFE A[4:0]:
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
7
Bits
6
5
4
TC_INDX_L [9]
Reset
W−0
Register RFFE:
3
2
1
0
W−0
W−0
W−0
DAC B value [6:0]
W−0
W−0
W−0
W−0
RFFE_REG_0x04
Address RFFE A[4:0]:
0x04
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
7
6
5
4
3
TC_INDX_L
[10]
Bits
Reset
W−0
Register RFFE:
2
1
0
W−0
W−0
W−0
DAC C value [6:0]
W−0
W−0
W−0
W−0
RFFE_REG_0x05
Address RFFE A[4:0]:
0x05
(1) Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
7
6
5
4
3
Bits
2
1
0
W−0
W−0
W−0
TC_INDX_U[7:0]
Reset
W−0
Register RFFE:
W−0
W−0
W−0
W−0
RFFE_REG_0x06
Address RFFE A[4:0]:
0x06
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
7
Bits
6
5
4
3
TC_INDX_U
[8]
Reset
W−0
Register RFFE:
2
1
0
W−0
W−0
W−0
DAC D value [6:0]
W−0
W−0
W−0
W−0
RFFE_REG_0x07
Address RFFE A[4:0]:
0x07
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
7
Bits
6
5
4
TC_INDX_U [9]
Reset
Register RFFE:
W−0
3
2
1
0
W−0
W−0
W−0
DAC E value [6:0]
W−0
W−0
W−0
W−0
RFFE_REG_0x08
Address RFFE A[4:0]:
0x08
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
7
Bits
Reset
6
5
4
TC_INDX_U
[10]
W-0
3
2
1
0
W−0
W−0
W−0
DAC F value [6:0]
W−0
W−0
W−0
W−0
www.onsemi.com
22
TCC−226
Register RFFE:
RFFE_REG_0x9
Address RFFE A[4:0]:
0x09
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
7
Bits
6
HW Wake-Up Polarity
Reset
W−0
W-1
5
HW Wake−
Up Disable
W−0
4
3
DAC_WAKEUP_CTRL
W−0
W−0
1.
−
−
2
1
0
Turbo Latency
Select
Reserved
boost_en_fast_st
(OTP duplicated) (2)
W−0
W−0
W−0
Changing RFFE_REG_0x09 bits [7:5] while chip is in LP STD mode does not have effect, until chip
returns to ACTIVE mode because bits [7:5] are shadowed when entering LP STD mode.
2. boost_en_fast_st can be set in ACTIVE or in LP mode
Bit [7:6]: HW Wake−Up Polarity
00: HW Wake−Up is always active LOW
01: (default) HW Wake−Up is always active HIGH
10: HW Wake−Up has inverted polarity referred to TRIG pin:
a. when RFFE_REG_0x11/TRIG_SEL = 1, HW Wake−Up is always active LOW
b. when RFFE_REG_0x11/TRIG_SEL = 0, HW Wake−Up is:
i.
active LOW if RFFE_REG_0x11/TRIG_EDGE = 0 ii.
active HIGH if
RFFE_REG_0x11/TRIG_EDGE = 1
11: HW Wake−Up has same polarity as TRIG pin:
a. when RFFE_REG_0x11/TRIG_SEL = 1, HW Wake−Up is always active HIGH
b. when RFFE_REG_0x11/TRIG_SEL = 0, HW Wake−Up is:
i.
active HIGH if RFFE_REG_0x11/TRIG_EDGE = 0
ii.
active LOW if RFFE_REG_0x11/TRIG_EDGE = 1
Bit [5]: HW Wake−Up Disable
0 : (default) HW Wake−Up is enabled
1: HW Wake−up is disabled
Bit [4:3]: DAC Wake−up Control applicable to Wake−up from LP
00: (default) Don’t apply Turbo when Wake−up from LP
01: Always apply Turbo UP when Wake−up from LP. Turbo UP is calculated based on DAC value
prior to enter
LP STD mode.
10: Apply Turbo UP when Wake−up from LP when HW Wake−up is applied, but don’t apply Turbo
UP when
SW Wake−up is applied
11: unused
NOTE 1: Turbo i s NOT appl i ed after Wake−up to the DACs whi ch are programmed with 0x00 in
the DAC value register
NOTE 2: When Bi t[4:3] = ‘10’ or ‘01’, then Turbo i s appl i ed after Wake−up regardl ess if:
DAC values are updated or not
l ast DAC val ue update i s equal wi th ol d DAC val ue
NOTE 3: When RFFE_REG_0x31 / Wake−up DAC Ctrl i s ‘0’ (default) Turbo after Wake−Up i s
appl i ed after fi rst vhv_too_low fal ling edge is detected. When RFFE_REG_0x31 / Wake−up DAC
Ctrl i s ‘1’ Turbo after Wake−up i s appl i ed after rc_clk starts.
Bit [2]: Turbo UP latency Select when Wake−up from LP.
This field has no effect when DAC_WAKEUP_CTRL[1:0] = ‘00’
0 : (default) Turbo UP latency is 50us
1: Turbo UP latency is 100us
Bit [1]: Fast Transition to Active Mode Enable
0: (default) Slow, current as low as possible in LP mode
1 Fast, RC oscillator and bandgap stay on, refer to section 5.6.2.4.2
Bit [0]: Boost Fast Startup Enable
0: (default) Startup with selected boost_il_trim
1: Startup with boost_il_trim_st[2:0], only if OTP[59]=1. The value of boost_il_trim_st[2:0] is applied
starting from the moment when RFFE_REG_0x1C / Power Mode filed is written ‘00’ during LP mode,
until first vhv_too_low negative edge is detected.
www.onsemi.com
23
TCC−226
RFFE_REG_0x10
Register RFFE:
0x10
Address RFFE A[4:0]:
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
7
Bits
Reset
6
5
Reserved
U−0
U−0
4
3
Fixed
U−0
U−1
2
1
0
Boost voltage value
W−1
W−0
W−1
W−1
Bit [3:0]: Boost voltage value
Refer to Table 19 for values
The MIPI RFFE Trigger Modes can be used as a synchronization signal to ensure that new DAC settings are applied to the
outputs at appropriate times in the overall transceiver system. When the RFFE TRIG function is enabled via the TRIG SEL
bit of RFFE_REG_0x11the requested DAC voltage levels are set up in the shadow registers and not transferred to the
destination registers until the trigger condition is met. In this manner the change in output voltage levels are synchronized with
the RFFE TRIG command. The trigger configuration also provides for an external TRIG pin to be used as a synchronization
signal. When the TRIG input pin is enabled via the TRIG SEL bit of RFFE_REG_0x11the requested DAC voltage levels are
set up in the shadow registers and are not transferred to the destination registers until the external trigger condition is met. In
this manner the change in output voltage levels are synchronized with the external TRIG event. The external TRIG input is
referenced to VIO. To improve interfacing options the polarity of external TRIG is programmable via TRIG_edge bit of
RFFE_REG_0x11. When MIPI RFFE trigger and the external TRIG input are disabled by
MASK_EXT_TRIG of RFFE_REG_0x11 and TRIGGER_MASK[5:3] of RFFE_REG_0x1C, the requested DAC voltage
levels are immediately applied to the outputs and are not synchronized with the RFFE Trigger Modes or the external TRIG
signal.
When valid trigger edge occurs, only the completely received messages are subject to be applied to the outputs.
A message is considered to be completed, if the TRIG edge occurs after TRIG_LAT following last SDL clock falling edge
in the frame.
In Figure 17, the last SDL clock cycle in each frame is highlighted gray.
The parameter TRIG_LAT is represented as the latency following the SDL last falling edge in the frame until TRIG edge
occurs.
As an example, in Figure 17 TRIG edge 3 occurs before TRIG_LAT, following last SDL falling edge in frame of
“MESSAGE A3”, so TRIG edge 3 will move “MESSAGE A2” to output, instead of “MESSAGE A3”. In this case TRIG edge
3 has the same effect as TRIG edge 2, which is described below.
If trigger edge occurs while a message frame is being received by the slave on the serial bus, than the pending message will
not be transferred to the output until next trigger edge occurs after frame transfer is completed.
A pending message is considered from the moment SSC cycle starts, until after TRIG_LAT following last SDL falling edge
in the frame.
For example, in Figure 17, both TRIG edge 2 and TRIG edge 3 occur while “MESSAGE A3” is pending. In this case both
will have same effect, which is to transfer “MESSAGE A2” to the output.
“MESSAGE A3” will be transferred to the output by TRIG edge 4, because it occurs after TRIG_LAT.
If more than one message was received before a trigger edge, than only the last completed message will be transferred to
the output.
For example, in Figure 17, between TRIG edge 1 and TRIG edge 2, there have been two messages sent: “MESSAGE A1”
and “MESSAGE A2”. In this case, “MESSAGE A1” will be ignored, and only “MESSAGE A2” will be transferred to the
output by TRIG edge 2.
Figure 17. Sequences of Triggers and Messages to Same Output
www.onsemi.com
24
TCC−226
In Figure 18, TRIG edge 2, will transfer “MESSAGE A2”, “MESSAGE B1”, and “MESSAGE C1” to the respective outputs,
but will ignore “MESSAGE A1”.
Figure 18. Sequences of Triggers and Messages to Different Outputs
Table 30. TRIG_LAT PARAMETER TIMING
Symbol
Description
Min
Max
Unit
TRIG_LAT
Latency following the falling edge of last clock cycle of a certain message, until
the moment a TRIG edge is allowed to update the value sent by that message
5
25
ns
Register RFFE:
RFFE_REG_0x11
7
6
Bits
Address RFFE A[4:0]:
5
Reserved
Reset
U-0
U-0
4
3
2
TRIG SEL
U-0
W-1
Reserved
U−0
U−0
0x11
1
0
TRIG Edge
(1) (2)
MASK EXT TRIG
W−1
W−1
(1) Following sequence is required when changing the expected polarity of TRIG pin:
a) TRIG_SEL = ‘1’ (disable TRIG pin)
b) TRIG_EDGE = new value
c) TRIG_SEL = ‘0’ (enable TRIG pin)
(2) After power−up, first configure TRIG_Edge, then write TRIG_SEL = ‘0’ Bit 4: TRIG Select
0: Use external TRIG pin. Sending the RFFE message will load a ’shadow’ registers only. Only upon an
active signal on external TRIG pin are the output registers loaded with the new voltage settings which
are then applied to the outputs. Software triggers generated by bits [2:0] of RFFE_REG_0x1C are
ignored when external TRIG pin is selected.
1: External TRIG pin will not be used. (default)
Bit [1]: TRIG edge
0: TRIG pin active falling
1: TRIG pin active rising (default)
Bit [0]: MASK EXT TRIG
0: External trigger is not masked
1: Mask external trigger pin (default)
Turbo mode timing is controlled by these registers:
Register RFFE:
RFFE_REG_0x12
0x12
Address RFFE A[4:0]:
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
7
6
Bits
Reset
Register RFFE:
Reserved
U−0
5
4
3
TC_STP_DAC_C
U−0
W−0
W−1
RFFE_REG_0x13
2
TC_STP_DAC_B
W−0
W−1
1
0
TC_STP_DAC_A
W−0
Address RFFE A[4:0]:
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
www.onsemi.com
25
0x13
W−1
TCC−226
7
6
Bits
5
Reserved
Reset
U−0
Register RFFE:
4
3
2
TCM_C
U−0
W−0
1
0
TCM_B
W−0
W−0
RFFE_REG_0x14
TCM_A
W−0
W−0
Address RFFE A[4:0]:
W−0
0x14
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
7
6
Bits
5
Reserved
Reset
U−0
Register RFFE:
4
3
TC_STP_DAC_F
U−0
W−0
2
1
TC_STP_DAC_E
W−1
W−0
RFFE_REG_0x15
0
TC_STP_DAC_D
W−1
W−0
Address RFFE A[4:0]:
W−1
0x15
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
7
6
Bits
5
Reserved
Reset
U−0
Register RFFE:
4
3
2
TCM_F
U−0
W−0
1
0
TCM_E
W−0
W−0
RFFE_STATUS_0x1A
TCM_D
W−0
W−0
Address RFFE A[4:0]:
W−0
0x1A
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
7
6
5
4
3
2
1
0
Bits
SWR
CFPE
CLE
AFPE
DFPE
RURE
WURE
BGE
Reset
W−0
R−0
R−0
R−0
R−0
R−0
R−0
R−0
TC_STP_DAC_x[1:0]
Turbo steps for TCDLY [us]
00
3
01 (default)
5
10
7
11
9
TCM_x[1:0]
Turbo Multiplication Factor
00 (default)
4
01
3
10
2
11
1
Step
(ms)
DAC
state
9
0
1
2
3
4
5
6
7
8
9
10
11
TCDLY
Turbo OFF
18
27
36
45
54
63
72
81
90
99
7
TCDLY
Turbo OFF
14
21
28
35
42
49
56
63
70
77
5
(default)
TCDLY
Turbo OFF
10
15
20
25
30
35
40
45
50
55
3
TCDLY
Turbo OFF
6
9
12
15
18
21
24
27
30
33
The value of Turbo time is deducted based on the hardware comparison of new DAC value in respect to old DAC value, as
follows:
If DAC new > DAC old, then TUP = TCDLY
www.onsemi.com
26
TCC−226
If DAC new < DAC old, and DAC new_divby2 < 21, then TDOWN = TCDLY + TCM * (21 – DAC_new_divby2) If DAC
new < DAC old, and DAC new_divby2 > 21, then TDOWN = TCDLY
If DAC new < DAC old, and DAC new_divby2 = 21, then TDOWN = TCDLY
RFFE_STATUS register can be read any time after power−up without the need to enable the Read Operation
as described in section 6.9.5
SWR Soft−Reset MIPI−RFFE registers
Write ‘1’ to this bit to reset all the MIPI−RFFE registers, except RFFE_REG_0x1C, RFFE_USID,
and
RFFE_GROUP_SID
This bit will always Read−back ‘0’.
The soft reset occurs in the last clock cycle of the MIPI−RFFE frame which Writes ‘1’ to this bit.
Right immediately after this frame, all the MIPI−RFFE registers have the reset value and are ready to
be reprogrammed as desired.
The OTP duplicated registers are reset to the values written in OTP.
SWR can be written only by USID messages. GSID and Broadcast frames will be ignored when
writing to this register field.
RFFE_STATUS Bits [6:0] are set ‘1’ by hardware to flag when a certain condition is detected, as described
below. RFFE_STATUS Bits [6:0] cannot be written, but it is cleared to ‘0’ under following conditions:
•
Hardware Self−reset is applied after RFFE_STATUS is READ
•
When SWR is written ‘1’ with USID frames
•
When power mode transitions through STARTUP mode ‘01’
•
After Power−up Reset
CFPE
1: Command frame with parity error received.
On the occurrence of this error, the slave will ignore the entire Command Sequence
CLE
1: Incompatible command length, due to unexpected SSC received before command length to be
completed.
On the occurrence of this error, the slave will accept Write data up to the last correct and
complete frame. When MIPI−RFFE multi−byte Read command is detected, the slave will
always replay with an extended Read command of length of one byte.
AFPE
1: Address frame with parity error received.
On the occurrence of this error, the slave will ignore the entire Command Sequence
DFPE
1: Data frame with parity error received.
RURE
On the occurrence of this error, the slave will ignore only the erroneous data byte (s)
1: Read of non−existent register was detected.
On the occurrence of this error, the slave will not respond to the Read command frame.
When the Read Operation is not enabled according to section 6.9.5, any read from an address
other than
0x1A, will set RURE and the slave will not respond to the Read command frame.
When the Read Operation is enabled according to section 6.9.5, any read from an unoccupied
RFFE register address will set RURE.
WURE
1: Write to non−existent register was detected.
On the occurrence of this error, the slave discards data being written, and on the next received
frame, proceeds as normal
BGE
1: Read using the Broadcast ID was detected
On the occurrence of this error, the slave will ignore the entire Command Sequence
www.onsemi.com
27
TCC−226
RFFE_GROUP_SID_0x1B
Register RFFE:
Address RFFE A[4:0]:
0x1B
Reset Source: nreset_dig or PWR_MODE = ‘01’ (transition through STARTUP mode)
Bits
Reset
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
GSID[3]
GSID[2]
GSID[1]
GSID[0]
0
0
0
0
W-0
W-0
W-0
W-0
GSID = Group Slave Identifier Register
NOTE: The GSID[3:0] field can be written directly by messages using USID. NOTE: GSID value is NOT retained during
SHUTDOWN power mode. NOTE: GSID value is not affected by SWR bit from RFFE_STATUS register
NOTE: Frames using USID = GSID, can write only to RFFE_REG_0x1C [7:6] and [2:0].
NOTE: RFFE READ frames containing GSID will be ignored
Register RFFE:
RFFE_REG_0x1C
Address RFFE A[4:0]:
0x1C
Reset Source: nreset_dig or PWR_MODE = ‘01’ (transition through STARTUP mode)
7
Bits
Reset
6
Power Mode (5)
W−0
W−0
5
4
3
2
1
0
Trigger Mask 2
(1) (2) (3) (4)
Trigger Mask 1 (1) (2) (3)
(4)
Trigger Mask 0
(1) (2) (3) (4)
Trigger 2
Trigger 1
Trigger 0
W−0
W−0
W−0
W−0
W−0
W−0
(1) Trigger Mask bits [5:3] can be changed, either set or cleared, only with an individual message
using USID
(2) During broadcast MIPI−RFFE accesses using GSID = ‘0000’, Trigger bits [2:0] are masked by the
pre−existent setting of Trigger Mask Bits [5:3]
(3) During Individual MIPI−RFFE accesses using USID, Trigger bits [2:0] are masked by the
incoming Trigger Mask bits [5:3] within the same write message to RFFE_REG_0x1C register.
During Individual MIPI−RFFE accesses using USID, pre−existent setting of Trigger Mask Bits [5:3]
is ignored.
(4) When RFFE_REG_0x11 / TRIG_SEL = ‘1’ (External TRIG pin will not be used) and
RFFE_REG_0x1C/ Trigger_Mask_2 = ‘1’ and Trigger_Mask_1 = ‘1’ and Trigger_Mask_0 = ‘1’,
then DAC messages will be sent to DACs immediately after RFFE_REG_0x04 is received, without
waiting for any trigger
(5) Power mode field bits [7:6] and Triggers bits [2:0] can be changed by either MIPI−RFFE
broadcast messages when USID field within the Register Write Command is 0x0 , or individual
messages when USID fields within the Register Write Command is equal with RFFE_REG_0x1F[3:0]
NOTE: All the 8 bits of RFFE_REG_0x1C register bits are NOT affected by SWR bit from
RFFE_STATUS register
Bit [7:6]: Power Mode
00: ACTIVE mode, defined by following hardware behavior:
•
Boost Control active, VHV set by Digital Interface
•
Vout A, B, C enabled and controlled by Digital Interface
01: STARTUP mode, defined by following hardware behavior:
•
Boost Control active, VHV set by Digital Interface
•
Vout A, B, C disabled
10: LOW POWER mode when TRIG pin = LOW, ACTIVE mode when TRIG pin = HIGH.
LOW POWER mode is defined by following hardware behavior:
•
Digital interface is active, while all other circuits are in low power mode
11: Reserved (State of hardware does not change)
Bit 5: Mask trigger 2
0:Trigger 2 not masked. Data goes to destination register after bit 2 is written value 1 (default)
1:Trigger 2 is masked. Data goes directly to the destination register
Bit 4: Mask trigger 1
0:Trigger 1 not masked. Data goes to destination register after bit 1 is written value 1(default)
1:Trigger 1 is masked. Data goes directly to the destination register.
Bit 3: Mask trigger 0
0:Trigger 0 not masked. Data goes to destination register after bit 0 is written value 1(default)
1:Trigger 0 is masked. Data goes directly to the destination register.
www.onsemi.com
28
TCC−226
Bit 2: Trigger 2
Write 1 to this bit, to move data from shadow registers into destination register. This trigger can be
masked by bit 5.
Bit 1: Trigger 1
Write 1 to this bit, to move data from shadow registers into destination register. This trigger can be
masked by bit 4.
Bit 0: Trigger 0
Write 1 to this bit, to move data from shadow registers into destination register. This trigger can be
masked by bit 3.
All three triggers from register [0x1C] behave in the same way as the external pin TRIG. When each of these triggers is set
using the MIPI RFFE interface the results are the same as when an active voltage level is applied to the TRIG pin when External
pin TRIG is selected.
Register RFFE:
RFFE_PRODUCT_ID_0x1D
Address RFFE A[4:0]:
0x1D
Reset Source: N/A
Bits
7
6
5
4
3
2
1
0
PID7
PID6
PID5
PID4
PID3
PID2
PID1
PID0 (1)
0
0
1
0
0
1
OTP[4]
IDB0 pin
Reset
Bits [7:2] are hardcoded in ASIC
Bit [1] is programmed during manufacturing 0=TCC−226A
The MIPI register RFFE_PRODUCT_ID can be read in SPI mode as described in 6.9.5
Register RFFE:
RFFE_MANUFACTURER_ID_0x1E
Address RFFE A[4:0]:
0x1E
Reset Source: N/A
Bits
Reset
7
6
5
4
3
2
1
0
MPN7
MPN6
MPN5
MPN4
MPN3
MPN2
MPN1
MPN0
0
0
1
0
1
1
1
0
Register RFFE:
RFFE_USID_0x1F
Address RFFE A[4:0]:
0x1F
Reset Source: nreset_dig or PWR_MODE = ‘01’ (transition through STARTUP mode)
7
Bits
Reset
6
Reserved (2)
0
0
5
4
3
2
1
0
MPN9 (2)
MPN8 (2)
USID3 (1)
USID2 (1)
USID1 (1)
USID0 (1)
0
1
W−0
W−1
W−1
W−1
USID = Unique Slave Identifier Register
(1) USID field can be changed by:
•
MIPI−RFFE broadcast messages when USID field within the Register Write Command is
0b0000
•
MIPI−RFFE individual messages when USID field within the Register Write Command
equal with content of RFFE_REG_0x1F[3:0]
(2) In the sequence of writing USID field, the upper [7:4] must match the value 0b0001 hard−coded in
the RFFE register 0x1F
NOTE: USID value is NOT retained during SHUTDOWN power mode.
NOTE: USID value is not affected by SWR bit from RFFE_STATUS register DAC Update
www.onsemi.com
29
TCC−226
Following picture shows TCC−226 and all the necessary external components
IVDDA
CVDDA
VBATT
IBATT
IIND
RFILT
LBOOST
CHV
CBOOST
L_BOOST
VDDA
IVIO
VIO
VIO
TCC−226
VHV
VREG
CVREG
OUTA,B,C,D,E,F
C DACA,B,C,D,E,F
CVIO
Figure 19. TCC−226 with External Components
Table 31. RECOMMENDED EXTERNAL BOM
Component
Description
CBOOST
Boost Supply Capacitor, 10 V
LBOOST
Boost Inductor
Nominal Value
Package
Recommended P/N
1 mF
0402
TDK: C1005X5R1A105K
15 mH
0603
TDK: VLS2010ET−150M, Sunlord
SPH201610H150MT
RFILT
Filtering resistor, 5%
3.3 Ws
0402
Vishay : CRCW04023R30JNED
CVIO
VIO Supply Decoupling, 10 V
100 nF
0201
Murata: GRM033R61A104ME15D
CAVDD
VAVDD Supply Decoupling, 10 V
1 mF
0402
TDK: C1005X5R1A105K
CVREG
VVREG Supply Decoupling, 10 V
220 nF
0201
TDK: C0603X5R1A224M
Boost Tank Capacitor, 50 V
47 nF
1005
Murata: GRM155C71H473KE19
Decoupling Capacitor, 50 V (Note 7)
100 pF
0201
Murata: GRM0335C1H101JD01D
CHV
CdacA,B,C,D,E,F
7. Recommended for noise reduction only – not essential
www.onsemi.com
30
TCC−226
Footprint Compatibility with TCC−303
TCC−226 and TCC−303 can share the same footprint on
a product board. If this is the intention for the product
design, an additional SOT−923 footprint is required to
support the boost diode needed by TCC−303. This
component is placed between the L−Boost and VHV pins.
Both parts use a 0.35 mm bump pitch with 200 um diameter
standard lead−free balls. Care should be taken when setting
up any pick and place type machinery for product assembly
as the footprint center and die placement centers are offset
by the following dimensions:
TCC−226
0.058(h) x 0.112(v)
TCC−303
−0.0175(h) x −0.0175(v)
Figure 20. TCC−226 and TCC−303 Bump
Configuration (Topside View)
www.onsemi.com
31
TCC−226
TAPE & REEL DIMENSIONS
Figure 21. WLCSP Carrier Tape Drawings
Figure 22. Orientation in Tape
Table 32. ORDERING INFORMATION
Device
Package
Marking
Shipping†
TCC−226A−RT
RDL
(Pb−Free)
t26a
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ASSEMBLY INSTRUCTIONS
Note: It is recommended that under normal circumstances, this device and associated components should be located in a
shielded enclosure.
www.onsemi.com
32
TCC−226
PACKAGE DIMENSIONS
WLCSP20 2.187x1.987
CASE 567MZ
ISSUE A
E
ÈÈ
PIN A1
REFERENCE
2X
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
B
D
0.05 C
2X
0.05 C
TOP VIEW
A
0.10 C
A2
A1
0.08 C
C
SIDE VIEW
NOTE 3
MILLIMETERS
MIN
MAX
−−−
0.65
0.13
0.19
0.38 REF
0.17
0.23
2.187 BSC
0.058 BSC
1.987 BSC
0.112 BSC
0.35 BSC
DIM
A
A1
A2
b
D
D2
E
E2
e
RECOMMENDED
SOLDERING FOOTPRINT*
SEATING
PLANE
A1
e
20X
0.05 C A B
0.03 C
E2
b
e
E
D
C
B
A
0.35
PITCH
D2
20X
0.35
PITCH
0.17
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
1 2 3 4
BOTTOM VIEW
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
www.onsemi.com
33
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
TCC−226/D