LM3263 www.ti.com SNVS837 – JUNE 2013 LM3263 High-Current Step-Down DC-DC Converter with MIPI® RF Front-End Control Interface for RF Power Amplifiers Check for Samples: LM3263 FEATURES 1 • • 23 • • • • • • • • • ® MIPI RFFE Digital Control Interface High-Efficiency PFM and PWM Modes with Internal Seamless Transition Operates from a Single Li-Ion Cell: 2.7V to 5.5V Dynamically Adjustable Output Voltage: 0.4V to 3.6V (typ.) in PFM and PWM Modes 2.5A Maximum Load Current in PWM Mode 2.7 MHz (typ.) Switching Frequency ACB (reduces inductor requirements and size) Internal Compensation Current and Thermal Overload Protection 16-bump DSBGA Package Very small Solution Size: approx. 9.8 mm2 APPLICATIONS • • • • • Smartphones RF PC Cards Tablets, eBook Readers Handheld Radios Battery-Powered RF Devices DESCRIPTION The LM3263 is a DC-DC converter optimized for powering multi-mode multi-band RF power amplifiers (PAs) from a single Lithium-Ion cell. The LM3263 steps down an input voltage from 2.7V to 5.5V to a dynamically adjustable output voltage of 0.4V to 3.6V. The output voltage is externally programmed through the RFFE Digital Control Interface and is set to ensure efficient operation at all power levels of the RF PA. The LM3263 operates in modulated frequency PWM mode producing a small and predictable amount of output voltage ripple. PWM mode enables best meeting power requirements and stringent spectral compliance, with the minimal amount of filtering and excess headroom. When operating in PFM mode, the LM3263 enables the lowest current consumption across PA output power level settings and therefore maximizes system efficiency. The LM3263 has a unique Active Current assist and analog Bypass (ACB) feature to minimize inductor size without any loss of output regulation for the entire battery voltage and RF output power range, until dropout. ACB provides a parallel current path, when needed, to limit the maximum inductor current to 1.45A (typ) while still driving a 2.5A load. The analog bypass feature also enables operation with minimal dropout voltage. The LM3263 is available in a small 2 mm x 2 mm chip-scale 16-bump DSBGA package. 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MIPI is a registered trademark of Mobile Industry Processor Interface Alliance. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated LM3263 SNVS837 – JUNE 2013 www.ti.com TYPICAL APPLICATION CIRCUIT VBATT 2.7V to 5.5V 0.1 µF 10 µF PACB PVIN SVDD FB VIO 1.8V RFFE Master ACB Output Voltage 0.4V to 3.6V 1.5 µH SCLK LM3263 SW SDATA 3.3 nF 10 µF 2G VCC_PA GPO1 4.7 µF PA BGND SGND PGND 3 x 1.0 µF 3G/4G VCC_PA PA(s) This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. CONNECTION DIAGRAMS PVIN SW PGND ACB A A ACB PGND SW PVIN PVIN SW BGND PACB B B PACB BGND SW PVIN VIO SDATA FB ACB C C ACB FB SDATA VIO SCLK GPO1 SGND SVDD D D SVDD SGND GPO1 SCLK 1 2 3 4 3 2 1 4 Bottom View Top View 2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 LM3263 www.ti.com SNVS837 – JUNE 2013 PIN DESCRIPTIONS Pin # A1 B1 Name PVIN C1 VIO D1 SCLK A2 B2 SW Description Power Supply Voltage Input to the internal PFET switch. VIO functions as the RFFE interface reference voltage. VIO also functions as reset and enable input to the LM3263. Typically connected to voltage regulator controlled by RF or Baseband IC. Digital control interface RFFE Bus clock input. Typically connected to RFFE master on RF or Baseband IC. SCLK must be held low when VIO is not applied. Switching Node connection to the internal PFET switch and NFET synchronous rectifier. SDATA Digital control interface RFFE Bus data input/output. Typically connected to RFFE master on RF or Baseband IC. SDATA must be held low when VIO is not applied. D2 GPO1 General Purpose Output. Also used to reconfigure USID. A3 PGND Power Ground to the internal NFET switch. B3 BGND ACB, Analog Bypass Ground and Digital Ground. C2 C3 FB D3 SGND A4 C4 ACB Feedback Analog Input. Connect to the output at the output filter capacitor. Signal Analog Ground (Low Current). ACB and Analog Bypass output. Connect to the output at the output filter capacitor. B4 PACB ACB Power Supply Input. D4 SVDD Analog Power Supply Voltage. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 3 LM3263 SNVS837 – JUNE 2013 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) (2) VBATT Pins to GND (PVIN, SVDD, PACB to PGND, SGND, BGND) FB, SW, GPO1, ACB, VIO, SDATA, SCLK −0.2V to +6.0V (GND-0.2V) to (VIN+0.2V) w/ 6.0V max Continuous power dissipation Internally Limited (3) Maximum operating junction temperature (TJ-MAX) +150°C Storage temperature range −65°C to +150°C Maximum lead temperature (Soldering 10 sec.) +260°C ESD rating (4) (5) Human Body Model Charged-Device Model (1) (2) (3) (4) (5) 1kV 250V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to the potential at the GND pins. Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and disengages at TJ = 125°C (typ.). The Human Body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (MIL-STD-883 3015.7) Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper ESD handling procedure can result in damage. OPERATING RATINGS (1) Input voltage range PVIN, SVDD, PACB 2.7V to 5.5V Input voltage range VIO 1.65V to 1.95V Recommended current load 0 to 2.5A −30°C to +125°C Junction temperature (TJ) range Ambient temperature (TA) range (1) (2) (2) −30°C to +90°C All voltages are with respect to the potential at the GND pins. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be de-rated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). At higher power levels duty cycle usage is assumed to drop (i.e., max power 12.5% usage is assumed) for GSM/GPRS mode. THERMAL PROPERTIES Junction-to-Ambient Thermal Resistance (θJA), YFQ16 Package (1) 4 (1) 50°C/W Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC standard JESD51-7 and is board-dependent. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 LM3263 www.ti.com SNVS837 – JUNE 2013 ELECTRICAL CHARACTERISTICS (1) (2) (3) Limits in standard typeface are for TA = TJ = 25°C. Limits in boldface type apply over the full operating ambient temperature range (−30°C ≤ TJ = TA ≤ +90°C). Unless otherwise noted, specifications apply to the Typical Application Diagram with VBATT = 3.8V (=PVIN = SVDD = PACB), VIO = 1.8V. Min Typ Max VFB,MIN Symbol Feedback voltage at minimum setting VSET[7:0] = 1Bh, SMPS_CFG[5] = 1b 0.350 0.4 0.450 VFB,MAX Feedback voltage at maximum setting VSET[7:0] = F0h, VBATT = 3.9V, SMPS_CFG[5] = 0b 3.492 3.6 3.708 ISHDN Shutdown supply current SW = 0V, VIO = 0V (4) 0.02 4 IL-PWR Low-power mode supply current VSET[7:0] = 00h 0.225 IQ-PFM PFM mode supply current into SVDD No switching (5), SMPS_CFG[5] = 1b 360 425 IQ PWM mode supply current No switching (5), SMPS_CFG[5] = 0b 1240 1400 1.9 2.1 1.35 1.45 1.65 1.4 1.7 2.0 PWM Parameter Condition ILIM, PFET Transient Positive transient peak current limit ILIM, PFET SteadyState Positive steady-state peak current limit VSET[7:0] = 64h (6) Units V µA A ILIM, P-ACB Positive Active Current Assist peak current limit ILIM,NFET NFET current limit VSET[7:0] = A7h (6) FOSC Average Internal oscillator frequency VSET[7:0] = A7h 2.97 MHz IVIO-IN VIO voltage average input current Average during a 26 MHz 1.25 mA VIORST RFFE I/O voltage reset voltage VIO toggled low 0.45 V IINVIO VIO reset current VIO = 0.45V −1.0 1.0 IIN SDATA, SCLK input current VIO = 1.95V −1.0 1.0 VIH Input high-level threshold SDATA, SCLK 0.4* VIO 0.7 * VIO VIL Input low-level threshold SDATA, SCLK 0.3 * VIO 0.6 * VIO VIH-GPO Input high-level threshold GPO1 1.35 VIL-GPO Input low-level threshold GPO1 VOH Output high-level threshold SDATA ISDATA = 2mA VOL Output low-level threshold SDATA ISDATA = –2mA VOH-GPO Output high-level threshold GPO VOL-GPO Output low-level threshold GPO VSET-LSB Output voltage LSB (1) (2) (3) (4) (5) (6) −1.50 2.43 2.7 µA V 0.67 IOUT = ±200 µA VSET[7:0] = A7h to A8h VIO * 0.8 VIO + 0.01 VIO * 0.2 VIO - 0.15 VIO + 0.1 -0.4 V 0.3 15 mV All voltages are with respect to the potential at the GND pins. Min and Max limits are specified by design, test, or statistical analysis. The parameters in the electrical characteristics table are tested under open loop conditions at PVIN = SVDD = PACB = 3.8V. Shutdown current includes leakage current of PFET. Iq specified here is when the part is not switching. Current limit is built-in, fixed, and not adjustable. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 5 LM3263 SNVS837 – JUNE 2013 www.ti.com SYSTEM CHARACTERISTICS The following spec table entries are specified by design and verifications providing the component values in the Typical Application Circuit are used (L = 1.5 µH, DCR = 120 mΩ, TOKO DFE201610MT-1R5N, CIN = 10 µF, 6.3V, 0402, Samsung CL05A106MP5NUN, COUT = 10 µF + 4.7 µF + 3 x 1.0 µF; 10V, 0402, Samsung CL05A106MP5NUN, CL05A475MPNRN; 6.3V, 0201, TDK, C0603X5R0J105M). These parameters are not verified by production testing. Min and Max values are specified over the ambient temperature range TA = -30°C to 90°C. Typical values are specified at VBATT = 3.8V (= PVIN = SVDD = PACB), VIO = 1.8V, SMPS_CFG = 20h, and TA =25°C unless otherwise stated. Symbol Parameter Conditions Turn-on time (time for output to reach 95% of 3.4V value from the end of the SCLK pulse) TON Min Typ VBATT = 4.2V, VSET[7:0] =00h to E3h, VSET = 3.4V, IOUT ≤ 1mA Time for VOUT to rise from 0.09V to 3.4V VBATT = 3.8V, RLOAD = 68Ω (3.07V, 90% of delta VOUT from the end of VSET[7:0] = 06h to E3h SCLK pulse) SMPS_CFG[5] = 0b/1b Time for VOUT to rise from 0.8V to 3.3V V = 3.8V, RLOAD = 20Ω (3.05V, 90% of delta VOUT from the end of BATT VSET[7:0] =36h to DCh SCLK pulse) 7.4 Time for VOUT to fall from 3.3V to 0.8V V = 3.8V, RLOAD = 20Ω (1.05V, 10% of delta VOUT from the end of BATT VSET[7:0] = DCh to 36h SCLK pulse) 6.8 Time for VOUT to rise from 1.4V to 3.4V (3.2V, 90% of delta VOUT from the end of SCLK pulse) VBATT = 3.8V, RLOAD = 6.8Ω VSET[7:0] = 5Eh to E3h Time for VOUT to fall from 3.4V to 1.4V (1.6V, 10% of delta VOUT from the end of SCLK pulse) VBATT = 3.8V, RLOAD = 6.8Ω VSET[7:0] = E3h to 5Eh Time for VOUT to rise from 1.8V to 2.8V (2.7V, 90% of delta VOUT from the end of SCLK pulse) VBATT = 3.8V, RLOAD = 2.2Ω VSET[7:0] = 78h to BBh SMPS_CFG[5] = 0b Time for VOUT to fall from 2.8V to 1.8V (1.9V, 10% of delta VOUT from the end of SCLK pulse) VBATT = 3.8V, RLOAD = 2.2Ω VSET[7:0] = BBh to 78h SMPS_CFG[5] = 0b µs µs 10 15 Time for VSET to rise from 0.09V to PVIN VBATT = 3.6V, IOUT ≤ 1mA, after BYPASS transition (90%) VSET[7:0] = 06h to FFh Rtot-drop Total dropout resistance in bypass mode VSET[7:0] = FAh, Max value at VBATT = 3.1V, Inductor DCR ≤ 151 mΩ IOUT Maximum load current in PWM mode Switcher + ACB IOUT, PU Maximum output transient pull-up current limit 45 20 µs 55 mΩ 2.5 3.0 A Switcher + ACB (1) IOUT, PD, PWM PWM maximum output transient pulldown current limit IOUT, MAX_PFM Maximum output load current in PFM mode VBATT = 3.8V, VSET = 3.2V Linearity Linearity in control range of VSET = 0.4V to 3.6V VBATT = 3.9V (2), Monotonic in nature; VSET[7:0] = 1Bh to F0h, SMPS_CFG[5] = 0b 6 50 12 TBypass (1) (2) Units 15 Time for VOUT to fall from 3.4V to 0.09V VBATT = 3.8V, RLOAD = 68Ω (0.42V, 10% of delta VOUT from the end of VSET[7:0] = E3h to 06h SCLK pulse) SMPS_CFG[5] = 0b/1b TRESPONSE Max −3.0 60 mA −3.0 +3.0 % −50 +50 mV Current limit is built-in, fixed, and not adjustable. Linearity limits are ±3% or ±50 mV whichever is larger. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 LM3263 www.ti.com SNVS837 – JUNE 2013 SYSTEM CHARACTERISTICS (continued) The following spec table entries are specified by design and verifications providing the component values in the Typical Application Circuit are used (L = 1.5 µH, DCR = 120 mΩ, TOKO DFE201610MT-1R5N, CIN = 10 µF, 6.3V, 0402, Samsung CL05A106MP5NUN, COUT = 10 µF + 4.7 µF + 3 x 1.0 µF; 10V, 0402, Samsung CL05A106MP5NUN, CL05A475MPNRN; 6.3V, 0201, TDK, C0603X5R0J105M). These parameters are not verified by production testing. Min and Max values are specified over the ambient temperature range TA = -30°C to 90°C. Typical values are specified at VBATT = 3.8V (= PVIN = SVDD = PACB), VIO = 1.8V, SMPS_CFG = 20h, and TA =25°C unless otherwise stated. Symbol η Parameter Conditions Efficiency Min Typ VBATT = 3.8V, VSET= 0.5V, IOUT = 5mA 52 56 VBATT = 3.8V, VSET= 1.8V, IOUT = 10 mA 78 82 VBATT = 3.8V, VSET= 1.6V, IOUT = 130 mA 83 89 VBATT = 3.8V, VSET = 2.5V, IOUT = 250 mA 90 94 VBATT = 3.8V, VSET = 3.4V, IOUT = 550 mA 93 95 VBATT = 3.8V, VSET = 1.0V, IOUT = 400 mA, SMPS_CFG[5] = 0b 81 85 VBATT = 3.8V, VSET = 3.5V, IOUT = 1900 mA, SMPS_CFG[5] = 0b 89 92 2.7 MHz PWM normal operation ripple VBATT = 3.2V to 4.3V, VSET = 0.4V to 3.6V, RLOAD = 1.9Ω (3) SMPS_CFG[5]= 0b Ripple voltage at pulse skipping condition VBATT = 3.2V, VSET = 3.0V, RLOAD = 1.9Ω (3) SMPS_CFG[5]= 0b VRIPPLE 1 Max % 3 8 mVpp VBATT = 3.2V, VSET = 3.0V, IOUT = 40 mA VBATT = 3.2V, VSET = 2.5V, IOUT = 10 mA PFM ripple voltage Units 50 VBATT = 3.2V, VSET< 0.5V, IOUT = 5 mA Line transient response VBATT = 3.6V to 4.2V, TR = TF = 10 µs, VSET = 3.2V, IOUT = 500 mA 50 Load_tr Load transient response VSET = 3.0V, TR = TF = 10 µs, IOUT = 0A to 1.2A, SMPS_CFG[5] = 0b 60 Max Duty Cycle Maximum duty cycle Line_tr PFM_Freq 100 Minimum PFM frequency % VBATT = 3.2V, VSET = 1.0V, IOUT = 10 mA 100 160 VBATT = 3.2V, VSET = 0.5V, IOUT = 5 mA 34 55 8 NSET VSET DAC number of bits Monotonic TSETUP Power-up time (time for RFFE bus active after VIO applied) VIO = Low to 1.65V TVIO-RST VIO supply reset timing VIO = 0.45V (3) mVpk KHz Bits 50 10 ns µs Ripple voltage should be measured at COUT electrode on a well designed PC board and using suggested inductor and capacitors. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 7 LM3263 SNVS837 – JUNE 2013 www.ti.com LM3263 USER STATE DIAGRAM VIO = Low VIO = Low Shutdown VIO = High VI O = w Lo PM_T= 38h and PM_T= 40h VC= 04h or 05h Low Power Standby PM_T= 80h or 40h or PM_T= 80h or 40h VC= 00h or 01h or VC= 04h or 05h VC= 00h or 01h PM_T= 38h and VC { 06h VC{ 06h Active VIO = Low PM_T = PM_TRIG [7:0] VC = VSET_CTRL [7:0] SMPS_CFG[5]= 0b SMPS_CFG[5]= 1b and and or VC= 1Bh to F0h VC= 1Bh to F0h VC= FEh or FFh Forced PWM mode SMPS_CFG[4]= 1b Auto-PFM mode Forced Bypass mode Note 1 : Specified Output Voltage range is 0.4V to 3.6V Note 2: Writing to and reading back from REGISTER_0 and VSET_CTRL access the same internal VSET register. Writing to VSET_CTRL programs the full 8 bits VSET value. Writing to REGISTER_0 will program 7 MSB of VSET with LSB set to zero. When REGISTER_0 is written, the internal VSET register LSB bit[0] will always take a value of 0 and subsequent read of VSET_CTRL bit[0] will be read back as 0. 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 LM3263 www.ti.com SNVS837 – JUNE 2013 TYPICAL PERFORMANCE CHARACTERISTICS (VBATT =3.8V, TA = 25°C, unless otherwise noted) Input Current (PFM) vs Input Voltage No Load Input Current (PWM) vs Input Voltage No Load 10 450 VOUT = 1.0V @ PFM mode INPUT CURRENT ( mA ) INPUT CURRENT (µA) 425 400 375 350 325 VOUT = 2.0V @ PWM Mode 8 6 4 2 0 300 2.5 3.0 3.5 4.0 4.5 INPUT VOLTAGE (V) 5.0 2.5 5.5 3.0 3.5 Figure 1. Average Switching Frequency vs. Input Voltage 5.0 5.5 C002 Output Voltage vs. VSET_CTRL Setting 4.0 2.95 VOUT = 2.0V, IOUT = 500mA OUTPUT VOLTAGE ( V ) SWITCHING FREQUENCY ( MHz ) 4.5 Figure 2. 3.00 2.90 2.85 2.80 2.75 2.70 2.65 2.60 3.5 VBATT = 4.2V RLOAD = 6.8 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.55 0.0 0.5 1.0 2.50 2.5 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE ( V ) 5.5 22 43 C003 1.5 2.0 2.5 3.0 3.5 C8 EA VSET VOLTAGE ( V ) 64 86 A7 VSET_CTRL (hex) 4.0 C004 Figure 3. Figure 4. Output Voltage vs. Input Voltage VOUT = 3.4V Efficiency vs. Load Current Auto-PFM Mode, IOUT = 10mA to 150mA 3.6 100 IOUT = 500mA 95 3.4 EFFICIENCY ( % ) OUTPUT VOLTAGE ( V ) 4.0 INPUT VOLTAGE ( V ) C001 3.2 3.0 IOUT = 1.5A 2.8 90 85 80 75 VOUT = 0.8V VOUT = 1.0V VOUT = 1.5V VOUT = 1.8V VOUT = 2.0V VOUT = 0.4V 70 65 2.6 60 2.5 3.0 3.5 4.0 4.5 INPUT VOLTAGE ( V ) 5.0 5.5 0 C005 Figure 5. 25 50 75 100 125 OUTPUT CURRENT ( mA ) 150 C006 Figure 6. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 9 LM3263 SNVS837 – JUNE 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) (VBATT =3.8V, TA = 25°C, unless otherwise noted) Efficiency vs. Load Current Forced PWM Mode, IOUT = 100mA to 1000mA 100 100 95 95 EFFICIENCY ( % ) EFFICIENCY ( % ) Efficiency vs. Load Current Auto-PFM Mode, IOUT = 150mA to 750mA 90 85 VOUT = 1.6V VOUT = 2.0V VOUT = 2.5V VOUT = 3.0V VOUT = 3.5V 80 75 90 85 VOUT = 1.6V VOUT = 2.0V VOUT = 2.5V VOUT = 3.0V VOUT = 3.5V 80 75 70 70 100 200 300 400 500 600 700 800 OUTPUT CURRENT ( mA ) 100 200 300 400 500 600 700 800 900 1,000 OUTPUT CURRENT ( mA ) C007 Figure 7. Figure 8. Efficiency vs. Load Current Forced PWM Mode, IOUT = 1.0A to 2.5A VOUT Transient (Auto-PFM) VOUT = 0.4V to 3.4V, RLOAD = 6.8Ω C008 100 VOUT (2V/DIV) EFFICIENCY ( % ) 95 90 85 SDATA (2V/DIV) 80 75 65 60 1.00 IOUT (500mA/DIV) VOUT = 2.0V VOUT = 2.5V VOUT = 3.0V VOUT = 3.5V 70 1.25 1.50 1.75 2.00 2.25 TIME ( 20µs/DIV ) 2.50 OUTPUT CURRENT ( A ) C010 C009 Figure 9. Figure 10. VOUT Transient (Forced PWM) VOUT = 1.4V to 3.4V, RLOAD = 1.9Ω Load Transient in PFM mode VOUT=1.0V, IOUT=0mA to 60mA VOUT (2V/DIV) VOUT 5mVac/DIV IOUT 50mA/DIV SDATA (2V/DIV) IOUT (1A/DIV) 100 s/DIV TIME ( 20µs/DIV ) C011 Figure 11. 10 Figure 12. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 LM3263 www.ti.com SNVS837 – JUNE 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) (VBATT =3.8V, TA = 25°C, unless otherwise noted) Load Transient VOUT=2.5V, IOUT=0mA to 300mA Load Transient VOUT=3.0V, IOUT=0mA to 700mA VOUT 50mVac/DIV VOUT 50mVac/DIV IOUT 200mA/DIV IOUT 500mA/DIV 100 s/DIV 100 s/DIV Figure 13. Figure 14. Load Transient VBATT=4.2V, VOUT=3.0V, IOUT=0mA to 1.2A Line Transient VBATT=3.6V to 4.2V, VOUT=2.5V, RLOAD=6.8Ω VOUT IOUT 100mVac/DIV VOUT 50mVac/DIV 500mA/DIV VBATT 500mV/DIV 100 s/DIV 100 s/DIV Figure 15. Figure 16. Line Transient VBATT=3.6V to 4.2V, VOUT=1.0V, RLOAD=6.8Ω Timed-Current Limit VBATT=4.2V, VOUT=2.5V, RLOAD=6.8Ω to 0Ω VOUT 1V/DIV SW 2V/DIV IIND 1A/DIV 50mVac/DIV VOUT 500mV/DIV VBATT 100 s/DIV 20 s/DIV Figure 17. Figure 18. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 11 LM3263 SNVS837 – JUNE 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) (VBATT =3.8V, TA = 25°C, unless otherwise noted) Startup from Low-Power Mode VBATT=4.2V, VOUT=3.4V, No Load Startup from Standby Mode VBATT=4.2V, VOUT=3.4V, No Load SW 2V/DIV SW 2V/DIV VOUT 1V/DIV VOUT 1V/DIV SDATA 2V/DIV SDATA 2V/DIV 10 s/DIV 10µs/DIV Figure 19. 12 Figure 20. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 LM3263 www.ti.com SNVS837 – JUNE 2013 OPERATION DESCRIPTION Device Information The LM3263 is a high-efficiency step-down DC-DC converter optimized to power the RF power amplifier (PA) in cell phones, portable communication devices, or battery-powered RF devices with a single Li-ion battery. It operates in modulated-frequency Pulsed Width Modulation (PWM) mode for 2G transmissions (with MODE=Forced PWM (PWM only), register 01h SMPS_CFG [5] set to 0b), automatic mode transition between Pulse Frequency Modulation (PFM) and PWM for 3G/4G RF PA operation (with MODE=Auto-PFM (PFM/PWM), SMPS_CFG bit 5 set to 1b), or Forced-Bypass mode (with SMPS_CFG [4] set to 1b or REGISTER_0 [6:0] set to 7Fh or register 03h VSET_CTRL [7:0] set to FEh-FFh). Power states are also in provided Shutdown, Low Power, Standby, and Active modes. The DC-DC converter operates at Active mode. Please see LM3263 USER STATE DIAGRAM and PROGRAMMABLE REGISTERS sections in detail. PWM mode provides high efficiency and very low output-voltage ripple. In PWM mode operation, the modulated switching frequency helps to reduce RF transmit noise. In PFM mode, the converter operates with reduced switching frequencies and lower supply current to maintain high efficiencies. The forced bypass mode allows the user to drive the output directly from the input supply through a bypass FET. The shutdown mode turns the LM3263 off and reduces current consumption to 0.02 µA (typ). In PWM and PFM mode of operation, the output voltage of the LM3263 can be dynamically programmed from 0.4V to 3.6V (typ) by setting the VSET register. Current overload protection and thermal overload protection are also provided. The LM3263 was engineered with Active Current assist and analog Bypass (ACB). This unique feature allows the converter to support maximum load currents of 2.5A (min.) while keeping a small footprint inductor and meeting all of the transient behaviors required for operation of a multi-mode RF Power Amplifier. The ACB circuit provides an additional current path when the load current exceeds 1.45A (typ.) or as the switcher approaches dropout. Similarly, the ACB circuit allows the converter to respond with faster VSET output voltage transition times by providing extra output current on rising and falling output edges. The ACB circuit also performs the function of analog bypass. Depending upon the input voltage, output voltage, and load current, the ACB circuit automatically and seamlessly transitions the converter into analog bypass, while maintaining output voltage regulation and low output voltage ripple. Full bypass (100% duty cycle operation) will occur if the total dropout resistance in bypass mode (Rtot_drop = 45 mΩ) is insufficient to regulate the output voltage. The LM3263’s 16-bump DSBGA package is the best solution for space-constrained applications such as cell phones and other hand-held devices. The high switching frequency, 2.7MHz (typ.) in PWM mode, reduces the size of input capacitors, output capacitor and of the inductor. Use of a DSBGA package is best suited for opaque case applications and requires special design considerations for implementation. (Refer to DSBGA Package Assembly And Use section below). PWM Operation The LM3263 operates in PWM mode when Forced-PWM mode operation is selected (SMPS_CFG [5] set to 0b). The switching frequency is modulated, and the switcher regulates the output voltage by changing the energy per cycle to support the load required. During the first portion of each switching cycle, the control block in the LM3263 turns on the internal PFET switch. This allows current to flow from the input through the inductor and to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of (VBATT – VSET)/L, by storing energy in its magnetic field. During the second portion of each cycle, the control block turns the PFET switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the NFET and to the output filter capacitor and load, which ramps the inductor current down with a slope of -VSET/L. The output filter capacitor stores charge when the inductor current is greater than the load current and releases it when the inductor current is less than the load current, smoothing the voltage across the load. At the next rising edge of the clock, the cycle repeats. An increase of load pulls the output voltage down, increasing the error signal. As the error signal increases, the peak inductor current becomes higher therefore increasing the average inductor current. The output voltage is therefore regulated by modulating the PFET switch on time to control the average current sent to the load. The circuit generates a duty-cycle modulated rectangular signal that is averaged using a low pass filter formed by the inductor and output capacitor. The output voltage is equal to the average of the duty-cycle modulated rectangular signal. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 13 LM3263 SNVS837 – JUNE 2013 www.ti.com PFM Operation When Auto-PFM mode operation is selected (SMPS_CFG [5] set to 1b), the LM3263 automatically transitions from PWM operation into PFM operation if the average inductor current is less than 60 mA (min.) and the difference between VBATT – VSET ≥ 0.6V. The switcher regulates the fixed output voltage by transferring a fixed amount of energy during each cycle and modulating the frequency to control the total power delivered to the output. The converter switches only as needed to support the demand of the load current, therefore maximizing efficiency. If the load current should increase during PFM mode to more than 120 mA (typ.), the part will automatically transition into PWM mode. A 20 mA (typ.) hysteresis window exists between PFM and PWM transitions. After a transient event, the part temporarily operates in PWM mode to quickly charge or discharge the output. This is true for startup conditions or if the mode operation is changed from Forced-PWM to Auto-PFM mode (SMPS_CFG [5] toggled from 0b to 1b). Once the output reaches its target output voltage, and the load is less than 60 mA (min.), then the part will seamlessly transition into PFM mode (assuming It is not in forced bypass condition). Active Current Assist and Analog Bypass (ACB) The 3GPP time mask requirement for 2G requires high current to be sourced by the LM3263. These high currents are required for a small time during transients or under a heavy load. Over-rating the switching inductor for these higher currents would increase the solution size and is not an optimum solution. Thus, to allow an optimal inductor size for such a load, an alternate current path is provided from the input supply through the ACB pin. Once the switcher current limit ILIM,PFET,SteadyState is reached, the ACB circuit starts providing the additional current required to support the load. The ACB circuit also minimizes the dropout voltage by having the analog bypass FET in parallel with VSET. The LM3263 can provide up to 2.5A (min.) of current in bypass mode. Bypass Operation The Bypass Circuit provides an analog bypass function with very low dropout resistance (Rtot_drop = 45 mΩ typ). When SMPS_CFG [4] is set to 0b, the part will be in automatic Bypass mode which will automatically determine the amount of bypass needed to maintain voltage regulation. When the input supply voltage to the LM3263 is lowered to a level where the commanded duty cycle is higher than what the converter is capable of providing, the part will go into pulse-skipping mode. The switching frequency will be reduced to maintain a low and well behaved output voltage ripple. The analog bypass circuit will allow the converter to stay in regulation until full bypass is reached (100% duty cycle operation). The converter comes out of full bypass and back into analog bypass regulation mode with a similar reverse process. To operate the device at the Forced-Bypass mode, set REGISTER_0 to 7Fh or VSET_CTRL to FEh-FFh. Shutdown Mode The Shutdown mode is entered whenever the voltage on the VIO pin is 0V. The communications and the controls are not powered. In this mode, the current consumption is 0.02 µA (typ.). Low-Power Mode The Low-Power mode is the initial default state when VIO is applied. In this mode, the DC-DC is disabled and its SW is tri-state. The current consumption is minimized 0.225 µA (typ.). This mode can be entered by programming any one of three registers below: • Register 00h REGISTER_0 [6:0] to 00h; • Register 03h VSET_CTRL[7:0] to 00h or 01h; • Register 1Ch PM_TRIG [7:6] to 10b. Standby Mode In Standby mode, switching is stopped, and the output power FETs are placed in tri-state. The Standby mode can be entered by setting PM_TRIG [7:6] and REGISTER_0 or VSET_CTRL registers. • Register 00h REGISTER_0 [6:0] to 02h; • Register 03h VSET_CTRL [7:0] to 04h or 05h; • Register 1Ch PM_TRIG [7:6] to 00b. 14 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 LM3263 www.ti.com SNVS837 – JUNE 2013 Active Mode The Active mode is a DC-DC converter operating mode that allows the device to function, process RFFE commands, and respond to RFFE commands. This mode can be entered by setting register 1Ch PM_TRIG [7:6] to 00b. Once the device is the Active Mode, the DC-DC converter operating mode and the output voltage can be programmed by using REGISTER_0 [6:0] and VSET_CTRL[7:0] registers. Dynamic Adjustment of Output Voltage The LM3263 can be dynamically programmed the output voltage from 0.4V to 3.6V with 30 mV or 15 mV steps. REGISTER_0 [6:0] is set to 0Dh to 78h with 30 mV output voltage steps, and VSET_CTRL [7:0] is set to 1Bh to F0h with 15 mV steps. Although the output voltage can be programmed lower than 0.4V and higher than 3.6V by setting the registers, the device might suffer from larger output ripple voltage, higher current limit operation, and decreased linearity. DC-DC Operating Mode Selection Programming SMPS_CFG [5] changes the state of the converter to one of the two allowed modes of operation. SMPS_CFG [5] default is 0b and the device operates in Forced PWM mode (PWM only). Setting the register bit to 1b sets the device for automatic transition between PFM/PWM mode operation. In this mode, the converter operates in PFM mode to maintain the output voltage regulation at very light loads and transitions into PWM mode at loads exceeding 120 mA (typ). Setting the register bit to 0b sets the device for PWM mode operation. The switching operation is in PWM mode only, and the switching frequency is also 2.7 MHz (typ). The device operates in Forced-Bypass mode when SMPS_CFG [4] is set to 1b. For typical operation mode is set to Auto-PFM and Auto-Bypass modes by setting SMPS_CFG = 20h. Table 1 shows the LM3263 parameters for the given modes. Table 1. Parameters under Different Modes of Operation SMPS_CFG [5] MODE SMPS_CFG [4] BYPS IOUT Conditions Operation Mode 0 0 X Forced-PWM (1) 1 X Forced-Bypass 1 0 IOUT ≤ 60 mA PFM 1 0 60 mA < IOUT ≤ 120 mA PFM or PWM 1 0 IOUT > 120 mA PWM X (1) doesn't care Internal Synchronous Rectification The LM3263 uses an internal NFET as a synchronous rectifier to reduce rectifier forward voltage drop, thus increasing efficiency. The reduced forward voltage drop in the internal NFET synchronous rectifier significantly improves efficiency for low output voltage operation. The NFET is designed to conduct through its intrinsic body diode during the transient intervals, eliminating the need of an external diode. Current Limit The LM3263 current limit feature protects the converter during current overload conditions. Both SW and ACB pins have positive and negative current limits. The positive and negative current limits bound the SW and ACB currents in both directions. The SW pin has two positive current limits. The ILIM,PFET,SteadyState current limit triggers the ACB circuit. Once the peak inductor current exceeds ILIM,PFET,SteadyState, the ACB circuit starts assisting the switcher and provides just enough current to keep the inductor current from exceeding ILIM,PFET,SteadyState allowing the switcher to operate at maximum efficiency. Transiently a second current limit ILIM,PFET,Transient of 1.9A (typ. or 2.1 max.) limits the maximum peak inductor current possible. The output voltage will fall out of regulation only after both SW and ACB output pin currents reach their respective current limits of ILIM,PFET,Transient and ILIM,P-ACB . Timed Current Limit If the load or output short-circuit pulls the output voltage to 0.3V or lower, and the peak inductor current sustains ILIM,PFET,SteadyState more than 10 µs, the LM3263 switches to a timed current limit mode. In this mode, the internal PFET switch is turned off. After approximately 30 µs, the device will return to the normal operation. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 15 LM3263 SNVS837 – JUNE 2013 www.ti.com Thermal Overload Protection The LM3263 IC has a thermal overload protection that protects itself from short-term misuse and overload conditions. If the junction temperature exceeds 150°C, the LM3263 shuts down. Normal operation resumes after the temperature drops below 125°C. Prolonged operation in thermal overload condition may damage the device and is therefore not recommended. Startup The waveform in Figure 21 shows the startup sequence and sample condition. First, VBATT (=PVIN=SVDD=PACB) should take on a value between 2.7V and 5.5V. After VBATT is ensured to be beyond 2.7V, VIO can be set 1.8V. Next, setting PM_TRIG [7:6] to 38h will enable Active mode. Finally, VSET can be programmed to a value that corresponds to the desired output voltage. The LM3263 output voltage will then go to the programmed VSET value. To optimize the startup time and behavior of the output voltage, the LM3263 will start up in PWM mode even when the operating mode selected is Auto-PFM mode (SMPS_CFG [5] set to 1b) if the output load current is ≤ 60 mA (min.), the LM3263 will then seamlessly transition into PFM mode. Shutdown Low Power Initialization Active APT 5 Ps (min) 150 ns (min) 50 Ps max 25 Ps max VBATT t0 VBATT applied, VIO = 0V. LM3263 in Shutdown. t1 VIO applied.150 ns later LM3263 is in Low Power and RFFE configuration writes may occur. Trigger Mask Bits are set. t2 VSET is programmed and takes effect immediately. LM3263 initializes and powers up internal circuit blocks. t3 DC-DC is active in normal mode. t4 Transmit Slot Boundary. DC-DC output settled (95%). VIO SDATA 3.4V 0V VOUT SW t0 t1 t2 RFFE write PM_TRIG (Reg 1Ch = 38h) RFFE write SMPS_CFG= auto PFM (Reg 01h = 20h) t3 t4 RFFE write VSET = DC-DC VOUT (Reg 03h = E3h) Figure 21. Non-Triggered Startup Sequence 16 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 LM3263 www.ti.com SNVS837 – JUNE 2013 Shutdown Low Power Initialization Active APT 150 ns (min) 50 Ps max 5 Ps (min) 25 Ps max VBATT t0 VBATT applied, VIO = 0V. LM3263 in Shutdown. t1 VIO applied.150ns later LM3263 is in Low Power, and RFFE configuration writes may occur. t2 Trigger is programmed. VSET and SMPS_CFG loaded from shadow registers. LM3263 initializes and powers up internal circuit blocks. t3 DC-DC is active in normal mode. t4 Transmit Slot Boundary. DC-DC output settled (95%). VIO SDATA 3.4V VOUT 0V SW t0 t1 t3 t2 RFFE write VSET = DC-DC VOUT (Reg 03h = E3h) RFFE write SMPS_CFG= auto PFM (Reg 01h = 20h) t4 RFFE write PM_TRIG (Reg 1Ch = 02h) Figure 22. Triggered Startup Sequence RFFE Interface The Digital Control Serial Bus Interface provides MIPI RF Front-End Control Interface compatible access to the programmable functions and registers on the device. The LM3263 uses a three-pin digital interface; two for bidirectional communications between the IC’s connected to the bus, along with an interface voltage reference VIO that also acts as asynchronous enable and reset. When VIO voltage supply is applied to the Bus, it enables the Slave interface and resets the user-defined Slave registers to the default settings. The LM3263 can be set to shutdown mode via the asynchronous VIO signal or low-power mode by setting the appropriate register via Serial Bus Interface. The two communication lines are serial data (SDATA), and clock (SCLK). SCLK and SDATA must be held low until VIO is present. The LM3263 connects as slave on a single-master Serial Bus Interface. The SDATA signal is bidirectional, driven by the Master or a Slave. Data is written on the rising edge (transition from logical level zero to logical level one) of the SCLK signal by both Master and Slaves. Master and Slave both read the data on the falling edge (transition from logical level one to logical level zero) of the SCLK signal. A logic-low level applied to VIO signal powers off the digital interface. Supported Command Sequences SCLK SA3 SDATA SSC SA2 SA1 SA0 1 D6 D5 D4 Slave Address D3 Data D2 D1 D0 P Parity 0 Bus Park Signal driven by Master. Signal not driven; pull-down only. For reference only. Figure 23. Register 0 Write Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 17 LM3263 SNVS837 – JUNE 2013 www.ti.com SCLK A SDATA SA3 SA2 SA1 SA0 0 SSC 1 0 A4 A3 A2 A1 A0 P Register Write Command Frame SCLK A SDATA P D7 D6 D5 D4 D3 D2 D1 D0 P 0 Bus Park Data Frame Signal driven by Master. Signal not driven; pull-down only. For reference only. Figure 24. Register Write SCLK A SDATA SA3 SA2 SA1 SA0 0 SSC 1 1 A4 A3 A2 A1 A0 P Register Read Command Frame SCLK A SDATA P 0 Bus Park D7 D6 D5 D4 D3 D2 Data Frame (from Slave) D1 D0 P 0 Bus Park Signal driven by Master. Signal driven by Slave. Signal not driven; pulldown only. For reference only. Figure 25. Register Read Device Enumeration The interface component recognizes broadcast Slave Address (SID) of 0000b and is configured, via internal interface signals, with a Unique SID address (USID) and a Group SID address (GSID). The USID is set to 0100b and GSID set to 0000b. The register-set component will typically set the USID to a fixed value; however, it is also possible to select a second pre-set USID if a second LM3263 is needed on the board. This second User ID can be set by forcing a voltage > 1.36V at the GPO1 pin for USID = 0101b. Please refer to GPO1 for detailed usage and programmability of the USID. The USID can also be re-programmed via the standard protocol for programming the RFFE as defined in the RFFE spec. The USID should not be programmed to the reserved broadcast slave id of 0000b. A value of 0000b will be ignored by the device. 18 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 LM3263 www.ti.com SNVS837 – JUNE 2013 GPO1 GPO1 has two functions. The first function is an input to select the default USID and the second function is to be a general purpose output. The state of the GPO1 pin at startup determines the default USID. If the GPO1 pin is low or left floating at startup, the USID is 0100b. If the GPO1 pin is high at startup, the USID is 0101b. One method to set the GPO1 pin high is to place a pull-up resistor (39KΩ) on the GPO1 pin. When the GPO1 pin is used as the general purpose output, GPO_CTRL [6] needs to be set to 1b. Once it has been enabled as the general purpose output, GPO_CTRL [7] will determine the state driven to the GPO1 pin. The pull-up resistor needs to be placed either as an external pull-up on the board or through an internal pull-up on the general purpose input which is tied to the GPO1 pin. The GPO1 pin can be left floating if unused. Trigger Registers Trigger registers are indicated in the RFFE register map by the “Trigger” column. All trigger registers are tied to each of the TRIG_0-2 register bits. When a trigger register is written directly across the RFFE interface, the new value will not be loaded into the register until one of the TRIG0-2 register bits is written with a ‘1’ and the associated TRIG_MSK_x bit for that TRIG_x is not set. (Triggers are ignored when their associated masking bit is set.) When all 3 TRIG_MSK_0-2 bits are set (all triggers are masked) the trigger feature is disabled and any trigger registers will be loaded directly at the time of the write operation to that register rather than waiting for a trigger event to update. Control Interface Timing Parameters TSCLKOTR TSCLKOTR TSCLKOH TSCLKOL VOHmin SCLK VOLmax Figure 26. Clock Timing VTPmax SCLK VTNmin TD TSDATAOTR TD TS TH TSDATAOTR TS TH VTPmax SDATA VTNmin Figure 27. Setup and Hold Timing Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 19 LM3263 SNVS837 – JUNE 2013 20 www.ti.com Symbol Parameter Min TCLK Clock Time Period 38.5 TSCLKOH Clock High Time 11.25 TSCLKOL Clock Low Time 11.25 TS Data Setup Time 1 TH Data Hold Time 5 TD-Forward Time for Data Output Valid from SCLK rising edge TD-Reverse Time for Data Output Valid from SCLK rising edge TSDATAOTR SDATA Output Transition (Rise/Fall) Time Submit Documentation Feedback Typ Max Units ns 10.25 22 2.1 6.5 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 LM3263 www.ti.com SNVS837 – JUNE 2013 PROGRAMMABLE REGISTERS Addr Register Contents 00h REGISTER _0 Bits Function Default Trigger* R/W Description 7 RSVD 0 N/A N/A Reserved R/W Register 00h interacts with Register 03h. DC-DC converter mode and output voltage control bits 00h : Low-Power Mode 01h : Reserved 02h : Standby Mode 03h to 7Eh : Active Mode, Setting Output Voltage is enabled. Output voltage can be set 0.4V to 3.6V by 0Dh to 78h with 30 mV steps 7Fh : Forced-Bypass Mode VSET[7:1] (dec) = Desired VOUT / 0.03 (round up decimals), then converts a decimal number to hexadecimal. 6:0 VSET[7:1] 00h Yes Bits Function Default Trigger* R/W 7:6 RSVD 0 N/A N/A Reserved 5 MODE 0 Yes R/W Switching mode select bit 0: Forced PWM Mode (PWM only) 1: Auto-PFM Mode (PFM/PWM) 4 BYPS 0 Yes R/W Forced bypass bit 0: Auto-Bypass Mode 1: Forced-Bypass Mode 3:0 RSVD 0h N/A N/A Reserved Bits Function Default Trigger* 01h SMPS_CFG 02h Description GPO_CTRL R/W Description 7 GPO1_OUT 0 Yes R/W GPO1 output control 0: Low state 1: High state 6 GPO1_MODE 0 Yes R/W GPO1 Mode Selection 0 : General Purpose Output disabled 1 : General Purpose output driven by GPO1_OUT. 5:0 RSVD 00h N/A N/A Reserved 03h VSET_CTRL Bits Function Default Trigger* 7:0 VSET[7:0] 00h Yes Bits Function Default Trigger* 1Ah R/W Description R/W DC-DC converter mode and output voltage fine control bits 00h-01h : Low-Power Mode 02h-03h : Reserved 04h-05h : Standby Mode 06h to FDh : Active Mode, Setting Output Voltage is enabled. Output voltage can be set 0.4V to 3.6V by 1Bh to F0h with 15 mV steps FEh-FFh : Forced Bypass Mode. VSET[7:0] (dec) = Desired VOUT / 0.015 (round up decimals), then converts a decimal number to hexadecimal. RFFE_STATUS 7 6 5 4 R/W Description SWRESET 0 No Software Reset. A write to '1' will cause all registers except for USID to be reset. Will always read back '0'. CMD_FRAME_PERR 0 No Set if parity error detected in command frame. Cleared on read. Write will have no effect on this bit. CMD_LENGTH_ERR 0 No Error when transaction interrupted by new SSC. Cleared on read. Write will have no effect on this bit. RSVD 0 No Reserved Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 21 LM3263 SNVS837 – JUNE 2013 www.ti.com Addr Register Contents 3 2 1 0 DATA_FRAME_PERR 0 No Write data frame parity error. Cleared on read. Write will have no effect on this bit. RD_UNUSED_REG 0 No Read command to an invalid register. Cleared on read. Write will have no effect on this bit. WR_UNUSED_REG 0 No Write command to an invalid register. Cleared on read. Write will have no effect on this bit. BID_GID_ERR 0 No Read command with a broadcast ID or Group ID. Cleared on read. Write will have no effect on this bit. 1Bh GROUP_ID Bits Function Default Trigger* R/W 7:4 RSVD 0h N/A N/A 3:0 GSID 0h No Bits Function Default Trigger* Description Reserved Group Slave ID. 1Ch PM_TRIG R/W 7:6 PWR_MODE 10b No 5 TRIG_MSK_2 0 No Mask bit for Trigger 2. Broadcast write to this bit is ignored. 4 TRIG_MSK_1 0 No Mask bit for Trigger 1. Broadcast write to this bit is ignored. 3 TRIG_MSK_0 0 No Mask bit for Trigger 0. Broadcast write to this bit is ignored. 2 TRIG_2 0 No Write to a '1' loads trigger registers with last written value TRIG_MSK_2 is cleared. Write to '0' has no affect. 1 TRIG_1 0 No Write to a '1' loads trigger registers with last written value TRIG_MSK_1 is cleared. Write to '0' has no effect. 0 TRIG_0 0 No Write to a '1' loads trigger registers with last written value TRIG_MSK_0 is cleared. Write to '0' has no effect. Bits Function Default Trigger* 1Dh R/W Description Power Mode Bits. 00b = Active Mode 01b = Restore default settings 10b = Low-Power Mode 11b = Reserved PRODUCT ID 7:0 PRODUCT_ID 82h No Bits Function Default Trigger* 1Eh R/W R Description Product Identification Bits. Product ID default value cannot be overwritten. MANUFACTURER ID, LSB R/W 7:0 MANID[7:0] 02h No Bits Function Default Trigger* R/W 7:6 RSVD 00b N/A N/A 5:4 MANID[5:4] 01b No R 1Fh R Description Manufacturer Identification, bits 7:0. Manufacturer ID default value cannot be overwritten. MANUFACTURER ID, MSB 3:0 USID 010xb No Description Reserved Manufacturer Identification, bits 5:4. Manufacturer ID default value cannot be overwritten. Unique Slave Identifier. Bit 0 (x) of USID is tied to the state of the GPO1 pin. 0100b: GPO1= Low state or floating 0101b: GPO1= High state * Trigger=Yes: When all PM_TRIG.TRIG_MSK_* bits are set '1', REGISTER_0 will be written immediately during a write operation. If any PM_TRIG.TRIG_MSK_* bits are cleared ('0'), REGISTER_0 will not be updated to the new value after a write operation only after an unmasked PM_TRIG.TRIG_* bit is subsequently written to a '1'. 22 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 LM3263 www.ti.com SNVS837 – JUNE 2013 APPLICATION INFORMATION Recommended External Components Inductor Selection A 1.5 µH inductor is needed for optimum performance and functionality of the LM3263. In the case of 2G transmission current bursts, the effective overall RMS current requirements are reduced. Therefore, please consult with the inductor manufacturers to determine if some of their smaller components will meet your application needs even though the classical inductor specification does not appear to meet the LM3263 RMS current specifications. The LM3263 automatically manages the inductor peak and RMS current (or steady-state current peak) through the SW pin. The SW pin has two positive current limits. The first is the 1.45A typical (or 1.65A maximum) overcurrent protection. It sets the upper steady-state inductor peak current (as detailed in the Electrical Characteristics Table ILIM,PFET,SteadyState). It is the dominant factor limiting the inductors ISAT requirement. The second is an over-limit current protection. It limits the maximum peak inductor current during large signal transients (i.e., < 20 µs) to 1.9A typical (or 2.1A maximum). A minimum inductance of 0.3uH should be maintained at the second current limit. The ACB circuit automatically adjusts its output current to keep the steady-state inductor current below the steady-state peak current limit. Thus, the inductor RMS current will effectively always be less than the ILIM,PFET,SteadyState during the transmit burst. In addition, as in the case with 2G where the output current comes in bursts, the effective overall RMS current would be much lower. For good efficiency, the inductor’s resistance should be less than 0.2Ω; low DCR inductors (<0.2Ω) are recommended. Table 2 suggests some inductors and their suppliers. Table 2. Suggested Inductors and Their Suppliers Model DFE201610C1R5N (1285AS-H-1R5M) Vendor Dimensions (mm) TOKO ISAT (30% drop in inductance) DCR 2.2A 120 mΩ LQM2MPN1R5MG Murata 2.0A 110 mΩ MAKK2016T1R5M Taiyo-Yuden 1.9A 115 mΩ TDK 1.4A 151 mΩ VLS201610MT-1R5N 2.0 x 1.6 x 1.0 Capacitor Selection The LM3263 is designed to use ceramic capacitors for its input and output filters. Use a 10 µF capacitor for the input and approximately 10 µF actual total output capacitance. Capacitor types such as X5R, X7R are recommended for both filters. These provide an optimal balance between small size, cost, reliability and performance for cell phones and similar applications. Table 3 lists suggested part numbers and suppliers. DC bias characteristics of the capacitors must be considered while selecting the voltage rating and case size of the capacitor. Smaller case sizes for the output capacitor mitigate piezo-electric vibrations of the capacitor when the output voltage is stepped up and down at fast rates. However, they have a bigger percentage drop in value with dc bias. For even smaller total solution size, 0402 (1005) case size capacitors are recommended for filtering. Use of multiple 2.2 µF or 1µF capacitors can also be considered. For RF Power Amplifier applications, split the output capacitor between DC-DC converter and RF Power Amplifiers: 10 µF (COUT1) + 4.7 µF (COUT2) + 3 x 1.0 µF (COUT3) is recommended. The optimum capacitance split is application dependent, and for stability the actual total capacitance (taking into account effects of capacitor DC bias, temperature de-rating, aging and other capacitor tolerances) should target 10 µF with 2.5V DC bias (measured at 0.5 VRMS). Place all the output capacitors very close to the respective device. A high-frequency capacitor (3300 pF) is highly recommended to be placed next to COUT1. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 23 LM3263 SNVS837 – JUNE 2013 www.ti.com Table 3. Suggested Capacitors and Their Suppliers Capacitance Model Size (WxL) (mm) Vendor 10 µF GRM185R60J106M 1.6 x 0.8 Murata 10 µF CL05A106MP5NUN 1.0 x 0.5 Samsung 4.7 µF CL05A475MP5NRN 1.0 x 0.5 Samsung 1.0 µF CL03A105MP3CSN 0.6 x 0.3 Samsung 1.0 µF C0603X5R0J105M 0.6 x 0.3 TDK 3300 pF GRM022R60J332K 0.4 x 0.2 Murata DSBGA Package Assembly And Use Use of the DSBGA package requires specialized board layout, precision mounting, and careful re-flow techniques, as detailed in Texas Instruments Application Note 1112 (SNVA009). Refer to the section Surface Mount Technology (SMD) Assembly Considerations. For best results in assembly, alignment ordinals on the PC board should be used to facilitate placement of the device. The pad style used with DSBGA package must be the NSMD (non-solder mask defined) type. This means that the solder-mask opening is larger than the pad size. This prevents a lip that otherwise forms if the solder-mask and pad overlap from holding the device off the surface of the board and interfering with mounting. See Application Note 1112 for specific instructions how to do this. The 16-bump package used for the LM3263 has 265 micron (nominal) solder balls and requires 0.225 mm pads for mounting the circuit board. The trace to each pad should enter the pad with a 90º entry angle to prevent debris from being caught in deep corners. Initially, the trace to each pad should be about 0.142 mm wide, for a section approximately 0.127 mm long, as a thermal relief. Then each trace should neck up or down to its optimal width. An important criterion is symmetry to insure the solder bumps on the LM3263 re-flow evenly and that the device solders level to the board. In particular, special attention must be paid to the pads for bumps A1, A3, B1, and B3 since PGND, PVIN and BGND are typically connected to large copper planes; inadequate thermal relief can result in inadequate re-flow of these bumps. The DSBGA package is optimized for the smallest possible size in applications with red-opaque or infraredopaque cases. Because the DSBGA package lacks the plastic encapsulation characteristic of larger devices, it is vulnerable to light. Backside metallization and/or epoxy coating, along with front-side shading by the printed circuit board, reduce this sensitivity. However, the package has exposed die edges that are sensitive to light in the red and infrared range shining on the package’s exposed die edges. 24 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 LM3263 www.ti.com SNVS837 – JUNE 2013 PCB LAYOUT CONSIDERATIONS 1. Overview PC board layout is critical to successfully designing a DC-DC converter into a product. A properly planned board layout optimizes the performance of a DC-DC converter and minimizes effects on surrounding circuitry while also addressing manufacturing issues that can have adverse impacts on board quality and final product yield. 2. PCB Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. Erroneous signals could be sent to the DC-DC converter IC, resulting in poor regulation or instability. Poor layout can also result in re-flow problems leading to poor solder joints between the DSBGA package and board pads. Poor solder joints can result in erratic or degraded performance of the converter. Energy Efficiency Minimize resistive losses by using wide traces between the power components and doubling up traces on multiple layers when possible. EMI By its very nature, any switching converter generates electrical noise. The circuit board designer’s challenge is to minimize, contain, or attenuate such switcher-generated noise. A high-frequency switching converter, such as the LM3263, switches Ampere level currents within nanoseconds, and the traces interconnecting the associated components can act as radiating antennas. The following guidelines are offered to help to ensure that EMI is maintained within tolerable levels. To help minimize radiated noise: • Place the LM3263 DC-DC converter, its input capacitor, and output filter inductor and capacitor close together, and make the interconnecting traces as short as possible. • Arrange the components so that the switching current loops curl in the same direction. During the first half of each cycle, current flows from the input filter capacitor, through the internal PFET of the LM3263 and the inductor, to the output filter capacitor, then back through ground, forming a current loop. In the second half of each cycle, current is pulled up from ground, through the internal synchronous NFET of the LM3263 by the inductor, to the output filter capacitor and then back through ground, forming a second current loop. Routing these loops so the current curls in the same direction prevents magnetic field reversal between the two halfcycles and reduces radiated noise. • Make the current loop area(s) as small as possible. Interleave doubled traces with ground planes or return paths, where possible, to further minimize trace inductances. • The Active Current Assist and Bypass (ACB) trace should be kept short and routed directly from ACB pads to the VOUT pad at the inductor. To help minimize conducted noise in the ground-plane: • Reduce the amount of switching current that circulates through the ground plane: Connect PGND bump of the LM3263 and its input filter capacitor together using generous component-side copper fill as a pseudo-ground plane. Then connect this copper fill to the system ground-plane (if one is used) by multiple vias located at the input filter capacitor ground terminal. The multiple vias help to minimize ground bounce at the LM3263 by giving it a low-impedance ground connection. Do not route the PGND pad directly to the RF ground plane. • An additional high frequency capacitor in 01005 (0402 mm) case size is also recommended between PVIN and the RF ground plane. Do not connect to PGND directly. • For optimum RF performance connect the output capacitor ground to the RF ground or System ground plane. Do not connect to PGND directly. To help minimize coupling to the DC-DC converter's own voltage feedback trace: • Route noise sensitive traces, such as the voltage feedback path (FB), as directly as possible from the DC-DC converter FB pad to the VOUT pad of the output capacitor, but keep it away from noisy traces between the power components. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 25 LM3263 SNVS837 – JUNE 2013 www.ti.com To help minimize noise coupled back into power supplies: • Use a star connection to route from the VBATT power input to DC-DC converter PVIN and to VBATT_PA. • Route traces for minimum inductance between PVIN pads and the input capacitor(s). • Route traces to minimize inductance between the input capacitors and the ground plane. • Maximize power supply trace inductance(s) to reduce coupling among function blocks. • Inserting a ferrite bead in-line with power supply traces can offer a favorable tradeoff in terms of board area, by attenuating noise that might otherwise propagate through the supply connections, allowing the use of fewer bypass capacitors. 3. Manufacturing Considerations The LM3263 package employs a 16-bump (4x4) array of 0.24 mm solder balls, with a 0.4 mm pad pitch. A few simple design rules will go a long way to ensuring a good layout. • Pad size should be 0.225 ± 0.02 mm. Solder mask opening should be 0.325 ± 0.02 mm. • As a thermal relief, connect to each pad with 9 mil wide, 6 mil long traces and incrementally increase each trace to its optimal width. Symmetry is important to ensure the solder bumps re-flow evenly. Refer to TI Application Note AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009). 4. LM3263 RF Evaluation Board VBATT 2.7V to 5.5V 0.1 µF 10 µF PVIN PACB SVDD FB VIO 1.8V RFFE Master ACB Output Voltage 0.4V to 3.6V 1.5 µH SCLK LM3263 SW SDATA 10 µF 3.3 nF 4.7 µF VBATT_PA GPO1 BGND SGND MMMB VCC_PA PGND 1.0 µF 3G/4G VCC_PA PA PA Figure 28. Simplified LM3263 RF Evaluation Board Schematic 26 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 LM3263 www.ti.com SNVS837 – JUNE 2013 Board Layout Overview LM3263 DC-DC Converter 3G/4G PA Multi-Mode Multi-Band PA Figure 29. Top View of RF Evaluation board with PAs Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 27 LM3263 SNVS837 – JUNE 2013 www.ti.com DC-DC Converter VBATT Input from board edge RF bypass to RF GND Plane Inductor Input Cap (RF) Output Cap (RF) RF bypass to RF GND Plane Output Cap (Main) Input Cap (Main) LM3263 Inductance Minimized Input Cap ground side is connected to PGND pin. PGND island should be isolated on the top layer andconnected to system ground plane directly with multi vias. Figure 30. Top Layer 28 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 LM3263 www.ti.com SNVS837 – JUNE 2013 DC-DC Converter, cont'd Inductor Input Cap (RF) Output Cap (RF) Output Cap (Main) PVIN can be connected to CIN with multi-vias if Power plane is in an innner plane. LM3263 FB trace (low current) Input Cap (Main) S VDD Connection to CIN PACB Connection to CIN Figure 31. Board Layer 2 – FB, SVDD, PACB, PVIN Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 29 LM3263 SNVS837 – JUNE 2013 www.ti.com DC-DC Converter, cont'd Control Traces Routed Away From PowerTraces Same net, but should be kept isolated on this layer Inductor Input Cap (RF) Output Cap (RF) Output Cap (Main) SW : Short, 20 mil min width LM3263 ACB : 20 mil min width. ACB trace can be placedin other layer if more layers are available. Input Cap (Main) Figure 32. Board Layer 3 – SW, ACB 30 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 LM3263 www.ti.com SNVS837 – JUNE 2013 DC-DC Converter, cont'd VCC_PA: Connects Directly To Cout at This Point Input Cap (RF) Inductor Output Cap (RF) Output Cap (Main) Input Cap (Main) LM3263 VCC_PA: Wide, High-Current Trace Figure 33. Board Layer 4 – VCC_PA, SYSTEM GND PLANE Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 31 LM3263 SNVS837 – JUNE 2013 www.ti.com DC-DC Converter, cont'd VBATT: Wide, High -Current Trace Inductor Input Cap (RF) Output Cap (RF) Output Cap (Main) Input Cap (Main) LM3263 Figure 34. Board Layer 5 – VBATT Connection 32 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 LM3263 www.ti.com SNVS837 – JUNE 2013 Star Connection between VBATT, DC-DC Converter, and PA VBATT Star Connection VBATT Connection for DC -DC Converter VBATT BUS Connection for PA(s) Figure 35. Multiple Board Layers – VBATT Supply Star Connection Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 33 LM3263 SNVS837 – JUNE 2013 www.ti.com VBATT Star Connection It is critically important to use a “Star” connection from VBATT supply to the LM3263 PVIN and from VBATT to PA modules as implementing a “daisy chain” supply connection may add noise to the PA output. Star Connection at VBATT VBATT_PA VIN DC-DC VBATT_PA * * VIN VBATT PA PA + LM3263 _ * Proper decoupling on VBATT_PA is Strongly recommended. Figure 36. VBATT Star Connection on PCIN and VBATT_PA 34 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3263 PACKAGE OPTION ADDENDUM www.ti.com 4-Jul-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) LM3263TME/NOPB ACTIVE DSBGA YFQ 16 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -30 to 90 S61 LM3263TMX/NOPB ACTIVE DSBGA YFQ 16 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -30 to 90 S61 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 2-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM3263TME/NOPB DSBGA YFQ 16 250 178.0 8.4 LM3263TMX/NOPB DSBGA YFQ 16 3000 178.0 8.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2.08 2.08 0.76 4.0 8.0 Q1 2.08 2.08 0.76 4.0 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 2-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM3263TME/NOPB DSBGA YFQ LM3263TMX/NOPB DSBGA YFQ 16 250 210.0 185.0 35.0 16 3000 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA YFQ0016xxx D 0.600±0.075 E TMD16XXX (Rev A) D: Max = 2.049 mm, Min =1.989 mm E: Max = 2.049 mm, Min =1.989 mm 4215081/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. 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