TCC-103 Three-Output PTIC Control IC Introduction ON Semiconductor’s PTIC Controller IC is a three-output high voltage digital to analog control IC specifically designed to control and bias ON Semiconductor’s Passive Tunable Integrated Circuits (PTICs). These tunable capacitive circuits are intended for use in mobile phones and dedicated RF tuning applications. The implementation of ON Semiconductor’s tunable circuits in mobile phones enables significant improvement in terms of antenna radiated performance. The tunable capacitors are controlled through a bias voltage ranging from 2 V to 20 V. The TCC−103 high-voltage PTIC control IC has been specifically designed to cover this need, providing three independent high-voltage outputs that control up to three different tunable PTICs in parallel. The device is fully controlled through a multi-protocol digital interface. www.onsemi.com CSP16, 2.10x1.90 CASE 568AE MARKING DIAGRAM TCCx ALYW Features • Controls ON Semiconductor’s PTIC Tunable Capacitors and RF Tuners • Compliant with Timing Needs of Cellular and Other Wireless System • • • • • Requirements Integrated Boost Converter with 3 Programmable Outputs (Up To 24 V) Low Power Consumption Auto-detection of SPI (30- or 32-bit) or MIPI RFFE Interfaces (1.2 V or 1.8 V) Available in WLCSP (RDL Ball Array) and for Stand-alone or Module Integration These are Pb−Free Devices CSP16 TCC x A L Y W O = Product Code = MIPI ID = Assembly Location = Wafer Lot Code = Year Code = Week Code = Pin 1 Marker ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 21 of this data sheet. Typical Applications • Multi-band, Multi-standard, Advanced and Simple Mobile Phones • Tunable Antenna Matching Networks • Compatible with Closed Loop and Open-loop Antenna Tuner Applications © Semiconductor Components Industries, LLC, 2016 May, 2016 − Rev. 9 1 Publication Order Number: TCC−103/D TCC−103 L_BOOST VHV GND_BOOST VREG BOOSTER AVDD REGULATOR BANDGAP vio_oi VREG POR bias_start/vreg_start GNDA 4 BIT DAC VIO POR VIO REGISTERS GNDIO INTERFACE LEVEL SHIFTER CS CLK 7 7 BIT DAC OUT A 7 7 BIT DAC OUT B 7 7 BIT DAC OUT C por_vreg START REFERENCE TRIG RC OSC OTP DATA ATEST Figure 1. HVDAC Functional Block Diagram www.onsemi.com 2 VIO AVDD VREG VHV TCC−103 RDL Pin Out Table 1. PIN FUNCTION DESCRIPTIONS Bump Name Type Description A1 VREG Analog Output VREG Capacitor A2 ATEST Analog Output Test Pin (Ground in Application) A3 GND_BOOST Power Boost Ground A4 VHV Analog HV I/O Boost High Voltage Output B1 OUTB Analog HV Output High Voltage Output B B2 OUTC Analog HV Output High Voltage Output C B3 AVDD Power Analog Supply B4 L_BOOST Analog HV Output Boost Inductor C1 OUTA Analog HV Output High Voltage Output A C2 GND_DIG Power Digital Ground C3 TRIG Digital I/O Trigger Signal Input (Note 1) C4 GND_REF Power Analog Ground D1 VIO Power IO Reference Supply D2 DATA Digital I/O RFFE SDATA/SPI_DATA D3 CLK Digital Input RFFE SCLK/SPI CLK D4 CS Digital Input SPI_CS (Ground for MIPI RFFE) 1. To be grounded when not in use. RDL Ball Array Package Footprint 2050 mm ±10 mm 1850 mm ±10 mm TCCx 7LYW A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 D1 D2 D3 D4 Figure 2. Ball Array Footprint − Top View www.onsemi.com 3 TCC−103 Electrical Performance Specifications Table 2. ABSOLUTE MAXIMUM RATINGS Symbol AVDD Parameter Rating Unit Analog Supply Voltage −0.3 to +6.0 V VIO IO Reference Supply Voltage −0.3 to +3.6 V VI/O Input Voltage Logic Lines (DATA, CLK, CS) −0.3 to VIO +0.3 V VHV VHV Maximum Voltage −0.3 to 30 V 2,000 V 200 V −55 to +150 °C +110 °C VESD (HBM) Human Body Model, JESD22-A114, All I/O VESD (MM) Machine Model, JESD22-A115 TSTG TAMB_OP_MAX Storage Temperature Max Operating Ambient Temperature without Damage Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Table 3. RECOMMENDED OPERATING CONDITIONS Rating Symbol Parameter Min Typ Max Unit TAMB_OP Operating Ambient Temperature −30 − +85 °C TJ_OP Operating Junction Temperature −30 − +125 °C AVDD Analog Supply Voltage 2.3 − 5.5 V IO Reference Supply Voltage 1.1 − 3.0 V VIO Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. Table 4. DC CHARACTERISTICS (TA = −30 to +85°C; VOUTX = 15 V for each output; 2.3 V < AVDD < 5.5 V; 1.1 V < VIO < 3.0 V; RLOAD = equivalent series load of 5.6 kW and 2.7 nF; CHV = 22 nF; LBOOST = 15 mH; TRIG pin grounded; unless otherwise specified) Parameter Min Typ Max Unit AVDD Supply Current − − 0.8 mA VIO Supply is Low L_BOOST Leakage − − 1 mA VIO Supply is Low Battery Current − − 1 mA VIO Supply is Low Symbol Comment Shutdown Mode IAVDD IL_BOOST IBATT IVIO VIO Supply Current −1 − 1 mA VIO Supply is Low ICLK CLK Leakage −1 − 1 mA VIO Supply is Low IDATA DATA Leakage −1 − 1 mA VIO Supply is Low Average Battery Current, 3 Outputs Actively Switching 16 V for 1205 ms to 2 V for 1705 ms to 8V for 1705 ms − 980 1,290 mA At VHV = 20 V AVDD = 3.3 V IBATT_SS0 Average Battery Current, 3 Outputs @ 0 V Steady State − 590 830 mA At VHV = 20 V AVDD = 3.3 V IBATT_SS2 Average Battery Current, 3 Outputs @ 2 V Steady State − 610 860 mA At VHV = 20 V AVDD = 3.3 V IBATT_SS16 Average Battery Current, 3 Outputs @ 20 V Steady State − 780 1,020 mA At VHV = 20 V AVDD = 3.3 V Average Inductor Current, 3 Outputs Actively Switching 20 V for 1205Ăms to 2 V for 1705 ms to 8 V for 1705 ms − 730 1,000 mA At VHV = 20 V AVDD = 3.3 V IL_BOOST_SS0 Average Inductor Current, 3 Outputs @ 0 V Steady State − 350 550 mA At VHV = 20 V AVDD = 3.3 V IL_BOOST_SS2 Average Inductor Current, 3 Outputs @ 2 V Steady State − 380 570 mA At VHV = 20 V AVDD = 3.3 V Active Mode IBATT IL_BOOST www.onsemi.com 4 TCC−103 Table 4. DC CHARACTERISTICS (continued) (TA = −30 to +85°C; VOUTX = 15 V for each output; 2.3 V < AVDD < 5.5 V; 1.1 V < VIO < 3.0 V; RLOAD = equivalent series load of 5.6 kW and 2.7 nF; CHV = 22 nF; LBOOST = 15 mH; TRIG pin grounded; unless otherwise specified) Symbol Parameter Min Typ Max Unit Comment Average Inductor Current, 3 Outputs @ 20 V Steady State − 550 750 mA At VHV = 20 V AVDD = 3.3 V IVIO_INACT VIO Average Inactive Current − − 3 mA VIO is High, No Bus Activity IVIO_ACTIVE VIO Average Active Current − − 250 mA VIO = 1.8 V, Master Sending Data at 26 MHz 2.05 − 2.3 V No External Load Allowed AVDD Supply Current − − 7 mA L_BOOST Leakage − − 3 mA Battery Current − − 10 mA IAVDD + IL_BOOST − − 3 mA No Bus Activity 2.0 − 3.3 V No External Load Allowed Active Mode (continued) IL_BOOST_SS16 VVREG Low Power Mode IAVDD IL_BOOST IBATT IVIO VIO Supply Current VVREG Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. Table 5. BOOST CONVERTER CHARACTERISTICS (AVDD from 2.3 V to 5.5 V; VIO from 1.1 V to 3.0 V; TA = –30 to +85°C; CHV = 22 nF; LBOOST = 15 mH; unless otherwise specified) Symbol Parameter Conditions Min Typ Max Unit − 9 − V VHV_min Minimum Programmable Output Voltage (Average), DAC Boost = 0h Active Mode VHV_max Maximum Programmable Output Voltage (Average), DAC Boost = Fh Active Mode Resolution Boost Voltage Resolution 4−bit DAC − n-Channel MOSFET On-Resistance IL_BOOST = 10 mA RDS(ON) IL_BOOST_LIMIT Inductor Current Limit www.onsemi.com 5 24 V 1 − V − 1.3 − W − 100 − mA TCC−103 Table 6. ANALOG OUTPUTS (OUT A, OUT B, OUT C) (AVDD from 2.3 V to 5.5 V; VIO from 1.1 V to 3.0 V; VHV = 24 V; TA = −30 to +85°C; RLOAD = ∞ unless otherwise specified) Description Parameter Min Typ Max Unit 7 − − MW Comment Shutdown Mode ZOUT OUT A, OUT B, OUT C Output Impedance DAC Disabled Active Mode VOH Maximum Output Voltage 22.0 − − V DAC A, B or C = FFh, DAC Boost = Fh, IOH < 10 mA VOL Minimum Output Voltage − − 1 V DAC A, B or C = 01h, DAC Boost = 0h to Fh, IOH < 10 mA − 6.5 10 ms 2 V to 20 V Step, Measured at VOUT = 15.2 V, RLOAD = Equivalent Series Load of 5.6 kW and 2.7 nF, Turbo Enabled OUT A, OUT B, OUT C Set In Pull−Down Mode − − 800 W DAC A, B or C = 00h, DAC Boost = 0h to Fh, Selected Output(s) is Disabled Resolution Voltage Resolution (1−bit) − 188 − mV VOFFSET Zero Scale, Least Squared Best Fit -1 − +1 LSB Slew Rate RPD Error (1 LSB = 1 Bit) -3.0 − +3.0 %VOUT Over 2 V – 18 V VO Range DNL Differential Non-linearity Least Squared Best Fit -0.9 − +0.9 LSB Over 2 V – 18 V VO Range INL Integral Non-linearity Least Squared Best Fit -1 − +1 LSB Over 2 V – 18 V VO Range ISC Over Current Protection − 35 65 mA Any DAC Output to Ground VRIPPLE Output Ripple with All Outputs at Steady State − − 10 mV RMS www.onsemi.com 6 Over 2 V – 18 V VO Range, VHV = 20 V TCC−103 Theory of Operation through the digital interface. The DAC settings can be dynamically modified and the HV outputs will be adjusted according to the specified timing diagrams. Each DAC can be individually controlled and/or switched off according to application requirements. Active mode is automatically entered from the startup mode. Active mode can also be entered from the low power mode under control software command. 4. Low Power Mode: In low power mode the serial interface is enabled, the DAC outputs are disabled and are placed in a high Z state and the boost voltage circuit is disabled. Control software can request to enter the low power mode from the active mode by sending an appropriate PWR_MODE command. The contents of all registers are maintained in the low power mode. Overview The control IC outputs are directly controlled by programming the three DACs (DAC A, DAC B, and DAC C) through the digital interface. The DACs are 8-bit DACs used in a 7-bit format. The DAC stages are driven from a reference voltage, generating an analog output voltage driving a high-voltage amplifier supplied from the boost converter (see Control IC block diagram − Figure 1). The control IC output voltages are scaled from 0 to 24 V, with 128 steps of 188 mV (2 × 24 V/255 = 0.188235 V). The nominal control IC output can be approximated to 188 mV × (DAC value). For performance optimization the boost output voltage (VHV) can be programmed to levels between 9 V and 24 V via the DAC_boost register (4 bits with 1 V steps). The startup default level for the boosted voltage is VHV = 20 V. For proper operation and to avoid saturation of the output devices and noise issues it is recommended to operate the boosted VHV voltage at least 2 V above the highest programmed VOUT voltage of any of the three outputs. When the DAC output value is set to 00h the corresponding output is disabled and the output is pulled to GND through an effective impedance of less than 800 W. AVDD Power-On Reset Upon application of AVDD the TCC−103 will be in shutdown mode. All circuit blocks are off and the chip draws only minimal leakage current. VIO Power-On Reset and Startup Conditions A high level on VIO places the chip in startup mode which provides a power on reset (POR) to the TCC−103. POR resets all registers to their default settings as described in Table 7. VIO POR also resets the serial interface circuitry. POR is not a brown-out detector and VIO needs to be brought back to a low level to enable the POR to trigger again. Operating Modes The following operating modes are available: 1. Shutdown Mode: All circuit blocks are off, the DAC outputs are disabled and placed in high Z state and current consumption is limited to minimal leakage current. The shutdown mode is entered upon initial application of AVDD or upon VIO being placed in the low state. The contents of the registers are not maintained in shutdown mode. 2. Startup Mode: Startup is only a transitory mode. Startup mode is entered upon a VIO high state. In startup mode all registers are reset to their default states, the digital interface is functional, the boost converter is activated, outputs OUT A, OUT B, and OUT C are disabled and the DAC outputs are placed in a high Z state. Control software can request a full hardware and register reset of the TCC−103 by sending an appropriate PWR_MODE command to direct the chip from either the active mode or the low power mode to the startup mode. From the startup mode the device automatically proceeds to the Active mode. 3. Active Mode: All blocks of the TCC−103 are activated and the DAC outputs are fully controlled Table 7. VIO POWER-ON RESET AND STARTUP Register Default State for VIO POR DAC Boost [1011] Comment VHV = 20 V Power Mode [01] > [00] Transitions from SHUTDOWN to STARTUP and then Automatically to ACTIVE Mode DAC Enable [000] VOUT A, B and C Disabled DAC A Output in High-Z Mode DAC B Output in High-Z Mode DAC C Output in High-Z Mode VIO Shutdown A low level at any time on VIO places the chip in shutdown mode in which all circuit blocks are off. The contents of the registers are not maintained in shutdown mode. www.onsemi.com 7 TCC−103 Table 8. VIO THRESHOLDS (AVDD from 2.3 V to 5.5 V; TA = –30 to +85°C unless otherwise specified) Description Parameter VIORST VIO Low Threshold Min Typ Max Unit − − 0.2 V Power Supply Sequencing Comment When VIO is lowered below this threshold level the chip is reset and placed into the Shutdown mode. shutdown state and draw minimum leakage currents. Upon application of VIO the chip automatically starts up using default settings and is placed in the active state waiting for a command via the serial interface. The AVDD input is typically directly supplied from the battery and thus is the first on. After AVDD is applied and before VIO is applied to the chip all circuits are in the Table 9. TIMING (AVDD from 2.3 V to 5.5 V; VIO from 1.1 V to 3.0 V; TA = –30 to +85°C; OUT A, OUT B & OUT C; CHV = 22 nF; LBOOST = 15 mH; VHV = 20 V; Turbo-Charge mode off unless otherwise specified) Parameter Description Min Typ Max Unit TPOR_VREG Internal bias settling time from Shutdown to Active mode − 50 120 ms For Info Only Time to charge CHV @ 95% of set VHV − 130 − ms For Info Only TBOOST_START Comment Startup time from Shutdown to Active mode − 180 250 ms TSET+ Output A, B, C positive settling time to within 5% of the delta voltage, equivalent series load of 5.6 kW and 2.7 nF, VOUT from 2 V to 20 V; 0Bh (11d) to 55h (85d) − 50 60 ms Voltage Settling Time Connected on VOUT A, B, C TSET− Output A, B, C negative settling time to within 5% of the delta voltage, equivalent series load of 5.6 kW and 2.7 nF, VOUT from 20 V to 2 V; 55h (85d) to 0Bh (11d) − 50 60 ms Voltage Settling Time Connected on VOUT A, B, C TSD_TO_ACT Figure 3. Output Setting Diagram www.onsemi.com 8 TCC−103 Figure 4. Startup Timing Diagram www.onsemi.com 9 TCC−103 Boost Control Due to the slow response time of the control loop, the VHV voltage may drop below the set voltage before the control loop compensates for it. In the same manner, VHV can rise higher than the set value. This effect may reduce the maximum output voltage available. Please refer to Figure 5 below. The asynchronous control reduces switching losses and improves the output (VHV) regulation of the DC/DC converter under light load, particularly in the situation where the TCC−103 only maintains the output voltages to fixed values. The TCC−103 integrates an asynchronous current control boost converter. It operates in a discontinuous mode and features spread-spectrum circuitry for Electro-Magnetic Interference (EMI) reduction. The average boost clock is 2 MHz and the clock is spread between 0.8 MHz and 3.2 MHz. Boost Output Voltage (VHV) Control Principle The asynchronous control starts the boost converter as soon as the VHV voltage drops below the reference set by the 4-bit DAC and stops the boost converter when the VHV voltage rises above the reference again. CHV Recharge CHV Discharge VHV Set VHV Delay Delay Delay Time Boost Running Figure 5. VHV Voltage Waveform High Impedance (High Z) Feature In Shutdown mode the OUT pins are set to a high impedance mode (high Z). Following is the principle of operation for the control IC: 1. The output voltage VOUT is defined by: V OUT + DAC code 255 24 V 2 (eq. 1) 2. The voltage VHV defines the maximum supply voltage of the output regulator and is set by the 4−bit DAC. 3. The maximum DC output voltage VOUT is limited to (VHV − 2 V). 4. The minimum output voltage VOUT is 1.0 V MAX. Figure 6. DAC Output Range Example A Figure 7. DAC Output Range Example B www.onsemi.com 10 TCC−103 Digital Interface 3-wire Serial Interface The control IC is fully controlled through a digital interface (DATA, CLK, CS). The digital interface automatically detects and responds to MIPI RFFE interface commands, 3-wire 30-bit Serial Interface commands or 3-wire 32-bit Serial Interface commands. Auto-detection is accomplished on a frame by frame basis. The digital interface is further described in the next sections of this document. The 3-wire serial interface operates in a synchronous write-only 3-wire slave mode. 30-bit or 32-bit message length is automatically detected for each frame. If CS changes state before all bits are received then all data bits are ignored. Data is transmitted most significant bit first and DATA is latched on the rising edge of CLK. Commands are latched on the falling edge of CS. Table 10. 3-WIRE SERIAL INTERFACE SPECIFICATION (TA = −30 to +85°C; 2.3 V < AVDD < 5.5 V; 1.1 V < VIO < 3.0 V; unless otherwise specified) Parameter Description FCLK Clock Frequency TCLK Clock Period NBIT Bits Number Min Typ Max Unit − − 26 MHz 38.4 − − ns − 30/32 − bits THIGH Clock High Time 13 − − ns Comment Auto-detection 30-bit or 32-bit TLOW Clock Low Time 13 − − ns TCSSETUP CS Set-up Time 5 − − ns 70% Rising Edge of CS to 30% Rising Edge of First Clock Cycle TCSHOLD CS Hold Time 5 − − ns 30% Falling Edge of Last Clock Cycle to 70% Falling Edge of CS TDSETUP Data Set-up Time 4 − − ns Relative to 30% of CLK Rising Edge TDHOLD Data Hold Time 4 − − ns Relative to 70% of CLK Rising Edge TSUCC CS Low Time between Successive Writes 38.4 − − ns 70% Falling Edge of CS to 70% Rising Edge of CS TSUCC CS Low Time between Successive DAC Update Writes 1,500 − − ns Time between Groups of DAC Update Reg [00000] & [00001] Writes CCLK Input Capacitance − − 5 pF CLK Pin CDATA Input Capacitance − − 8.3 pF DATA Pin CCS Input Capacitance − − 5 pF CS Pin CTRIG Input Capacitance − − 10 pF TRIG Pin VIH Input Logic Level High 0.7 × VIO − VIO + 0.3 V DATA, CLK, CS VIL Input Logic Level Low −0.3 − 0.3 × VIO V DATA, CLK, CS IIH_DATA Input Current High −2 − 10 mA DATA IIL_DATA Input Current Low −2 − 1 mA DATA IIH_CLK,CS Input Current High −1 − 10 mA CLK, CS IIL_CLK,CS Input Current Low −1 − 1 mA CLK, CS VTP_TRIG Positive Going Threshold Voltage 0.4 × VIO − 0.7 × VIO V TRIG VTN_TRIG Negative Going Threshold Voltage 0.3 × VIO − 0.6 × VIO V TRIG VH_TRIG Hysteresis Voltage (VTP – VTN) 0.1 × VIO − 0.4 × VIO V TRIG IIH_TRIG TRIG Input Current High −2 − 10 mA TRIG = 0.8 × VIO IIL_TRIG TRIG Input Current Low −2 − 1 mA TRIG = 0.2 × VIO www.onsemi.com 11 TCC−103 Figure 8. SPI 3-wire Serial Interface Signal Timing SPI Frame Length Decoding rising edges while CS is kept high. The TCC−103 will not respond to a SPI command if the length of the frame is not exactly 30 bits or 32 bits. SPI registers are write only. 30-bit or 32-bit frame length is automatically detected. The length of the frame is defined by the number of Clock SPI Frame Structure Table 11. 32 BITS FRAME: ADDRESS DECODING (1 OR 2 OR 3 OUTPUTS) H0 H1 1 1 ON Semiconductor Header R/W A12 0 1 R/W A11 A10 A9 0 1 0 Device ID A8 A7 A6 A5 A4 A3 A2 A1 A0 0 1 0 0 X X X X X Specific Device ID Register Address for Operation Table 12. 30 BITS FRAME: ADDRESS DECODING (1 OR 2 OR 3 OUTPUTS) R/W A12 0 1 R/W A11 A10 A9 A8 A7 A6 A5 A4 0 1 0 0 1 0 0 X Device ID Specific Device ID A3 A2 A1 A0 X X X X Register Address for Operation Table 13. 3-WIRE SERIAL INTERFACE ADDRESS MAP A4 A3 A2 A1 A0 Data [15:8] Data [7:0] 0 0 0 0 0 Turbo Charge Settings for DAC A, B, C DAC C 0 0 0 0 1 DAC B DAC A 0 0 1 0 0 Turbo-Charge Delay Parameters for DAC A, B, C Turbo Threshold Delay Settings for A, B, C 1 0 0 0 0 1 0 0 1 0 1 1 1 1 To 1 Mode Select + Control IC Setup Reserved www.onsemi.com 12 Reserved TCC−103 Turbo-Charge Mode voltage above or a delta voltage below the actual desired target for the TCDLY time. It is recommended that VHV be set to 24 V when using Turbo-Charge mode. For more details about programming the part in Turbo-Charge mode, refer to application note XXXX (coming soon). The TCC−103A control IC has a Turbo-Charge mode that significantly shortens the system settling time when changing programming voltages. In Turbo-Charge mode the DAC output target voltage is temporarily set to either a delta www.onsemi.com 13 TCC−103 RF Front-End Control Interface (MIPI RFFE Interface) The TCC−103 is a write-only slave device which is fully compliant to the MIPI Alliance Specification for RF Front-End Control Interface (RFFE) Version 1.10.00 26 July 2011. This device is rated at Full-Speed operation for 1.65 V < VIO < 1.95 V and at Half-Speed operation for 1.1 V < VIO < 1.65 V. When using the MIPI RFFE interface the CS pin is grounded. Table 14. MIPI RFFE INTERFACE SPECIFICATION (TA = −30 to +85°C; 2.3 V < AVDD < 5.5 V; 1.1 V < VIO < 1.95 V; unless otherwise specified) Parameter Description Min Typ Max Unit Comment FSCLK Clock Full-Speed Frequency 0.032 − 26 MHz Full-Speed Operation: 1.65 V < VIO < 1.95 V TSCLK Clock Full-Speed Period 0.038 − 32 ms Full-Speed Operation: 1.65 V < VIO < 1.95 V TSCLKIH CLK Input High Time 11.25 − − ns Full-Speed TSCLKIL CLK Input Low Time 11.25 − − ns Full-Speed FSCLK_HALF Clock Half-Speed Frequency 0.032 − 13 MHz TSCLK_HALF Clock Half-Speed Period 0.077 − 32 ms TSCLKIH CLK Input High Time 24 − − ns Half-Speed TSCLKIL CLK Input Low Time 24 − − ns Half-Speed VTP Positive Going Threshold Voltage 0.4 × VIO − 0.7 × VIO V CLK, DATA, TRIG, 1.2 or 1.8 V Bus VTN Negative Going Threshold Voltage 0.3 × VIO − 0.6 × VIO V CLK, DATA, TRIG, 1.2 or 1.8 V Bus VH Hysteresis Voltage (VTP – VTN) 0.1 × VIO − 0.4 × VIO V CLK, DATA, TRIG, 1.2 or 1.8 V Bus IIH Input Current High −2 − +10 mA TRIG, SDATA = 0.8 × VIO −1 − +10 mA SCLK = 0.8 × VIO −2 − +1 mA TRIG, SDATA = 0.2 × VIO −1 − +1 mA SCLK = 0.2 × VIO IIL Input Current Low CCLK Input Capacitance − − 5 pF CLK Pin CDATA Input Capacitance − − 8.3 pF DATA Pin CTRIG Input Capacitance − − 10 pF TRIG Pin TDSETUP DATA Setup Time 1 − − ns Full-Speed TDHOLD DATA Hold Time 5 − − ns Full-Speed TDSETUP DATA Setup Time 2 − − ns Half-Speed TDHOLD DATA Hold Time 5 − − ns Half-Speed 1,500 − − ns TSUCC Time between Successive DAC Update Writes www.onsemi.com 14 TCC−103 The control IC contains twenty−four 8−bit registers. Register content is described in Table 15. Some additional registers, implement as provision, are not described in this document. Table 15. MIPI RFFE ADDRESS MAP Register Address Description Purpose Access Type Size (Bits) 0x00 DAC Configuration (Enable Mask) High Voltage Output Enable Mask Write 7 0x01 Turbo Register DAC A, B & C Turbo-Charge Configuration DAC A, B & C Write 8 0x02 DAC A Register Used to Set Up OUT A Write 8 0x03 DAC B Register Used to Set Up OUT B Write 8 0x04 DAC C Register Used to Set Up OUT C Write 8 0x10 DAC Boost (VHV) Settings for the Boost High Voltage Write 8 0x11 Trigger Register Trigger Configuration Write 8 0x12 Turbo-Charge Delay DAC A, B, C Turbo-Charge Delay Steps DAC A, B, C Write 8 0x13 Turbo-Charge Delay DAC A, B, C Turbo-Charge Delay Multiplication DAC A, B, C Write 8 0x1C Power Mode and Trigger Register Power Mode & Trigger Control PWR_MODE [7:6] TRIG_REG [5:0] Write 8 0x1D Product ID Register Product Number * Hard Coded into ASIC (Write) 8 0x1E Manufacturer ID Register MN (10 Bits Long) Manufacturer ID[7:0] Hard Coded into ASIC (Write) 8 0x1F Unique Slave Identifier Register (USID) Spare [7:6] [5,4] = Manufacturer ID [9:8] USID [3:0] Write 8 *The two least significant bits are programmed in OTP during manufacture. www.onsemi.com 15 TCC−103 Command Sequences • Register 0 Write (used to access the Register 0 DAC Configuration - Enable Mask). Register 0 can be also be accessed using Register Write or/and Extended Register Write. • Register Write (used to access only one register at the Register 0 Write Command Sequence Command Frame. This Frame contains the Slave address, a logic one, and the seven bit word that will be written to Register 0. The Command Sequence is depicted below. • The Command Sequence starts with a Sequence Start Condition (SSC) which is followed by the Register 0 Write time) Extended Register Write (used to access a group of contiguous registers with one command bursting up to 16 bytes) Figure 9. Register 0 Write Command Sequence Table 16. MIPI RFFE COMMAND FRAME FOR REGISTER 0 WRITE COMMAND SEQUENCE Description SSC SSE & DAC Configuration 1 0 Command Frame SA [3,0] 1 SSE 0 0 DAC_A BP DAC_B DAC_C 0 P BP Register Write Command Sequence The Write Register command sequence may be used to access each register (addresses 0-31). Figure 10. Register Write Command Sequence Table 17. MIPI RFFE COMMAND FRAME FOR REGISTER 0 WRITE COMMAND SEQUENCE Description SSC Command Frame Data Frame BP Turbo Charge Settings 1 0 SA [3,0] 0 1 0 0 0 0 0 1 P Turbo Charge [7:0] P BP Register Write DAC A 1 0 SA [3,0] 0 1 0 0 0 0 1 0 P TC [8] & DAC_A [6:0] P BP Register Write DAC B 1 0 SA [3,0] 0 1 0 0 0 0 1 1 P TC [9] & DAC_B [6:0] P BP Register Write DAC C 1 0 SA [3,0] 0 1 0 0 0 1 0 0 P TC [10] & DAC_C [6:0] P BP www.onsemi.com 16 TCC−103 Extended Register Write Command Sequence If more than one byte is to be written, the register address in the Command Sequence contains the address of the first extended register that will be written to and the Slave’s local extended register address shall be automatically incremented by one for each byte written up to address 0x1F, starting from the address indicated in the Address Frame. In order to access more than one register in one sequence this message could be used. Most commonly it will be used for loading three DAC registers at the same time. The four LSBs of the Extended Register Write Command Frame determine the number of bytes that will be written by the Command Sequence. A value of 0b0000 would write one byte and a value of 0b1111 would write sixteen bytes. Figure 11. Extended Register Write Command Sequence Table 18. EXTENDED REGISTER WRITE Description Extended Register Write Turbo Charge & DAC SSC Command Frame Op Code 1 0 Data Frame SA [3,0] 0 0 0 0 Data Frame Address Frame <Byte Count> P 0 P 0 1 1 <Starting Address> 0 Data Frame 0 0 0 0 0 P 0 Data Frame 1 P BP <Data-8 Bit> P <Data-8 Bit> P <Data-8 Bit> P <Data-8 Bit> P BP Turbo Charge P DAC_A [7,0] P DAC_B [7,0] P DAC_C [7,0] P BP www.onsemi.com 17 TCC−103 IVDDA CVDDA IBATT RFILT LBOOST IIND VBATT CH CBOOST VDDA VHV L_BOOST VREG IVIO VIO VIO CVREG OUTA,B,C TCC−103 CVIO CDACA,B,C CS CLK DATA MIPI Interface Figure 12. Recommended MIPI RFFE Interface Application Schematic Table 19. RECOMMENDED EXTERNAL BOM Component Description CBOOST Boost Supply Capacitor, 10 V LBOOST Boost Inductor RFILT Decoupling Resistor, 5% CVIO VIO Supply Decoupling, 10 V Nominal Value Package (Inch) Recommended P/N 1 mF 0402 TDK: C1005X5R1A105K 15 mH 0603 TDK: VLS2010ET-150M 3.3 W 0402 Vishay: CRCW04023R30JNED 100 nF 0201 Murata: GRM033R61A104ME15D CAVDD VAVDD Supply Decoupling, 10 V 1 mF 0402 TDK: C1005X5R1A105K CVREG VVREG Supply Decoupling, 10 V 220 nF 0201 TDK: C0603X5R1A224M Boost Output Capacitor, 50 V 22 nF 0402 Murata: GRM155R71H223KA12 Decoupling Capacitor, 50 V (Note 2) 100 pF 0201 Murata: GRM0335C1H101JD01D CHV CdacA CdacB CdacC 2. Recommended for noise reduction only− not essential. www.onsemi.com 18 TCC−103 7 L Y W • 1850 mm ±10 mm TCCx 7LYW 425 mm 400 mm 2050 mm ±10 mm 400 mm = Product Code = MIPI ID (see MIPI Version Table) = Assembly Location = Wafer Lot Code = Year Code = Week Code = Pin 1 Marker 400 mm TCC x 425 mm MECHANICAL DESCRIPTION A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 D1 D2 D3 D4 325 mm 400 mm 400 mm 400 mm Pb-Free (96.8% Sn/2.6% Ag/0.6% Cu) 250 mm dia 325 mm MIPI VERSION a = 00 380 mm ±25 mm b = 01 c = 10 d = 11 Figure 13. Ball Array Package NOTE: Die dimensions include an assumed 50 mm wide sawing kerf, this kerf width is subject to change without notice. www.onsemi.com 19 580 mm TCC−103 TAPE & REEL DIMENSIONS Figure 14. WLCSP Carrier Tape Drawings www.onsemi.com 20 TCC−103 Table 20. ORDERING INFORMATION Device Package Shipping† TCC−103A−RT RDL (Pb-Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Assembly Instructions Note: It is recommended that under normal circumstances, this device and associated components should be located in a shielded enclosure. www.onsemi.com 21 TCC−103 PACKAGE DIMENSIONS CSP16, 2.1x1.90 CASE 568AE ISSUE O ÈÈ ÈÈ PIN A1 REFERENCE D A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. B DIM A A1 b D E e E 0.10 C 2X 0.10 C 2X MILLIMETERS MIN MAX 0.62 −−− 0.18 0.22 0.24 0.30 2.10 BSC 1.90 BSC 0.40 BSC TOP VIEW 0.10 C A RECOMMENDED SOLDERING FOOTPRINT* 0.05 C NOTE 3 16X SIDE VIEW SEATING PLANE A1 PACKAGE OUTLINE e b 0.05 C A B 0.03 C C A1 e D 0.40 PITCH 16X 0.25 C 0.40 PITCH B DIMENSIONS: MILLIMETERS A 1 2 3 4 BOTTOM VIEW *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. 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