LM3279 www.ti.com SNVS970A – MARCH 2013 – REVISED MAY 2013 LM3279 Buck-Boost Converter with MIPI® RFFE Interface for 3G and 4G RF Power Amplifiers Check for Samples: LM3279 FEATURES DESCRIPTION • • The LM3279 is a buck-boost DC/DC converter designed to generate output voltages above or below a given input voltage and is particularly suitable for Power Amplifiers operating from single-cell Li-Ion batteries in portable applications. 1 2 • • • • • • • • • • • MIPI® RFFE Digital Control Interface High-Efficiency PFM and PWM Modes with Internal Seamless Transition Operates from a Single Li-Ion Cell: 2.7V to 5.5V Adjustable Output Voltage: – RFFE Digital Control: 0.4V to 4.2V – Analog Control: 0.6V to 4.2V 1A Maximum Load Capability for VBATT ≥ 3.2V, VOUT = 3.6V 2.4 MHz (typ.) Switching Frequency Seamless Buck-Boost Mode Transition Fast Output Voltage Transition: 0.8V to 4.0V in 20 µs High-Efficiency: 95% typ. at VBATT = 3.7V, VOUT = 3.3V, at 300 mA Input Over-Current Limit Output Over-Voltage Clamp Internal Compensation 16-bump DSBGA Package APPLICATIONS • • • • 3G/4G Smartphones RF PC Cards Tablets, eBooks Readers Battery-Powered RF Devices The LM3279 has four modes of operation: Pulse Width Modulation (PWM), Pulse Frequency Modulation (PFM), standby, and shutdown. During normal conditions, the LM3279 operates in full synchronous PWM mode at 2.4 MHz typical switching frequency, providing seamless transitions between buck and boost operating regimes. Energy-saving PFM mode increases efficiencies and current savings during low-power RF transmission modes. For hightransmit power, the device operates in PWM buck or boost mode, whereas the device can transition between PWM and PFM modes during low-power transmit. The LM3279 can be controlled either via an included MIPI® RFFE Digital Control Interface or by using an analog control from an external MCU, offering design flexibility. The power converter topology enables minimum total solution size by using one small footprint and case size inductor and two surface mount capacitors. The LM3279 is internally compensated for buck and boost modes of operation thus providing an optimal transient response. The LM3279 is available in a small 16-bump lead-free DSBGA package of size 2.121 mm x 2.504 mm. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated LM3279 SNVS970A – MARCH 2013 – REVISED MAY 2013 www.ti.com TYPICAL APPLICATION CIRCUIT: DIGITAL CONTROL 1.5 ÛH SW2 SW1 VBATT: 2.7V to 5.5V PVIN VOUT SVIN FB X LM3279 VOUT: 0.4V to 4.2V VCON RF PA(s) EN 10 ÛF 10 ÛF VIO GPO0 2 x 0.47 ÛF (PA decoupling caps) SDATA GPO1 SCLK DGND SGND PGND BB or RFIC RF Control Bits TYPICAL APPLICATION CIRCUIT: ANALOG CONTROL 1.5 ÛH SW2 SW1 VOUT: 0.6V to 4.2V VBATT: 2.7V to 5.5V PVIN VOUT SVIN FB X LM3279 RF PA(s) VCON EN 10 ÛF 10 ÛF VIO GPO0 2 x 0.47 F (PA decoupling caps) SDATA GPO1 SCLK DGND SGND PGND BB or RFIC DAC 2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3279 LM3279 www.ti.com SNVS970A – MARCH 2013 – REVISED MAY 2013 CONNECTION DIAGRAM 1 2 3 4 A SCLK GPO0 GPO1 SVIN B SDATA VCON EN PVIN C VIO FB SGND SW1 D GND VOUT SW2 PGND Top View (Bumps Down) Figure 1. 16-Bump Thin DSBGA Package, Large Bump PIN DESCRIPTIONS Pin # Name Description A1 SCLK Digital control interface (DCON) RFFE Bus clock input. Typically connected to RFFE master on RF or Baseband IC. SCLK must be held low when VIO is not applied. B1 SDATA Digital control interface (DCON) RFFE Bus data input/output. Typically connected to RFFE master on RF or Baseband IC. SDATA must be held low when VIO is not applied. C1 VIO Digital control interface (DCON) 1.8V supply input. VIO functions as the RFFE interface reference voltage. VIO also functions as a reset and enable input to LM3279. Bypass capacitor should be connected between VIO and GND. Typically connected to voltage regulator controlled by RF or Baseband IC. When VIO = HIGH, EN shall be connected to GND. D1 GND Digital Ground. A2 GPO0 Multipurpose GPIO. When VIO = HIGH, GPO0 is a general purpose output for configuring RF front end circuitry. When the GPO0 control bit in Register 02 is set to 1, the output is driven to a 1.8V (VIO) high logic level. The output is pulled to a low logic level when the GPO0 control bit is set to 0. (Input has an internal pullup resistor.) B2 VCON Voltage Control Analog input. When EN = HIGH, VCON controls the output voltage in PWM and PFM modes. When in Digital control, VCON can be left as no connect or connected to system ground. C2 FB Feedback input to inverting input of error amplifier. Connect output voltage directly to this node at load point. D2 VOUT Regulated output voltage of LM3279. Connect this to a 10 µF ceramic output filter capacitor to GND. A3 GPO1 Multipurpose GPIO. When VIO = HIGH, GPO1 is a general purpose output for configuring RF front end circuitry. When the GPO1 control bit in Register 02 is set to 1, the output is driven to a 1.8V (VIO) high logic level. The output is pulled to a low logic level when the GPO1 control bit is set to 0. (Input has an internal pullup resistor.) B3 EN C3 SGND D3 SW2 Switch pin for Internal Power Switches M3 and M4. Connect inductor between SW1 and SW2. A4 SVIN SVIN is no connect. Analog supply is internally connected to PVIN. B4 PVIN Power MOSFET input and power current input pin. Optional low-pass filtering may help reduce radiated EMI and noise during buck and buck-boost modes. C4 SW1 Switch pin for Internal Power Switches M1 and M2. Connect inductor between SW1 and SW2. D4 PGND Enable Pin. Pulling this pin higher than 1.2V enables part to function in analog control mode. VIO must be tied to ground. Signal Ground for analog circuits and control circuitry. Power Ground for Power MOSFETs and gate drive circuitry. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3279 3 LM3279 SNVS970A – MARCH 2013 – REVISED MAY 2013 www.ti.com BLOCK DIAGRAM SVIN PVIN SW1 SW2 VOUT SMALL FET LARGE FET M6 _G GATE DRIVE CIRCUITS M1 M2 M6 M3 M5 M4 + REF FB NETWORK PFM COMPARATOR + LOGIC - 1.7A Error Amp CONTROL EN + VCON - FB INPUT OVER CURRENT PROTECTION EN ONE SHOT TIMER INTERNAL LOOP COMPENSATION M6_G XOR CLK PWM RAMP 7 VSET DAC SGND PGND RFFE DGND VIO SDATA SCLK GPO1 GPO0 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 4 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3279 LM3279 www.ti.com SNVS970A – MARCH 2013 – REVISED MAY 2013 ABSOLUTE MAXIMUM RATINGS (1) (2) −0.2V to +6.0V PVIN, VOUT to GND PGND to SGND, GND PGND−0.2V to +0.2V −0.2V to (PVIN+0.2V) w/ 6.0V max VIO, SDATA, SCLK, EN, VCON, GPO1/GPO0 to SGND, GND −0.2V to (VOUT+0.2V) w/ 6.0V max FB to PGND (PGND −0.2V) to (PVIN +0.2V) w/ 6.0V max SW1, SW2 Continuous power dissipation (3) Internally Limited Maximum operating junction temperature (TJ-MAX) +150°C −45°C to +150°C Storage temperature range Maximum lead temperature (4) (soldering) (5) ESD rating Human Body Model: (1) (2) (3) (4) (5) 1 kV Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to the potential at the GND pins. Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and disengages at TJ = 125°C (typ.). For detailed soldering specifications and information, please refer to Texas Instruments Application Note 1112: DSBGA Wafer Level Chip Scale Package (AN-1112). The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (MIL-STD-883 3015.7) OPERATING RATINGS (1) (2) Input voltage range 2.7V to 5.5V Output voltage range (digital control) 0.4V to 4.212V Recommended current load Operating ambient temperature (TA) range (1) (2) (3) 0 to 1000 mA (3) −30°C to +85°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to the potential at the GND pins. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be de-rated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). THERMAL PROPERTIES Junction-to-ambient thermal resistance (θJA), YZR0016 Package (1) (1) 55°C/W Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC standard JESD51-7. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3279 5 LM3279 SNVS970A – MARCH 2013 – REVISED MAY 2013 www.ti.com ELECTRICAL CHARACTERISTICS (1) Limits in standard typeface are for TA = TJ = 25°C. Limits in boldface type apply over the full operating ambient temperature range (−30°C ≤ TJ = TA ≤ +85°C). Unless otherwise noted, specifications apply to the LM3279 Typical Application Circuits with: PVIN = 3.8V, VIO or EN = 1.8V. Symbol Parameter Conditions Min Typ VSET = 0Bh 0.35 0.40 0.45 VCON = 0.167V 0.43 0.5 0.570 VSET = 75h 4.122 4.212 4.302 4.11 4.2 4.29 1.4 2.0 mA 2.0 µA VFB,MIN Minimum FB voltage VFB,MAX Maximum FB voltage IQ_PWM DC bias current in PVIN, SVIN No switching ISHDN Shutdown supply current VIO = EN = 0V, VCON = 0V, SW1 = SW2 = VOUT = 0V 0.2 IQ Standby supply current VIO = 1.8V, VSET_CTRL = 02h, SW1 = SW2 = VOUT = 0V 1.2 STBY VCON = 1.4V (2) ILIM_L Input current limit (large) Open Loop (3) ILIM_S Input current limit (small) Open Loop (3) FOSC_PWM Internal oscillator frequency PWM fSCLK SCLK clock frequency IVIO-IN VIO voltage average input current ISDATA IIL ISDATA 1500 1700 700 850 2.1 2.4 0.032 VIH Input high-level threshold EN, GPO0, GPO1 VIL Input low-level threshold EN, GPO0, GPO1 2.7 −1 1 −2 10 −1 10 V Input low-level threshold SDATA, SCLK 0.3*VIO 0.6*VIO SCLK VOH-SDATA Output high-level threshold SDATA ISDATA = −2mA 0.8*VIO VIO + 0.01 VOL-SDATA Output low-level threshold SDATA ISDATA = 2 mA VOH-GPO Output high-level threshold GPO IOUT = ±200 µA VIO−0.15V VIO+0.1V VOL-GPO Output low-level threshold GPO IOUT = ±200 µA −0.4 VSET-LSB Output voltage LSB VSET_CTRL = 40h to 41h 36 IEN EN pin pulldown current VIO = 0V 5 Gain Internal gain 0.2V ≤ VCON ≤ 1.4V 3 ICON VCON pin input leakage EN = 3.8V IOUT_LEAKAGE Leakage into VOUT pin of the buckboost EN = 0, VOUT ≤ 4.2V, VBATT ≤ 5.5V (1) (2) (3) (4) 6 µA 0.6 0.7*VIO (4) mA 1.2 0.4*VIO VIL-SDATA, MHz 1 Input high-level threshold SDATA, SCLK SCLK V mA 1.25 −2 Units mA 26 VIO = 1.8V, Average during 26 MHz write VIN = 0.8*VIO ISCLK VIH-SDATA, VCON = 1.2V VCON = 0.2V VIN = 0.2*VIO ISCLK IIH FB = HIGH Max V 0.2*VIO -1 0.3 V mV 10 µA V/V +1 5 µA Min and Max limits are specified by design, test, or statistical analysis. IQ specified here is when the part is not switching. The parameters in the electrical characteristics table are tested under open loop conditions at PVIN = 3.8V. For performance over the input voltage range and closed loop results refer to the datasheet curves. When using analog control (EN = HIGH) to calculate VOUT, use the following equation: VOUT = VCON × 3. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3279 LM3279 www.ti.com SNVS970A – MARCH 2013 – REVISED MAY 2013 SYSTEM CHARACTERISTICS The following spec table entries are specified by design and verifications, providing the component values in the Typical Application Circuits are used: L = 1.5 µH, DFE201610C-1R5M (2016)/TOKO; CIN and COUT each = 10 µF 6.3V, C105A106MQ5NUNC (0402)/Samsung; PA decoupling cap emulation = 0.47 µF, GRM033R60J474ME90 (0201)/Murata. These parameters are not verified by production testing. Limits in standard typeface are TA = 25°C. Min and Max limits in boldface apply over the full ambient temperature range (−30°C ≤ TA ≤ 85°C) and over the VIN range = 2.7V to 5.5V unless otherwise specified. Symbol Parameter Conditions TON Turn-on time (time for output to reach 0V→90% × 3.4V) IOUT_MAX Max output current DMAX Maximum duty cycle FOSC_PFM Internal oscillator frequency PFM: VOUT = 0.6V, PVIN = 3.7V IOUT = 13 mA CL Load capacitance Half speed readback SCLK = 13 MHz, not including LM3279 capacitance. CVCON VCON input capacitance VCON = 1V, Test frequency = 100 kHz VCON_LIN VCON linearity VIO VO_RIPPLE Load_tr EN = L to H, VBATT = 3.8V, VCON = 1.14V, IOUT = 0 mA VBATT ≥ 3.0V, VOUT = 3.8V 750 VBATT ≥ 3.2V, VOUT = 4.2V 650 Max Units 35 50 µs mA Boost (% M4 on) 50 Buck (% M1 on) 100 63 % kHz 50 pF 10 pF 0.2V ≤ VCON ≤ 1.4V −2.5 +2.5 % VIO I/O voltage level 1.8V Bus 1.65 1.8 1.95 V Ripple voltage VBATT ≥ 3.2V, 0.6 ≤ VOUT ≤ 4.2V, 0 mA ≤ IOUT ≤ 430 mA 15 50 PFM ripple VOUT = 0.6V, IOUT = 5mA 40 Ripple voltage in mode transition VBATT = 3.0V to 5.0V, Tr = Tf = 30s 3.3V ≤ VOUT ≤ 4.2V 50 Line regulation VBATT = 3.2V to 4.9V, VOUT = 3.5V, PWM Operation 10 Load regulation IOUT = 0 mA to 500 mA, VBATT = 3.2V to 4.9V, PWM Operation 20 Line transient response Load transient response VOUT transient response rise time mV mV VBATT = 3.6V to 4.2V, Tr = Tf = 10 µs, VOUT = 3.5V, RLOAD = 11.4Ω, PWM −100 +100 VBATT = 3.6V to 4.2V, Tr = Tf = 10 µs, VOUT = 0.8V, RLOAD = 20Ω, PFM −5 +5 IOUT = 1 mA to 200 mA, Tr = Tf = 1µs, VBATT = 4.2V, VOUT = 3.5V, PWM −100 +100 IOUT = 10 mA to 90 mA, Tr = Tf = 1µs, VBATT = 4.2V, VOUT = 0.8V, PFM −10 +10 VOUT transient response overshoot VOUT_TR Typ 10 ΔVOUT Line_tr Min VBATT = 3.8V, VIO = 1.8V, RFFE write VSET = 3.42V (VSET_CTRL = 5Fh), IOUT = 0mA mV mV 200 VBATT = 3.2V to 4.2V, VOUT = 0.6V to 3.4V, Tr = Tf = 1µs, RLOAD = 5Ω VOUT transient response fall time mV 20 µs 50 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3279 7 LM3279 SNVS970A – MARCH 2013 – REVISED MAY 2013 www.ti.com SYSTEM CHARACTERISTICS (continued) The following spec table entries are specified by design and verifications, providing the component values in the Typical Application Circuits are used: L = 1.5 µH, DFE201610C-1R5M (2016)/TOKO; CIN and COUT each = 10 µF 6.3V, C105A106MQ5NUNC (0402)/Samsung; PA decoupling cap emulation = 0.47 µF, GRM033R60J474ME90 (0201)/Murata. These parameters are not verified by production testing. Limits in standard typeface are TA = 25°C. Min and Max limits in boldface apply over the full ambient temperature range (−30°C ≤ TA ≤ 85°C) and over the VIN range = 2.7V to 5.5V unless otherwise specified. Symbol η Parameter Conditions Efficiency TS Data setup time TH Data hold time Min Typ VBATT = 3.0V, VOUT = 1.9V, IOUT = 20 mA (PWM) 77 VBATT = 3.0V, VOUT = 2.41V, IOUT = 60 mA (PWM) 91 VBATT = 3.0V, VOUT = 2.71V, IOUT = 200 mA (PWM) 94 VBATT = 3.0V, VOUT = 3.31V, IOUT = 480 mA (PWM) 93 VBATT = 3.8V, VOUT = 0.60V, IOUT = 10 mA (PFM) 57 VBATT = 3.8V, VOUT = 1.0V, IOUT = 20 mA (PFM) 75 VBATT = 3.8V, VOUT = 1.9V, IOUT = 20 mA (PWM) 68 VBATT = 3.8V, VOUT = 2.41V, IOUT = 70 mA (PWM) 88 VBATT = 3.8V, VOUT = 2.71V, IOUT = 200 mA (PWM) 94 VBATT = 3.8V, VOUT = 3.31V, IOUT = 480 mA (PWM) 94 VBATT = 3.0, VOUT = 3.6V, IOUT = 200 mA (PWM) 94 Max Units % 1 5 TSDATAOTR SDATA output transition time (rise/fall time) VIO range = 1.65 to 1.95V ns 2.1 6.5 SYSTEM CHARACTERISTICS RECOMMENDED CAPACITANCE SPECIFICATIONS 8 BUS MIN (µF) Typical (µF) MAX (µF) VBATT 4.7 10 — VOUT 3.0 13 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3279 LM3279 www.ti.com SNVS970A – MARCH 2013 – REVISED MAY 2013 STARTUP TIMING VBATT 120 ns (min) 5 Ps (min) SSC 50 Ps max 25 Ps max RFFE write VOUT = 3.42V (REG03h VSET_CTRL = 5Fh) VBATT applied, VIO = 0V. t0 LM3279 in Shutdown. VIO applied. t1 LM3279 in Low Power. Low Power Shutdown Initialization VOUT Settling t2 VOUT programmed. LM3279 initializes and powers up internal circuit blocks. t3 Switcher is active in normal mode. VIO t4 Buck-Boost output settled (90%). SDATA Hi Z 3.42V VOUT discharges VOUT SW t0 t1 t2 t3 t4 Figure 2. Cold Powerup 25 µs max 5 µs max VBATT > 2.7V t0 Standby VIO Init VOUT Settling 1.8V (typ) LM3279 in Standby. VBATT > 2.7V = VIO = 1.8V (typ) VOUT programmed LM3279. Initializes and powers up t1 internal circuit blocks. (Register set to default value.) RFFE write VOUT = 3.40V (REG03h, VSET_CTRL= 5Fh) t2 Switcher is active in normal mode t3 Buck-Boost output settled (90%) SDATA 3.40V Hi Z VOUT SW t0 t1 t2 t3 Figure 3. Standby to Active Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3279 9 LM3279 SNVS970A – MARCH 2013 – REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (PVIN = EN = 3.6V and TA = 25°C, unless otherwise noted) Shutdown Current vs Temperature (VCON=VOUT=SW1=SW2=EN=0V) Switching Frequency vs Temperature (VOUT=3.5V, IOUT=300 mA) Figure 4. Figure 5. PFM Efficiency (VOUT=1.0V) 90 90 80 80 70 60 50 40 PVIN = 2.7V PVIN = 3.0V PVIN = 3.6V PVIN = 4.2V PVIN = 4.8V 30 20 10 70 60 50 40 20 10 0 0 20 40 60 80 100 OUTPUT LOAD (mA) Figure 6. 0 120 PWM Efficiency (VOUT=2.4V) 100 20 40 60 80 100 OUTPUT LOAD (mA) Figure 7. 120 PWM Efficiency (VOUT=3.6V) 100 90 90 80 70 60 PVIN = 2.7V PVIN = 3.0V PVIN = 3.6V PVIN = 4.2V 50 EFFICIENCY (%) EFFICIENCY (%) PVIN = 2.7V PVIN = 3.0V PVIN = 3.6V PVIN = 4.2V PVIN = 4.8V 30 0 40 80 70 60 PVIN = 2.7V PVIN = 3.0V PVIN = 3.6V PVIN = 4.2V 50 40 0 10 PFM Efficiency (VOUT=1.4V) 100 EFFICIENCY (%) EFFICIENCY (%) 100 100 200 300 400 500 600 700 OUTPUT LOAD (mA) Figure 8. Submit Documentation Feedback 0 100 200 300 400 500 600 700 OUTPUT LOAD (mA) Figure 9. Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3279 LM3279 www.ti.com SNVS970A – MARCH 2013 – REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) (PVIN = EN = 3.6V and TA = 25°C, unless otherwise noted) VSET_CTRL Voltage vs Output Voltage (No Load, RFFE Digital Control Mode) Auto Efficiency Mode (VOUT=1.5V) Figure 10. Figure 11. Auto Efficiency Mode (VOUT=2.5V) Auto Efficiency Mode (VOUT=3.4V) Figure 12. Figure 13. VOUT Transient (PVIN=3.8V, VOUT=0.8V<-->2V, RLOAD=20Ω Boost Mode Operation (PVIN=3.37V, VOUT=3.45V, Load=500 mA) SW1 2V/DIV SW2 2V/DIV 20 mV/DIV AC_Vout 400 ns/DIV Figure 14. Figure 15. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3279 11 LM3279 SNVS970A – MARCH 2013 – REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) (PVIN = EN = 3.6V and TA = 25°C, unless otherwise noted) Buck-Boost Operation (PVIN=3.8V, VOUT=3.6V, IOUT=600 mA SW1 Startup (PVIN=3.6V, VOUT=3.45V, Load=350 mA) 2V/DIV 2V/DIV EN SW2 2V/DIV VOUT 2V/DIV 1A/DIV 20 mV/DIV AC_Vout IL 20 s/DIV Figure 17. 400 ns/DIV Figure 16. Line Transient for DC/DC (PVIN Step=3.6V <-> 4.2V, VOUT=3.0V Load=320 mA) Load Transient, Forced PWM Mode PVIN=3.8V, VOUT=3.5V Figure 18. Figure 19. Load Transient, Forced PFM Mode PVIN=4.2V, VOUT=0.8V Standby-to-Active Mode PVIN=4.2V, VSET_CTRL=0x5F, VOUT=3.4V, VIO=1.8V 20 µs/DIV Figure 20. 12 Figure 21. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3279 LM3279 www.ti.com SNVS970A – MARCH 2013 – REVISED MAY 2013 OPERATION DESCRIPTION The LM3279 buck-boost converter provides high-efficiency, low-noise power for RF power amplifiers (PAs) in mobile phones, portable communicators and similar battery powered RF devices. It is designed to allow the RF PA to operate at maximum efficiency for a wide range of power levels from a single Li-Ion battery cell. The capability of LM3279 to provide an output voltage lower than as well as higher than the input battery voltage enables the PA to operate with high linearity for a wide range of battery voltages, thereby extending the usable voltage range of the battery. The converter feedback loop is internally compensated for both buck and boost operation, and the architecture is such that it provides seamless transition between buck and boost mode of operation. The LM3279 operates in energy-saving Pulse Frequency Modulation (PFM) mode for increased efficiencies and current savings during low-power RF transmission modes. The output voltage is dynamically programmable from 0.4V to 4.2V by either programming the VSET value in register 00h, or adjusting the voltage on the control pin VCON. The fast output voltage transient response of LM3279 makes it suitable for adaptively adjusting the PA supply voltage depending on its transmitting power which improves systems efficiency and prolongs battery life Additional features include current-overload protection, output over-voltage clamp, and thermal-overload shutdown. The LM3279 is constructed using a chip-scale 16-bump DSBGA package that offers the smallest possible size for space-critical applications such as cell phones where board area is an important design consideration. Use of a high switching frequency (2.4 MHz, typ.) reduces the size of external components. As shown in the Typical Application diagrams, only three external power components are required for circuit operation. Use of a DSBGA package requires special design considerations for implementation. (See DSBGA Package Assembly And Use in the APPLICATION INFORMATION section.) Its fine bump-pitch requires careful board design and precision assembly equipment. Use of this package is best suited for opaque-case applications where its edges are not subjected to high-intensity ambient red or infrared light. In addition, the system controller should set VIO = LOW (or EN if system implementation with analog VCON) during power-up and other low supply-voltage conditions. Dynamically Adjustable Output Voltage The LM3279 features a dynamically adjustable output voltage to eliminate the need for external feedback resistors. The output can be set from 0.4V to 4.2V by either programming the VSET value in register 00h, or by changing the voltage on the analog VCON pin when implementing analog control. This feature is useful in cellphone RF PA applications where peak power is needed only when the handset is far away from the base station or when data is being transmitted. In other instances, the transmitting power can be reduced. Hence, the supply voltage to the PA can be reduced, promoting longer battery life. In order to adaptively adjust the supply voltage to the PA in real time in a cell-phone application, the output-voltage transition should be fast enough in order to meet the RF transmit signal specifications. The LM3279 offers ultra-fast output-voltage transition without drawing very large currents from the battery supply. For a current limit of 1700 mA (typ.), the output voltage can transition from 0.6V to 3.4V in less than 20 µs with a load resistance of 5Ω at VBATT = 3.8V. Seamless Mode Transition In a typical non-inverting buck-boost converter, all four power switches M1 through M4 are switched every cycle. This operation increases MOSFET drive losses and lowers the converter efficiency. The LM3279 switches only two power switches every cycle to improve converter efficiency. Hence, it operates either as buck converter or a boost converter depending upon the input and output voltage conditions. This creates a boundary between the buck and boost mode of operation. When the input battery voltage is close to the set output voltage, the converter automatically switches to a four-switch operation seamlessly such that the output voltage does not see any perturbations at the mode boundary. The excellent mode-transition capability of the LM3279 enables lownoise output with highest efficiency. Internal feedback loop compensation ensures stable operation in buck, boost, and buck-boost modes, as well as during mode transitions. Setting the Output Voltage The output voltage can be set by two methods: via Analog Control or Digital Control. In the Analog Control method, the VCON pin is an external analog control input pin. It can be enabled (EN = HIGH) or disabled (EN = LOW). An analog voltage is provided by an external MCU (either a D/A or averaged PWM output) to the VCON pin. The range of this signal is 0.2V (min.) to 1.4V (max. typ.) to provide the full range of the possible output voltage. This signal is internally amplified by a gain of 3 to go from 0.6V to 4.2V output. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3279 13 LM3279 SNVS970A – MARCH 2013 – REVISED MAY 2013 www.ti.com For the Digital Control method, the output voltage is set by writing a 7-bit value to reg 00h, bits 0 through 6. Programming a value 00h will force the LM3279 into low-power mode where the entire device except the RFFE interface is turned off. Programming register 00h with the value 02h will place the LM3279 into Standby mode where the SW pin is tri-stated. Values programmed above 0Bh will determine the output voltage from 0.4V to 4.212V in 36 mV (typ.) increments. The output voltage quickly adjusts to the new output voltage value within 20 microseconds both in the positive and negative directions. To accomplish this, the LM3279 buck-boost output can both source and sink current. In the positive direction the buck may assume a 100-percent duty cycle or enter boost mode at up to 50% duty cycle to provide the required current. In the negative direction, the synchronous rectifier (NFET) will remain on to sink current from the output capacitor. General Purpose Outputs The LM3279 provides two general-purpose outputs to control the RF front-end circuitry. These outputs have a maximum output voltage of +1.8V. These bits are set by writing to register 02h bits 6 (GPO1) and bit 7 (GPO0). Enable and Shutdown Mode Setting the VIO and EN digital pins low (< 0.6V) places the LM3279 in shutdown mode (0.01 μA typ. for VIO or EN = 0V). During shutdown, the output of LM3279 is in tri-state mode. Setting VIO or EN high (>1.2V) enables normal operation. VIO and EN should be set low to turn off the LM3279 during power-up and undervoltage conditions when the power supply (VBATT) is less than the 2.7V minimum operating voltage. When VIO is HIGH, EN must be GND, and when EN = HIGH, VIO must be GND. When EN goes logic low →logic high, for the first 20 μs the dump-switch M6 turns ON to discharge the output capacitor. The duration of M6 being ON is about 20 μs. This enables discharge of (an initially charged) output capacitor to voltages much less than 4.2V. The switcher feedback-control loops continues the discharge process (if need be) so that the charge in the output capacitor is regulated to the correct output voltage value. When VIO is applied, the default values are loaded into the control registers. Low-Power Mode The low-power mode is a very low current state where the VIO voltage remains at 1.8V, and the RFFE interface continues to operate. Here, the current drawn from the VBATT is < 0.1 µA (typ.). This mode can be entered by writing a value of 00h into register 00h (VSET Control Register) or by programming PWR_MODE[1:0] to 10b (bits 6 and 7 of register 1Ch PM-TRIG Register). During low power mode, the LM3279 maintains the previous programmable register settings upon resuming normal operation. Standby Mode The standby mode is a mode where the switching is stopped and the power control circuit is off, but the control and the RFFE interface continue to operate. The VIO voltage remains at 1.8V. Here, the current drawn from the VBATT is 1 mA (typ.). This mode can be entered by writing a value of 02h into register 00h (VSET Control Register) when the PWR_MODE bits are set to normal operation 00b (bits 6 and 7 of register 1Ch PM-TRIG Register). In this mode the SW pins are tri-stated. VCONON When EN = HIGH, the output is disabled when VCON is below 125 mV (typ.). It is enabled when VCON is above 150 mV (typ.). The threshold has 25 mV (typ.) of hysteresis. RDSON Management The LM3279 has a unique RDSON-management function to improve efficiency in both the low-output voltage and high-output voltage conditions. For VSET < 2.1V (typ.) or VCON < 0.7 (typ.), the device uses only a small part of the PMOSFET M1 to minimize drive loss of the PMOSFET. When VSET > 2.175V or VCON > 0.725V, a large PMOSFET is also used along with the small PMOSFET. The threshold has a 25 mV of hysteresis. For RF PAs, the current consumption typically increases with its supply voltage; thus, higher supply voltage for a PA also means higher power delivered to it. Hence, adding a large PMOSFET for VSET > 2.175V or VCON > 0.725V 14 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3279 LM3279 www.ti.com SNVS970A – MARCH 2013 – REVISED MAY 2013 reduces the conduction losses, thereby achieving high efficiency. The LM3279 can also provide output voltages higher than the battery voltage. This boost mode of operation is typically used when the battery voltage has discharged to a low voltage that is not sufficient to provide the required linearity in the PA. A special RDSONmanagement scheme is designed for operation well into boost mode so that an auxiliary PMOSFET switch is also turned on along with Large and Small PMOSFET switches, effectively reducing the RDSON of M1 to a very low value in order to keep the efficiency maximum. Since M1 conducts all the time in boost mode, reducing the RDSON of M1 achieves significant improvement in efficiency. Supply Current Limit A current limit feature allows the LM3279 to protect itself and external components during overload conditions. In Pulse Width Modulation (PWM) mode, a 1700 mA (typ.) cycle-by-cycle current limit is normally used when VOUT is above 2.1V (typ.) and an 850 mA (typ.) limit is used when VOUT is below 2.1V (typ.). If an excessive load pulls the output voltage down to approximately 0.30V, the device switches to a timed current-limit mode, and the current limit in this mode is 850 mA (typ.), independent of the set VOUT voltage. In timed current limit mode, the internal PMOSFET switch M1 is turned off after the current limit is hit, and the beginning of the next cycle is inhibited for 3.5 μs to force the instantaneous inductor current to ramp down to a safe value. Reverse Current Limit Since the LM3279 features a dynamically adjustable output voltage, the inductor current can build up to high values in either direction depending on the output voltage transient. For a low-to-high output voltage transient, the inductor current flows from SW1 pin to SW2 pin; this current is limited by the current-limit feature monitoring of MOSFET M1. For a high-to-low output voltage transient, the inductor current flows from SW2 pin to SW1 pin and this current needs to be limited to protect the LM3279 as well as the external components. A reverse current limit feature allows monitoring the reverse inductor current that also flows through MOSFET M2. A −1.2A (typ.) cycle-by-cycle current limit is used to limit the reverse current. When the reverse current hits the reverse current limit during a PWM cycle, MOSFET M2 is turned off, and MOSFET M1 and M4 are turned on, for the rest of that switching cycle. This allows the inductor to build current in the opposite direction thereby limiting the reverse current. It should be noted that the power MOSFET switches M3 and M4 do not have their own current limiting circuits and are dependent on the current-limit operation implemented for power MOSFETs M1 and M2 to protect them. The implication of this is that any external forcing of voltage/current on SW2 pin or misuse of SW2 pin may be detrimental to the part and may damage the internal circuits. VCON Overvoltage Clamp The LM3279 features an internal clamp on the analog VCON pin voltage to limit the output voltage to a maximum safe value. The VCON voltage is internally switched to a reference voltage of approximately 1.6V when the VCON pin voltage exceeds 1.6V. This limits the output voltage to approximately 4.8V and protects the part from overvoltage stress. When implementing digital control, the VSET inherently limits the output voltage to the required range. Thermal Overload Protection The LM3279 has a thermal overload protection function that operates to protect itself from short-term misuse and overload conditions. When the junction temperature exceeds around 150°C, the device inhibits operation. All power MOSFET switches are turned off in PWM mode. When the temperature drops below 125°C, normal operation resumes. Prolonged operation in thermal overload conditions may damage the device and is considered bad practice. PFM Mode The LM3279 enters PFM mode and operates with reduced switching frequency and supply current to maintain very high efficiencies for light-load operation. The conditions for entering and exiting the PFM and PWM mode are provided in Table 1. In PFM mode, the LM3279 will support up to 100 mA max. In Analog Control Mode the PWM/PFM mode transition has a 60 mV VOUT hysteresis. For STATE_CTRL[1:0] = 10, the PWM/PFM load current threshold has a 30 mA hysteresis. During output voltage transients, the LM3279 will automatically shift temporarily to PWM mode before settling to the final output voltage in either PFM or PWM mode depending on the conditions in Table 1. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3279 15 LM3279 SNVS970A – MARCH 2013 – REVISED MAY 2013 www.ti.com Table 1. PWM-PFM Operation Truth Table STATE_CTRL [1:0] Analog Control (EN = HIGH, external DAC connected to Digital Control (VIO = High, VSET_CTRL in Register 00h or GPO1, GPO0 VCON) programmed via RFFE) 00 Forced PFM 01 PWM if VCON > 0.5V; PFM if VCON < 0.5V PWM if VSET_CTRL ≥ 29h; PFM if VSET_CTRL < 29h 10 PWM if VCON > 0.7V OR load >130 mA; PFM if VCON < 0.7V AND IOUT < 100 mA PWM if VSET_CTRL ≥ 39h OR load > 130 mA; PFM if VSET_CTRL < 39h AND IOUT < 100 mA 11 Forced PWM Digital Control Serial Bus Interface The Digital Control Serial Bus Interface provides MIPI RF Front-End Control Interface-compatible access to the programmable functions and registers on the device. When VIO voltage supply is applied to the Bus, it enables the Slave interface and resets the user-defined Slave registers to the default settings. The LM3279 uses a threepin digital interface; two for bidirectional communications between the ICs connected to the Bus, along with an interface voltage reference VIO that also acts as asynchronous enable and reset. When VIO voltage supply is applied to the Bus, it enables the Slave interface and resets the user-defined Slave registers to the default settings. The device can be set to power-down mode via the asynchronous VIO signal or by setting the appropriate register via Serial Bus Interface. The two communication lines are serial data (SDATA) and clock (SCLK). SCLK and SDATA must be held low until VIO is present. The LM3279 connects as a slave on a singlemaster Serial Bus Interface. The SDATA signal is bidirectional, driven by the Master or a Slave. Data is written on the rising edge (transition from logical level zero to logical level one) of the SCLK signal by both Master and Slaves. Master and Slave both read the data on the falling edge (transition from logical level one to logical level zero) of the SCLK signal. A logic-low level applied to VIO signal powers off the digital interface. Programming the VSET_CTRL register dynamically adjusts the Buck-Boost output voltage. The feedback voltage changes from VFB,MIN to VFB,MAX depending upon the register value. The digital interface is also used to program the LM3279 for PWM or into PWM and PFM mode. Supported Command Sequences SCLK SA3 SDATA SSC SA2 SA1 SA0 1 D6 D5 D4 Slave Address D3 Data D2 D1 D0 P Parity 0 Bus Park Signal driven by Master. Signal not driven; pull-down only. For reference only. Figure 22. Register 0 Write 16 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3279 LM3279 www.ti.com SNVS970A – MARCH 2013 – REVISED MAY 2013 SCLK A SDATA SA3 SA2 SA1 SA0 0 SSC 1 0 A4 A3 A2 A1 A0 P Register Write Command Frame SCLK A SDATA P D7 D6 D5 D4 D3 D2 D1 D0 P 0 Bus Park Data Frame Signal driven by Master. Signal not driven; pull-down only. For reference only. Figure 23. Register Write SCLK A SDATA SA3 SA2 SA1 SA0 0 SSC 1 1 A4 A3 A2 A1 A0 P Register Read Command Frame SCLK A SDATA P 0 Bus Park D7 D6 D5 D4 D3 D2 Data Frame (from Slave) D1 D0 P 0 Bus Park Signal driven by Master. Signal driven by Slave. Signal not driven; pulldown only. For reference only. Figure 24. Register Read Device Enumeration The interface component recognizes broadcast Slave Address (SID) of 0000b and is configured, via internal interface signals, with a Unique SID address (USID) and a Group SID address (GSID). The USID is set to 0101b and GSID set to 0000b. The register-set component will typically set the USID to a fixed value; however, it is also possible to construct a register-set component that allows the USID to be programmed via the RFFE bus. I/O This RFFE interface supports a 1.8V VIO supply level. A power-on reset circuit will be included that resets the RFFE interface and register-set components when VIO is removed. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3279 17 LM3279 SNVS970A – MARCH 2013 – REVISED MAY 2013 www.ti.com Control Interface Timing Parameters TSCLKOTR TSCLKOTR TSCLKOH TSCLKOL VOHmin SCLK VOLmax Figure 25. Clock Timing VTPmax SCLK VTNmin TD TSDATAOTR TD TS TH TSDATAOTR TS TH VTPmax SDATA VTNmin Figure 26. Setup and Hold Timing Programmable Registers ADDRESS REGISTER CONTENTS 00h VSET_CTRL Bits Name 7 Reserved 6:0 VSET_CTRL[6:0] Bits Name 7:6 STATE_CTRL[1:0] 5:0 Reserved 01h DC-DC voltage control bits. VSET_CTRL = 00h puts the part into a low power mode. VSET_CTRL = 02h puts the part in a standby mode. VSET_CTRL = 0Bh corresponds to 0.4V and 75h corresponds to 4.212V STATE_CTRL 02h 18 Description Reserved bit. Default = 0. Description PWM and PFM state control bits. 00b = Force PFM 01b = PFM if VOUT < 1.5 (default) 10b = PFM if VOUT < 2.1 and IOUT < 100 mA 11b = Force PWM GPO_CTRL Bits Name 7 GPO0 GPO0 control bit. 0b = Output set to low level (default) 1b = Output set to high level Description 6 GPO1 GPO1 control bit. 0b = Output set to low level (default) 1b = Output set to high level Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3279 LM3279 www.ti.com SNVS970A – MARCH 2013 – REVISED MAY 2013 03h-1Bh RESERVED Bits Name Description Reserved registers for configuration, test, and trim. 1Ch PM_TRIG Bits Name 7:6 PWR_MODE[1:0] Power Mode Bits. 00b = Normal operation 01b = Default settings 10b = Low power 11b = Reserved 5:0 TRIG_REG[5:0] Reserved for trigger bits. Bits Name 7:0 PRODUCT_ID[7:0] Bits Name 7:0 MANUFACTURER_ID[7:0] Bits Name Description 7:6 SPARE[1:0] This is a read-only register that is reserved and yields a value of 00b at readback. Potentially used in future for extending manufacturer ID field. 5:4 MANUFACTURER_ID[5:4] 3:0 USID[3:0] 1Dh Description PRODUCT_ID 1Eh Description Product identification bits. Set to A0h. MANUFACTURER_ID 1Fh Description Manufacturer identification bits. 7:0 1Eh are LSB for TI. USID Manufacturer identification bits. 5:4 01h are MSB for TI. Unique slave identifier. Default 0101b. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3279 19 LM3279 SNVS970A – MARCH 2013 – REVISED MAY 2013 www.ti.com APPLICATION INFORMATION Output Current Capability The typical LM3279 load capability vs. input voltage is as shown in Table 2. There are 3 distinct regions of current capability. In the low output-voltage region, VOUT < 2.1V (also known as the RDSON-managed region), the output-current capability is determined by the current capability of the RDSON-managed MOSFET, typically 600 mA. When the output voltage is greater than 2.1V, and in buck mode, the current capability increases to 1400 mA as determined by the over-current limit setting and the magnitude of ripple current. While in boost-mode operation, the output-current capability is determined by the output-input voltage ratio. It is expected for the typical RF PA to have an approximate resistive load characteristic. Refer to Table 2 for output current capability. Table 2. Output Voltage vs Maximum Output Current Derating VOUT VIN Maximum IOUT Capability (mA) ≤ 3.0V 450 > 3.0V 650 ≥ 2.5V 500 ≥ 2.7V 750 ≥ 3.0V 950 ≥ 2.5V 750 3.4 ≥ 2.7V 950 ≥ 3.0V 1100 < 1.5V 2.7V to 5.0V 100 mA (in PFM mode) 4.2V 3.8V Recommended External Components Inductor Selection A 1.5 µH inductor with a saturation current rating over 1900 mA and low inductance drop at the full DC bias condition is recommended for almost all applications. An inductor with a DC resistance of less than 0.1Ω and smaller ESR should be used to get good efficiency for all output current conditions. Table 3. Suggested Inductors Model DFE201610C-1R5M (1285A5-H-1R5M) (1.5 µH) TFM201610A-1R5M (1.5 µH) ELGUEA1R5NA (1.5 μH) Vendor Dimensions (mm) ISAT mA (30% drop in inductance) DCR TOKO 2.0 x 1.6 x 1.0 2200 120 mΩ TDK 2.0 x 1.6 x 1.0 2000 140 mΩ Panasonic 2.0 x 1.6 x 1.0 1900 100 mΩ If a smaller inductance inductor is used in the application, the VOUT transient response time is affected. If a winding type inductor is used, the efficiency at light load current condition may not be so good due to bigger DCR. Input Capacitor Selection A ceramic input capacitor of 10 µF, 6.3V, 0402 or higher is sufficient for most applications. Place the input capacitor as close as possible to the PVIN pin and PGND pin of the device. A larger value of higher voltage rating may be used to improve input filtering. Use X7R, X5R, or B types; do not use Y5V or F. The input filter capacitor supplies current to the PFET (high-side) switch in the first half of each cycle and reduces voltage ripple imposed on the input power source. A ceramic capacitor’s low ESR provides the best noise filtering of the input voltage spikes due to this rapidly changing current. 20 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3279 LM3279 www.ti.com SNVS970A – MARCH 2013 – REVISED MAY 2013 Output Capacitor Selection Use a 10 µF, 6.3V, 0402 capacitor for the output capacitor. Use of capacitor types such as X5R, X7R is recommended for the filter. These provide an optimal balance between small size, cost, reliability, and performance for cell phones and similar applications. Table 4 lists suggested part numbers and suppliers. DC bias characteristics of the capacitors must be considered while selecting the voltage rating and case size of the capacitor. Smaller case sizes for the output capacitor mitigate piezo-electric vibrations of the capacitor when the output voltage is stepped up and down at fast rates. However, they have a bigger percentage drop in value with DC bias. A 0402 case size output capacitor is recommended for small solution size. For RF Power Amplifier applications, the output capacitor loading is combined between the DC-DC converter and the RF Power Amplifier(s). (10 μF (0402) + PA input cap 3 x 1μF (0402/0201) is recommended.) The optimum capacitance split is application-dependent. Place all the output capacitors very close to their respective device. If using a 4.7 μF, 0402 as the output capacitor, the total recommended actual capacitance on the VOUT bus should be at least > 6.8 μF (4.7 μF + PA decoupling caps), to take into account the 0402 DC bias degradation and other tolerances. The minimum capacitance under DC bias conditions should be > 3 μF. Table 4. Suggested Capacitors Model Vendor CL05A106MQ5NUN (0402) Samsung 10 µF for CIN = COUT 1.0 µF for PA Decoupling Caps (x 3) C0603X5R0G105M(0201(0603)) TDK 0.47 µF for PA Decoupling Caps (x 2) GRM033R60J474ME90 (0201(0603)) Murata DSBGA Package Assembly And Use Use of the DSBGA package requires specialized board layout, precision mounting, and careful re-flow techniques, as detailed in Texas Instruments Application Note 1112. Refer to the section Surface Mount Technology (SMD) Assembly Considerations. For best results in assembly, alignment ordinals on the PC board should be used to facilitate placement of the device. The pad style used with DSBGA package must be the NSMD (non-solder mask defined) type. This means that the solder-mask opening is larger than the pad size. This prevents a lip that otherwise forms if the solder-mask and pad overlap from holding the device off the surface of the board and interfering with mounting. See Application Note 1112 for specific instructions how to do this. The 16-bump package used for the LM3279 has 300 micron solder balls and requires 10.82 mil pads for mounting on the circuit board. The trace to each pad should enter the pad with a 90° entry angle to prevent debris from being caught in deep corners. Initially, the trace to each pad should be 9 mil wide, for a section approximately 9 mil long, as a thermal relief. Then each trance should neck up or down to its optimal width. The important criterion is symmetry. This ensures the solder bumps on the LM3279 re-flow evenly and that the device solders level to the board. In particular, special attention must be paid to the pads for bumps B4 and D4. Because PVIN and PGND are typically connected to large copper planes, inadequate thermal relief can result in late or inadequate re-flow of these bumps. The DSBGA package is optimized for the smallest possible size in applications with red or infrared opaque cases. Because the DSBGA package lacks the plastic encapsulation characteristic of larger devices, it is vulnerable to light. Backside metallization and/or epoxy coating, along with front-side shading by the printed circuit board, reduce this sensitivity. However, the package has exposed die edges. In particular, DSBGA devices are sensitive to light (in the red and infrared range) shining on the package's exposed die edges. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3279 21 LM3279 SNVS970A – MARCH 2013 – REVISED MAY 2013 www.ti.com PCB LAYOUT CONSIDERATIONS Overview PC board layout is critical to successfully designing a DC-DC converter into a product. As much as a 10 dB improvement in RX noise floor can be achieved by carefully following recommended layout practices. A properly planned board layout optimizes the performance of a DC-DC converter and minimizes effects on surrounding circuitry while also addressing manufacturing issues that can have adverse impacts on board quality and final product yield. PCB Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. Erroneous signals could be sent to the DC-DC converter IC, resulting in poor regulation or instability. Poor layout can also result in re-flow problems leading to poor solder joints between the DSBGA package and board pads. Poor solder joints can result in erratic or degraded performance of the converter. Energy Efficiency Minimize resistive losses by using wide traces between the power components and doubling up traces on multiple layers when possible. EMI By its very nature, any switching converter generates electrical noise. The circuit board designer’s challenge is to minimize, contain, or attenuate such switcher-generated noise. A high-frequency switching converter, such as the LM3279, switches Ampere level currents within nanoseconds, and the traces interconnecting the associated components can act as radiating antennas. The following guidelines are offered to help to ensure that EMI is maintained within tolerable levels. To help minimize radiated noise: • Place the LM3279 switcher, its input capacitor, and output filter inductor and capacitor close together, and make the interconnecting traces as short as possible. • Arrange the components so that the switching current loops curl in the same direction. During the first half of each cycle (buck mode), current flows from the input filter capacitor, through the internal PFET of the LM3279 and the inductor, to the output filter capacitor, then back through ground, forming a current loop. In the second half of each cycle (buck mode), current is pulled up from ground, through the internal synchronous NFET of the LM3279 by the inductor, to the output filter capacitor and then back through ground, forming a second current loop. Routing these loops so the current curls in the same direction prevents magnetic field reversal between the two half-cycles and reduces radiated noise. • Make the current loop area(s) as small as possible. To help minimize conducted noise in the ground-plane: • • Reduce the amount of switching current that circulates through the ground plane: Connect the ground bumps of the LM3279 and its input/output filter capacitors together using generous component-side copper fill as a pseudo-ground plane. Then connect this copper fill to the system ground-plane (if one is used) by multiple vias. These multiple vias help to minimize ground bounce at the LM3279 by giving it a lowimpedance ground connection. To help minimize coupling to the DC-DC converter's own voltage feedback trace: • Route noise sensitive traces, such as the voltage feedback path (FB), as directly as possible from the switcher FB pad to the VOUT pad of the output capacitor, but keep it away from noisy traces between the power components. If possible, connect FB bump directly to VOUT bump. To decouple common power supply lines, series impedances may be used to strategically isolate circuits: • Take advantage of the inherent inductance of circuit traces to reduce coupling among function blocks, by way of the power supply traces. • Use star connection for separately routing VBATT to PVIN and VBATT_PA (VCC1). • Inserting a single ferrite bead in-line with a power supply trace may offer a favorable tradeoff in terms of board area, by allowing the use of fewer bypass capacitors. 22 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3279 LM3279 www.ti.com SNVS970A – MARCH 2013 – REVISED MAY 2013 Manufacturing Considerations The LM3279 package employs a 16-bump (4x4) array of 300 micron solder balls, with a 0.5 mm pad pitch. A few simple design rules will go a long way to ensuring a good layout. • Pad size should be 0.265 ± 0.02 mm. Solder mask opening should be 0.375 ± 0.02 mm. • As a thermal relief, connect to each pad with 9.5 mil wide, 5 mil long traces and incrementally increase each trace to its optimal width. Symmetry is important to ensure the solder bumps re-flow evenly. Refer to TI Application Note AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009). LM3279 RF Evaluation Board 1.5 ÛH SW2 SW1 VBATT: 2.7V to 5.5V PVIN VOUT SVIN FB X LM3279 VOUT: 0.4V to 4.2V VCON EN RF PA(s) 10 ÛF 10 ÛF VIO GPO0 2 x 0.47 ÛF (PA decoupling caps) SDATA GPO1 SCLK DGND SGND PGND BB or RFIC RF Control Bits Figure 27. Simplified LM3279 RF Evaluation Board Schematic 1. 2. 3. 4. 5. 6. 7. Input Capacitor C2 should be placed closer to LM3279 than C1. Optional to add a 100 nF (C1) on input of LM3279 for high frequency filtering. Bulk Output Capacitor C3 should be placed closer to LM3279 than C4. Optional to add a 100 nF (C4) on output of LM3279 for high frequency filtering. Connect both GND terminals of C1 and C4 directly to System RF GND layer of phone board. Connect bumps SGND (C3) and GND (D1) directly to System GND. TI has seen improvement in high frequency filtering for small bypass caps (C1 and C4) when they are connected to System GND instead of same ground as PGND. These capacitors should be 0201 (0603 metric) case size for minimum footprint and best high frequency characteristics. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3279 23 LM3279 SNVS970A – MARCH 2013 – REVISED MAY 2013 www.ti.com Component Placement C1 FB C2 PGND SVIN PVIN SW1 GPO1 EN SGND SW2 GPO0 VCON FB VOUT SCLK SDATA VIO GND C3 C4 L Figure 28. LM3279 Recommended Parts Placement (Top View) PCB Considerations by Layer VBATT Use a star connection from VBATT to LM3279 and VBATT to PA VBATT (VCC1) connection. Do not daisy-chain VBATT connection to LM3279 circuit and then to PA device VBATT connection. Top Layer 1. Create a PGND island as shown. PGND pads of C2 (CIN) and C3 (COUT) must be isolated from each other. This PGND island will connect to the dedicated system ground with many vias. 2. Each SW (C3) and (D4) bump will have a via in pad and an additional via next to it, to drop down the SW trace to layer 3. 3. SGND bump (C2) and GND (D1) will have a via in pad, and directly connecting it to the system ground. 4. FB (C2) should connect directly to the VOUT bump (D1). 5. Have PVIN vias next to optional ferrite bead. Layer 2 6. Digital logic signals may be routed on this layer. 7. PVIN for the LM3279 can be routed on this layer. 8. VCC2 can be routed on this layer. Layer 3 9. Each SW trace is routed on this layer. The width of each trace should be 15 mils (0.381mm) for current capabilities. Have two vias bring each SW trace up to the inductor pads. Layer 4 10. Connect the PGND, SGND, and high Frequency vias from the top layer on this layer. 24 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3279 LM3279 www.ti.com SNVS970A – MARCH 2013 – REVISED MAY 2013 Figure 29. Top Layer Figure 30. Board Layer 2 - Logic and PVIN Routing Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3279 25 LM3279 SNVS970A – MARCH 2013 – REVISED MAY 2013 www.ti.com Figure 31. Board Layer 3 - SW Routing Figure 32. Board Layer 4 - System GND Plane 26 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3279 PACKAGE OPTION ADDENDUM www.ti.com 29-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LM3279TLE/NOPB ACTIVE DSBGA YZR 16 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -30 to 85 SJ4B LM3279TLX/NOPB ACTIVE DSBGA YZR 16 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -30 to 85 SJ4B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM3279TLE/NOPB DSBGA YZR 16 250 178.0 8.4 LM3279TLX/NOPB DSBGA YZR 16 3000 178.0 8.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2.18 2.69 0.76 4.0 8.0 Q1 2.18 2.69 0.76 4.0 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM3279TLE/NOPB DSBGA YZR LM3279TLX/NOPB DSBGA YZR 16 250 210.0 185.0 35.0 16 3000 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA YZR0016xxx D 0.600±0.075 E TLA16XXX (Rev C) D: Max = 2.529 mm, Min =2.469 mm E: Max = 2.146 mm, Min =2.086 mm 4215051/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. 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