STK5C4U332J E D

STK5C4U332J-E
Advance Information
3A/600V Integrated Power Module
in Compact DIP package
The STK5C4U332J-E is a fully-integrated inverter power stage consisting
of a high-voltage driver, six IGBT’s and a thermistor, suitable for driving
permanent magnet synchronous (PMSM) motors, brushless-DC (BLDC)
motors and AC asynchronous motors. The IGBT’s are configured in a 3phase bridge with separate emitter connections for the lower legs for
maximum flexibility in the choice of control algorithm.
The power stage has a full range of protection functions including crossconduction protection, external shutdown and under-voltage lockout
functions. An internal comparator and reference connected to the overcurrent protection circuit allows the designer to set the over-current
protection level.
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PACKAGE PICTURE
Features







Three-phase 3A/600V IGBT module with integrated drivers
Typical values: VCE(SAT) = 1.3V, VF = 1.3V, ESW = 115J at 1.5A
Compact 29.6mm  18.2mm dual in-line package
Cross-conduction protection
Adjustable over-current protection level
Integrated bootstrap diodes and resistors
Enable pin
MODULE 29.6x18.2 DIP S
MARKING DIAGRAM
Certification
 UL1557 (File number: E339285)
Typical Applications




Industrial Pumps
Industrial Fans
Industrial Automation
Home Appliances
STK5C4U332J = Specific Device Code
A = Year
B = Month
C = Production Site
DD = Factory Lot Code
Device marking is on package underside
ORDERING INFORMATION
Device
STK5C4U332J-E
Package
Shipping
(Qty / Packing)
MODULE
29.6x18.2 DIP S
(Pb-Free)
16 / Tube
Figure 1. Functional Diagram
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
© Semiconductor Components Industries, LLC, 2016
March 2016 - Rev. P2
1
Publication Order Number:
STK5C4U332J-E/D
STK5C4U332J-E
Figure 2. Application Schematic
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2
STK5C4U332J-E
Figure 3. Simplified Block Diagram
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STK5C4U332J-E
PIN FUNCTION DESCRIPTION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
17
18
19
20
22
26
28
32
34
38
Name
GND
VDD
HINU
HINV
HINW
LINU
LINV
LINW
FAULT
ITRIP
ENABLE
RCIN
TH1
TH2
NU
NV
NW
W
VBW
V
VBV
U
VBU
VP
Description
Negative Main Supply
+15V Main Supply
Logic Input High Side Gate Driver - Phase U
Logic Input High Side Gate Driver - Phase V
Logic Input High Side Gate Driver - Phase W
Logic Input Low Side Gate Driver - Phase U
Logic Input Low Side Gate Driver - Phase V
Logic Input Low Side Gate Driver - Phase W
Fault output
Current protection pin
Enable input
R,C connection terminal for setting FAULT clear time
Thermistor output 1
Thermistor output 2
Low Side Emitter Connection - Phase U
Low Side Emitter Connection - Phase V
Low Side Emitter Connection - Phase W
W phase output. Internally connected to W phase high side driver ground
High Side Floating Supply Voltage for W phase
V phase output. Internally connected to V phase high side driver ground
High Side Floating Supply voltage for V phase
U phase output. Internally connected to U phase high side driver ground
High Side Floating Supply voltage for U phase
Positive Bus Input Voltage
Note: Pins 15, 16, 21, 23, 24, 25, 27, 29, 30, 31, 33, 35, 36, 37 are not present
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STK5C4U332J-E
ABSOLUTE MAXIMUM RATINGS (Notes 1, 2)
Rating
Symbol
Conditions
Value
Unit
450
V
600
V
Supply voltage
VCC
VP to NU,NV,NW, surge < 500V
Collector-emitter voltage
VCE max
VP to U,V,W; U to NU; V to NV; W to NW
VP,U,V,W,NU,NV,NW terminal current
±3
A
Output current
Io
±1.5
A
Output peak current
Iop
±6
A
Gate driver supply voltages
VBS
0.3 to +20.0
V
Input signal voltage
VIN
HINU, HINV, HINW, LINU, LINV, LINW
0.3 to VDD
V
FAULT terminal voltage
VFAULT
FAULT terminal
0.3 to VDD
V
RCIN terminal voltage
VRCIN
RCIN terminal
0.3 to VDD
V
ITRIP terminal voltage
VITRIP
ITRIP terminal
0.3 to +10.0
V
0.3 to VDD
V
(Note 3)
VP,U,V,W,NU,NV,NW terminal current,
Tc = 100C
VP,U,V,W,NU,NV,NW terminal current,
pulse width 1ms
VBU to U, VBV to V, VBW to W, VDD to GND
(Note 4)
ENABLE terminal voltage
VENABLE
ENABLE terminal
Maximum power dissipation
Pd
IGBT per 1 channel
11.3
W
Junction temperature
Tj
IGBT, Gate driver IC
150
C
Storage temperature
Tstg
40 to +125
C
Operating case temperature
Tc
IPM case temperature
20 to +100
C
Case mounting screw
0.6
Nm
2000
Vrms
Package mounting torque
Isolation voltage
1.
2.
3.
4.
5.
Vis
50Hz sine wave AC 1 minute
(Note 5)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device
functionality should not be assumed, damage may occur and reliability may be affected.
Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for
Safe Operating parameters.
This surge voltage developed by the switching operation due to the wiring inductance between VP and NU,NV,NW terminals.
VBS=VBU to U, VBV to V, VBW to W.
Test conditions : AC2500V, 1 s.
RECOMMENDED OPERATING RANGES (Note 6)
Rating
Supply voltage
Gate driver supply voltage
Symbol
Max
Unit
0
280
450
V
17.5
V
16.5
V
2.5
VDD
V
0
0.8
1
20
VP to NU,NV,NW
VBS
VBU to U, VBV to V, VBW to W
12.5
15
VDD
VDD to GND (Note 4)
13.5
15
VIN(ON)
OFF-state input voltage
VIN(OFF)
PWM frequency
fPWM
Dead time
DT
Turn-off to turn-on (external)
Allowable input pulse width
PWIN
ON and OFF
Package mounting torque
Typ
VCC
ON-state input voltage
6.
Min
HINU, HINV, HINW, LINU, LINV, LINW
‘M3’ type screw
1.3
μs
1
μs
0.4
0.6
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to
stresses beyond the Recommended Operating Ranges limits may affect device reliability.
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5
kHz
Nm
STK5C4U332J-E
ELECTRICAL CHARACTERISTICS (Note 7)
at Tc=25C
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Power output section
Collector-emitter leakage current
VCE = 600V
ICE
100
μA
Bootstrap diode reverse current
VR(BD) = 600V
IR(BD)
100
μA
Ic = 3A, Tj = 25C
VCE(SAT)
1.6
2.4
V
1.3
-
V
1.5
2.3
V
1.3
-
V
Collector to emitter saturation voltage
Diode forward voltage
Ic = 1.5A, Tj = 100C
VF
IF = 3A, Tj = 25C
IF = 1.5A, Tj = 100C
Junction to case thermal resistance
Reverse conducting IGBT
Switching time
Ic = 3A, VCC = 300V, Tj = 25C
Turn-on switching loss
θj-c(T)
-
-
11
C/W
tON
-
0.5
1.2
μs
tOFF
-
0.6
1.4
μs
EON
-
100
-
μJ
EOFF
-
15
-
μJ
Total switching loss
ETOT
-
115
-
μJ
Turn-on switching loss
EON
-
120
-
μJ
EOFF
-
20
-
μJ
ETOT
-
140
-
μJ
EREC
-
35
-
μJ
Full
Square
150
-
ns
3
-
-
μs
50
-
50
V/ns
-
0.1
0.2
mA
Turn-off switching loss
Turn-off switching loss
Ic = 1.5A, VCC = 300V, Tj = 25C
Ic = 1.5A, VCC = 300V, Tj = 100C
Total switching loss
Diode reverse recovery energy
Diode reverse recovery time
Ic = 1.5A, VCC = 300V, Tj = 100C
(di/dt set by internal driver)
trr
Reverse bias safe operating area
Ic = 6A, VCE = 450V
RBSOA
Short circuit safe operating area
VCE =400V
SCSOA
Allowable offset voltage slew rate
U to UN, V to VN, W to WN
dv/dt
VBS=15V (Note 4), per driver
ID
-
Driver Section
Gate driver consumption current
VDD = 15V, total
ID
-
1.3
2.6
mA
2.5
-
-
V
Low level Input voltage
HINU, HINV, HINW, LINU, LINV, LINW
to GND
Vin H
Vin L
-
-
0.8
V
Logic 1 input current
VIN = +3.3V
IIN+
-
100
143
μA
Logic 0 input current
VIN = 0V
IIN-
-
-
2
μA
Bootstrap ON Resistance
IB = 1mA
RB
-
110
300
Ω
FAULT terminal sink current
FAULT : ON / VFAULT=0.1V
High level Input voltage
FAULT clearance delay time
ENABLE ON/OFF voltage
ITRIP threshold voltage
IoSD
-
2
-
mA
FLTCLR
1
2
3
ms
VEN ON-state voltage
VEN +
2.5
-
-
V
VEN OFF-state voltage
VEN 
-
-
0.8
V
ITRIP to GND
VITRIP
0.44
0.49
0.54
V
-
550
-
ns
100
350
-
ns
ITRIP to shutdown propagation delay
tITRIP
ITRIP blanking time
tITRIPBL
VDD and VBS supply undervoltage
VDDUV+
10.5
11.1
11.7
V
VBSUV+
positive going input threshold
VDD and VBS supply undervoltage
VDDUV10.3
10.9
11.5
V
VBSUVnegative going input threshold
VDD and VBS supply undervoltage Ilockout
VDDUVH
0.14
0.2
V
VBSUVH
hysteresis
7. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted.
Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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STK5C4U332J-E
6
6
5
IF, FOWERD CURRENT (A)
IC, COLLECTOR CURRENT (A)
TYPICAL CHARACTERISTICS
TJ = 25C
4
3
TJ = 100C
2
1
0
0.0
0.5
1.0
1.5
2.0
2.5
VCE, COLLECTOR-EMITTER VOLTAGE (V)
TJ = 25C
4
3
TJ = 100C
2
1
0
0.0
3.0
Figure 5 VCE versus ID for different temperatures
(VDD=15V)
0.5
1.0
1.5
2.0
2.5
VF, FOWERD VOLTAGE (V)
3.0
Figure 4 VF versus ID for different temperatures
0.5
0.05
Eoff, SWITCHIG LOSS (mJ)
Eon, SWITCHING LOSS (mJ)
5
0.4
0.3
TJ = 100C
0.2
TJ = 25C
0.1
0.0
0
1
2
3
4
5
6
IC, COLLECTOR CURRENT (A)
7
8
0.04
0.03
TJ = 100C
0.02
TJ = 25C
0.01
0.00
0
Figure 8 EON versus ID for different temperatures
1
2
3
4
5
6
7
IC, COLLECTOR CURRENT (A)
Figure 7 EOFF versus ID for different temperatures
STANDARDIZED SQUARE-WAVE
PEAK R(t)
1.0
0.8
0.6
0.4
0.2
0.0
0.000001
0.0001
0.01
1
8
100
ON-PULSE WIDTH (S)
Figure 6 Thermal impedance plot
X:100ns/div
X:100ns/div
Vce: 100V/div
Io:2A/div
Vce: 100V/div
Io:2A/div
Figure 9 Turn-on waveform Tj=100C, VCC=400V
Figure 10 Turn-off waveform Tj=100C, VCC=400V
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STK5C4U332J-E
APPLICATIONS INFORMATION
Input / Output Timing Chart
Figure 11. Input/Output Timing Chart
Notes
1. This section of the timing diagram shows the effect of cross-conduction prevention.
2. This section of the timing diagram shows that when the voltage on VDD decreases sufficiently all gate output signals will go low,
switching off all six IGBTs. When the voltage on VDD rises sufficiently, normal operation will resume.
3. This section shows that when the bootstrap voltage VBS drops, the corresponding high side output (U or V or W) is switched off.
When VBS rises sufficiently, normal operation will resume.
4. This section shows that when the voltage on ITRIP exceeds the threshold, all IGBT’s are turned off. Normal operation resumes
later after the over-current condition is removed.
5. After VDD has risen above the threshold to enable normal operation, the driver waits to receive an input signal on the LIN input
before enabling the driver for the HIN signal.
Input / Output Logic Table
INPUT
OUTPUT
HIN
LIN
Itrip
Enable
High side
IGBT
Low side
IGBT
U,V,W
FAULT
H
L
L
H
ON (Note 5)
OFF
VP
OFF
L
H
L
H
OFF
ON
NU,NV,NW
OFF
L
L
L
H
OFF
OFF
High Impedance
OFF
H
H
L
H
OFF
OFF
High Impedance
OFF
X
X
H
H
OFF
OFF
High Impedance
ON
X
X
X
L
OFF
OFF
High Impedance
OFF
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STK5C4U332J-E
Thermistor characteristics
Parameter
Resistance
B-Constant (25 to 50℃)
Symbol
Condition
Min
Typ
Max
Unit
R25
Tc=25℃
99
100
101
kΩ
R100
Tc=100℃
B
5.18
5.38
5.60
kΩ
4208
4250
4293
K
+125
℃
40
Temperature Range
Figure 10 Thermistor resistance versus case temperature
Figure 11 Voltage on circuit connected to thermistor
(RTH=39k, pull-up voltage 5V, see Figure 2)
Figure 9 Thermistor Resistance versus Case Temperature
Figure 12 Thermistor Voltage versus Case Temperature
Conditions: RTH=39kΩ, pull-up voltage 5.0V (see Figure 2)
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STK5C4U332J-E
Fault output
Calculation of bootstrap capacitor value
The FAULT output is an open drain output requiring a
pull-up resistor. If the pull-up voltage is 5V, use a pullup resistor with a value of 6.8kΩ or higher. If the pullup voltage is 15V, use a pull-up resistor with a value of
20kΩ or higher. The FAULT output is triggered if
there is a VDD undervoltage or an overcurrent
condition.
The bootstrap capacitor value CB is calculated using
the following approach. The following parameters
influence the choice of bootstrap capacitor:

VBS: Bootstrap power supply.
15V is recommended.
QG: Total gate charge of IGBT at VBS=15V.
34nC
UVLO: Falling threshold for UVLO.
Specified as 12V.
IDMAX: High side drive consumption current.
Specified as 0.4mA
tONMAX: Maximum ON pulse width of high
side IGBT.


Undervoltage lockout protection
If VDD goes below the VDD supply undervoltage
lockout falling threshold, the FAULT output is
switched on. The FAULT output stays on until VDD
rises above the VDD supply undervoltage lockout
rising threshold. After VDD has risen above the
threshold to enable normal operation, the driver waits
to receive an input signal on the LIN input before
enabling the driver for the HIN signal.


Capacitance calculation formula:
CB = (QG + IDMAX * tONMAX)/(VBS - UVLO)
Overcurrent protection
CB is recommended to be approximately 3 times the
value calculated above. The recommended value of CB
is in the range of 1 to 47μF, however, the value needs
to be verified prior to production. When not using the
bootstrap circuit, each high side driver power supply
requires an external independent power supply.
An over-current condition is detected if the voltage on
the ITRIP pin is larger than the reference voltage.
There is a blanking time of typically 350ns to improve
noise immunity. After a shutdown propagation delay of
typically 0.55 s, the FAULT output is switched on.
The FAULT output is held on for a time determined by
the resistor and capacitor connected to the RCIN pin. If
RCIN pin is unconnected, the internal RC components
set fault clear time to 2ms (typical).
The internal bootstrap circuit uses a MOSFET. The
turn on time of this MOSFET is synchronized with the
turn on of the low side IGBT. The bootstrap capacitor
is charged by turning on the low side IGBT.
The over-current protection threshold should be set to
be equal or lower to 2 times the module rated current
(IO).
If the low side IGBT is held on for a long period of
time (more than one second for example), the bootstrap
voltage on the high side MOSFET will slowly
discharge.
Bootstrap Capacitance CB F
An additional fuse is recommended to protect against
system level or abnormal over-current fault conditions.
Capacitors on High Voltage and VDD supplies
Both the high voltage and VDD supplies require an
electrolytic capacitor and an additional high frequency
capacitor.
Enable pin
The ENABLE terminal pin is used to enable or shut
down the built-in driver. If the voltage on the ENABLE
pin rises above the ENABLE ON-state voltage, the
output drivers are enabled. If the voltage on the
ENABLE pin falls below the ENABLE OFF-state
voltage, the drivers are disabled.
100
10
1
0.1
0.01
0.1
1
10
tONMAX [ms]
100
1000
Figure 13: Bootstrap capacitance versus tONMAX
Minimum input pulse width
When input pulse width is less than 1μs, an output may
not react to the pulse. (Both ON signal and OFF signal)
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STK5C4U332J-E
Mounting Instructions
Item
Recommended Condition
Pitch
26.0±0.1mm (Please refer to Package Outline Diagram)
Screw
Diameter : M3
Screw head types : pan head, truss head, binding head
Washer
Plane washer dimensions (Figure 14)
D = 7mm, d = 3.2mm and t = 0.5mm JIS B 1256
Heat sink
Torque
Grease
Material: Aluminum or Copper
Warpage (the surface that contacts IPM ) : 50 to 50 μm
Screw holes must be countersunk.
No contamination on the heat sink surface that contacts IPM.
Temporary tightening : 50 to 60 % of final tightening on first screw
Temporary tightening : 50 to 60 % of final tightening on second screw
Final tightening : 0.4 to 0.6Nm on first screw
Final tightening : 0.4 to 0.6Nm on second screw
Silicone grease.
Thickness : 50 to 100 μm
Uniformly apply silicon grease to whole back.
Thermal foils are only recommended after careful evaluation. Thickness, stiffness and
compressibility parameters have a strong influence on performance.
Recommended
Notrecommended
Siliconegrease
Figure 14: Module Mounting details: components; washer drawing; need for even spreading of thermal grease
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STK5C4U332J-E
TEST CIRCUITS
■ ICE
ICE
U+
V+
W+
U-
V-
W-
M
38
38
38
32
26
20
N
32
26
20
17
18
19
VBS=15V
VBS=15V
U+,V+,W+ : High side phase
U-,V-,W- : Low side phase
34
A
M
32
28
26
VCE
22
VBS=15V
VBS=15V
20
2
1
N
Figure 15 Test Circuit for ICE
■ VCE(sat) (Test by pulse)
VBS=15V
U+
V+
W+
U-
V-
W-
M
38
38
38
32
26
20
N
32
26
20
17
18
19
m
3
4
5
6
7
8
VBS=15V
34
M
32
26
V
22
VBS=15V
VDD=15V
5V
VCE(sat)
20
2
m
N
1,10,N
Figure 16 Test circuit for VCE (SAT)
■ VF (Test by pulse)
U+
V+
W+
U-
V-
W-
M
38
38
38
32
26
20
N
32
26
20
17
18
19
Figure 17 Test circuit for VF
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Ic
STK5C4U332J-E
M
■ RB (Test by pulse)
U+
V+
W+
M
2
2
2
N
34
28
22
6
5V
7
V
8
VB
(RB)
IB
2
VDD=15V
N
1,3,4,5,10
Figure 18 Test circuit for RB
ID
■ ID
A
VBS U+
VBS V+
VBS W+
VDD
M
34
28
22
2
N
32
26
20
1
M
VD
N
Figure 19 Test circuit for ID
■ Switching time (The circuit is a representative example of the low side U phase.)
Input signal
(0 to5V)
VBS=15V
VBS=15V
90%
34
38
32
28
26
32
22
VBS=15V
Io
10%
tON
VDD=15V
Input signal
tOFF
Vcc
CS
20
Ic
2
6
17
1,10
Figure 20 Switching time test circuit
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STK5C4U332J-E
PACKAGE DIMENSIONS
unit : mm
5.8
9.8
The tolerances of length are +/ 0.5mm unless otherwise specified.
+0
0 .4- 0..205
5°
38
1
20
(10)
18.2
STK5C4U332J
1 .7
3.4
R
2-
(21.1)
20
29.6
26.4±0.1
26±0.1(Screw pitch)
note2
missing pin : 15, 16, 21, 23, 24, 25, 27,
29, 30, 31, 33, 35, 36, 37
1
4
19
note1
note3
+0.2
0.5 -0.05
1
3.4
18×1.0=18
4.3
5.8
9.8
1
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nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
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