MC100EL29 D

MC100EL29
5VECL Dual Differential
Data and Clock D Flip−Flop
With Set and Reset
Description
The MC100EL29 is a dual master−slave flip flop. The device
features fully differential Data and Clock inputs as well as outputs.
Data enters the master latch when the clock is LOW and transfers to
the slave upon a positive transition on the clock input.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The differential inputs have special circuitry which ensures device
stability under open input conditions. When both differential inputs
are left open the D input will pull down to VEE and the D input will
bias around VCC/2. The outputs will go to a defined state, however the
state will be random based on how the flip flop powers up.
Both flip flops feature asynchronous, overriding Set and Reset
inputs. Note that the Set and Reset inputs cannot both be HIGH
simultaneously.
The 100 Series Contains Temperature Compensation
Features
•
•
•
•
•
•
•
•
•
•
•
•
1100 MHz Flip−Flop Toggle Frequency
580 ps Propagation Delays
Q Output will Default LOW with Inputs Open or at VEE
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.7 V
Internal Input Pulldown Resistors on D(s), CLK(s), S(s), and R(s).
ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 100 V
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level:
Pb = 1
Pb−Free = 3
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V−0 @ 1.125 in,
Oxygen Index: 28 to 34
Transistor Count = 313 devices
Pb−Free Package is Available*
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SO−20
WB SUFFIX
CASE 751D
MARKING DIAGRAM*
20
100EL29
AWLYYWWG
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 4
1
Publication Order Number:
MC100EL29/D
MC100EL29
R0
VCC
Q0
Q0
S0
S1
VCC
Q1
Q1
VEE
20
19
18
17
16
15
14
13
12
11
Q
Q
R
S
D
1
CLK
2
D0
3
Q
Q
D
CLK
S
4
5
R
6
7
D0 CLK0 CLK0 VBB D1
8
9
10
D1 CLK1 CLK1 R1
* All VCC pins are tied together on the die.
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. Logic Diagram and Pinout: 20-Lead SOIC (Top View)
Table 1. PIN DESCRIPTION
Table 2. TRUTH TABLE
PIN
D0, D0; D1, D1
R0−R1
CLK0, CLK0; CLK1, CLK1
S0−S1
Q0, Q0; Q1, Q1
VBB
VCC
VEE
FUNCTION
R*
S*
D*
CLK*
Q
Q
ECL Differential Data Inputs
ECL Reset Inputs
ECL Differential Clock Inputs
ECL Set Inputs
ECL Differential Data Outputs
Reference Voltage Output
Positive Supply
Negative Supply
L
L
H
L
H
L
L
L
H
H
L
H
X
X
X
Z
Z
X
X
X
L
H
L
H
Undef
H
L
H
L
Undef
Z = LOW to HIGH Transition
* Pins will default LOW when left open.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Mode Power Supply
VEE = 0 V
8
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
−6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
SOIC−20
SOIC−20
90
60
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
SOIC−20
30 to 35
°C/W
Tsol
Wave Solder
265
265
°C
Pb
Pb−Free
VI VCC
VI VEE
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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MC100EL29
Table 4. 100EL SERIES PECL DC CHARACTERISTICS VCC = 5.0 V; VEE = 0.0 V (Note 1)
−40°C
Symbol
Characteristic
Min
25°C
Typ
Max
Min
85°C
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
130
156
130
156
130
156
mA
IEE
Power Supply Current
35
50
35
50
35
50
mA
VOH
Output HIGH Voltage (Note 2)
3915
3995
4120
3975
4045
4120
3975
4050
4120
mV
VOL
Output LOW Voltage (Note 2)
3170
3305
3445
3190
3295
3380
3190
3295
3380
mV
VIH
Input HIGH Voltage (Single−Ended)
3835
4120
3835
4120
3835
4120
mV
VIL
Input LOW Voltage (Single−Ended)
3190
3525
3190
3525
3190
3525
mV
VBB
Output Voltage Reference
3.62
3.74
3.62
3.74
3.62
3.74
V
VIHCMR
Common Mode Range
(Differential Configuration) (Note 3)
VPP < 500 mV
VPP ≥ 500 mV
IIH
Input HIGH Current
IIL
Input LOW Current
V
1.3
1.5
4.6
4.6
1.2
1.4
4.6
4.6
150
0.5
1.2
1.4
4.6
4.6
150
0.5
150
0.5
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / −0.5 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP min and
1 V.
Table 5. 100E SERIES NECL DC CHARACTERISTICS VCC = 0.0 V; VEE = −5.0 V (Note 4)
−40°C
Symbol
Characteristic
Min
25°C
Typ
Max
35
50
Min
85°C
Typ
Max
35
50
Min
Typ
Max
Unit
35
50
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 5)
−1085
−1005
−880
−1025
−955
−880
−1025
−955
−880
mV
VOL
Output LOW Voltage (Note 5)
−1830
−1695
−1555
−1810
−1705
−1620
−1810
−1705
−1620
mV
VIH
Input HIGH Voltage (Single−Ended)
−1165
−880
−1165
−880
−1165
−880
mV
VIL
Input LOW Voltage (Single−Ended)
−1810
−1475
−1810
−1475
−1810
−1475
mV
VBB
Output Voltage Reference
−1.38
−1.26
−1.38
−1.26
−1.38
−1.26
V
VIHCMR
Common Mode Range
(Differential Configuration) (Note 6)
VPP < 500 mV
VPP ≥ 500 mV
IIH
Input HIGH Current
IIL
Input LOW Current
V
−3.7
−3.5
−0.4
−0.4
−3.8
−3.6
150
0.5
−0.4
−0.4
−3.8
−3.6
150
0.5
−0.4
−0.4
150
0.5
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / −0.5 V.
5. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
6. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP min and
1 V.
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MC100EL29
Table 6. AC CHARACTERISTICS VCC = 5.0 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −5.0 V (Note 7)
−40°C
Symbol
Min
Characteristic
25°C
Typ
Max
Min
TBD
85°C
Typ
Max
Min
Max
Maximum Toggle Frequency
tPLH
tPHL
Propagation Delay
to Output
tS
tH
Setup Time
Hold Time
0
100
0
100
0
100
ps
tRR
Set/Reset Recovery
100
100
100
ps
tPW
Minimum Pulse Width CLK, Set, Reset
400
400
400
ps
tJITTER
Cycle−to−Cycle Jitter
VPP
Input Swing (Note 8)
150
1000
150
1000
150
1000
mV
tr
tf
Output Rise/Fall Times Q
(20% − 80%)
280
550
280
550
280
550
ps
480
480
680
700
TBD
Unit
fmax
CLK
S, R
TBD
Typ
500
500
TBD
700
720
520
520
TBD
GHz
720
740
TBD
ps
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. VEE can vary vary +0.8 V / −0.5 V.
8. VPP (min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40.
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 2. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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MC100EL29
ORDERING INFORMATION
Package
Shipping †
MC100EL29DW
SOIC−20
38 Units / Rail
MC100EL29DWG
SOIC−20
(Pb−Free)
38 Units / Rail
MC100EL29DWR2
SOIC−20
1000 / Tape & Reel
MC100EL29DWR2G
SOIC−20
(Pb−Free)
1000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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MC100EL29
PACKAGE DIMENSIONS
SO−20 WB
CASE 751D−05
ISSUE G
A
20
q
X 45 _
E
h
H
M
10X
0.25
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
B
0.25
M
T A
S
B
S
L
A
18X
e
A1
SEATING
PLANE
C
T
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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MC100EL29/D