MC14076B 4-Bit D-Type Register with Three-State Outputs The MC14076B 4−Bit Register consists of four D−type flip−flops operating synchronously from a common clock. OR gated output−disable inputs force the outputs into a high−impedance state for use in bus organized systems. OR gated data−disable inputs cause the Q outputs to be fed back to the D inputs of the flip−flops. Thus they are inhibited from changing state while the clocking process remains undisturbed. An asynchronous master root is provided to clear all four flip−flops simultaneously independent of the clock or disable inputs. http://onsemi.com SOIC−16 D SUFFIX CASE 751B Features • Three−State Outputs with Gated Control Lines • Fully Independent Clock Allows Unrestricted Operation for the • • • • • • Two Modes: Parallel Load and Do Nothing Asynchronous Master Reset Four Bus Buffer Registers Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load Over the Rated Temperature Range NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant MARKING DIAGRAM 16 14076BG AWLYWW 1 A WL, L YY, Y WW, W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. MAXIMUM RATINGS (Voltages Referenced to VSS) Parameter Value Unit −0.5 to +18.0 V −0.5 to VDD + 0.5 V Input or Output Current (DC or Transient) per Pin ±10 mA PD Power Dissipation, per Package (Note 1) 500 mW Symbol VDD Vin, Vout Iin, Iout DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) TA Ambient Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. © Semiconductor Components Industries, LLC, 2014 August, 2014 − Rev. 8 1 Publication Order Number: MC14076B/D MC14076B PIN ASSIGNMENT OUTPUT DISABLE A {B 1 16 VDD 2 15 R Q0 3 14 D0 Q1 4 13 D1 Q2 5 12 D2 Q3 6 11 D3 C 7 10 B VSS 8 9 A }DATA DISABLE BLOCK DIAGRAM 15 14 13 12 11 10 9 7 2 1 RESET Q0 3 Q1 4 DATA DISABLE Q2 5 CLOCK B OUTPUT A DISABLE Q3 6 D0 D1 D2 D3 B A VDD = PIN 16 VSS = PIN 8 FUNCTION TABLE Inputs Data Disable Reset Clock A B Data D Output Q 1 X X X X 0 0 0 X X X Qn 0 1 X X Qn 0 X 1 X Qn 0 0 0 0 0 0 0 0 1 1 When either output disable A or B (or both) is (are) high the output is disabled to the high−impedance state; however sequential operation of the flip−flops is not affected. X = Don’t Care. http://onsemi.com 2 MC14076B ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) −55_C Characteristic Output Voltage Vin = VDD or 0 Symbol 25_C VDD Vdc Min Max Min Typ (Note 2) 125_C Max Min Max Unit “0” Level VOL 5.0 10 15 − − − 0.05 0.05 0.05 − − − 0 0 0 0.05 0.05 0.05 − − − 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 − − − 4.95 9.95 14.95 5.0 10 15 − − − 4.95 9.95 14.95 − − − Vdc “0” Level VIL 5.0 10 15 − − − 1.5 3.0 4.0 − − − 2.25 4.50 6.75 1.5 3.0 4.0 − − − 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 − − − 3.5 7.0 11 2.75 5.50 8.25 − − − 3.5 7.0 11 − − − 5.0 5.0 10 15 –3.0 –0.64 –1.6 –4.2 − − − − –2.4 –0.51 –1.3 –3.4 –4.2 –0.88 –2.25 –8.8 − − − − –1.7 –0.36 –0.9 –2.4 − − − − IOL 5.0 10 15 0.64 1.6 4.2 − − − 0.51 1.3 3.4 0.88 2.25 8.8 − − − 0.36 0.9 2.4 − − − mAdc Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 mAdc Input Capacitance (Vin = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) IDD 5.0 10 15 − − − 5.0 10 20 − − − 0.005 0.010 0.015 5.0 10 20 − − − 150 300 600 mAdc Total Supply Current (Notes 3, 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IT 5.0 10 15 Three−State Leakage Current ITL 15 Vin = 0 or VDD Input Voltage (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) “1” Level VIH (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) Vdc Vdc IOH Source (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Sink mAdc IT = (0.75 mA/kHz) f + IDD IT = (1.50 mA/kHz) f + IDD IT = (2.25 mA/kHz) f + IDD ±0.1 − − ±0.0001 ±0.1 mAdc − ±3.0 mAdc Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002. http://onsemi.com 3 MC14076B SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C) Characteristic Symbol Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL Propagation Delay Time Clock to Q tPLH, tPHL = (1.7 ns/pF) CL + 215 ns tPLH, tPHL = (0.66 ns/pF) CL + 92 ns tPLH, tPHL = (0.5 ns/pF) CL + 65 ns tPLH, tPHL Reset to Q tPLH, tPHL = (1.7 ns/pF) CL + 215 ns tPLH, tPHL = (0.66 ns/pF) CL + 92 ns tPLH, tPHL = (0.5 ns/pF) CL + 65 ns VDD Vdc Min Typ (Note 6) Max 5.0 10 15 − − − 100 50 40 200 100 80 Unit ns ns 5.0 10 15 − − − 300 125 90 600 250 180 5.0 10 15 − − − 300 125 90 600 250 180 3−State Propagation Delay, Output “1” or “0” to High Impedance tPHZ, tPLZ 5.0 10 15 − − − 150 60 45 300 120 90 ns 3−State Propagation Delay, High Impedance to “1” or “0” Level tPZH, tPZL 5.0 10 15 − − − 200 80 60 400 160 120 ns Clock Pulse Width tWH 5.0 10 15 260 110 80 130 55 40 − − − ns Reset Pulse Width tWH 5.0 10 15 370 150 110 185 75 55 − − − ns Data Setup Time tsu 5.0 10 15 30 10 4 15 5 2 − − − ns Data Hold Time th 5.0 10 15 130 60 50 65 30 25 − − − ns Data Disable Setup Time tsu 5.0 10 15 220 80 50 110 40 25 − − − ns tTLH, tTHL 5.0 10 15 − − − − − − 15 5 4 ms fcl 5.0 10 15 − − − 3.6 9.0 12 1.8 4.5 6.0 MHz Clock Pulse Rise and Fall Time Clock Pulse Frequency 5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. http://onsemi.com 4 MC14076B 20ns D OUTPUT DISABLE A OR B INPUT RISE AND FALL 20 ns 90% 50% 10% th tsu INPUT INFORMATION tsu fcl OUTPUT VDD 10% tWL 90% 10% tPHZ 90% OUTPUTS CONNECTED OUTPUTS DISCONNECTED VOH VOL tTHL tTLH ANY Q OUTPUT RL = 1 kW OTHER INPUTS RESET = 0 DATA DISABLE A AND B = 0 OUTPUT DISABLE A AND B = 0 MC14076B OUTPUT DISABLE A OR B Figure 1. Timing Diagram tPZH 10% 50% 10% tPZL 90% ANY Q OUTPUT VSS tPHL tPLH Q ANY Q OUTPUT VSS 90% VDD 10% tPLZ 20ns 50% tWH 50% VDD th 20ns 90% 50% 1 2 D C 9 10 D D1 13 C CLOCK OUTPUTS CONNECTED VDD FOR tPLZ AND tPZL VSS FOR tPHZ AND tPZH Figure 2. Three−State Propagation Delay Waveshape and Circuit D0 14 DATA DISABLE A DATA DISABLE B VOH ≈ 2.5 V @ VDD = 5 V, 10 V, AND 15 V ≈ 2 V @ VDD = 5 V ≈ 6 V @ VDD = 10 V ≈ 10 V @ VDD = 15 V VOL CL EQUIVALENT FUNCTIONAL BLOCK DIAGRAM OUTPUT DISABLE A OUTPUT DISABLE B VSS Q R Q 3Q0 Q R Q 4Q1 7 D2 12 D3 11 D Q C R Q D Q C RESET 15 http://onsemi.com 5 R Q 5Q2 6Q3 MC14076B ORDERING INFORMATION Package Shipping† MC14076BDG SOIC−16 (Pb−Free) 48 Units / Rail MC14076BDR2G SOIC−16 (Pb−Free) 2500 Units / Tape & Reel NLV14076BDR2G* SOIC−16 (Pb−Free) 2500 Units / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 6 MC14076B PACKAGE DIMENSIONS SOIC−16 D SUFFIX CASE 751B−05 ISSUE K −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K DIM A B C D F G J K M P R F X 45 _ C −T− SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 S SOLDERING FOOTPRINT* 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. 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