INTERSIL ISL28248FUZ

ISL28148, ISL28248, ISL28448
®
Data Sheet
September 21, 2010
4.5MHz, Single Dual and Quad Precision
Rail-to-Rail Input-Output (RRIO) Op Amps
with Very Low Input Bias Current
The ISL28148, ISL28248 and ISL28448 are 4.5MHz
low-power single, dual and quad operational amplifiers. The
parts are optimized for single supply operation from 2.4V to
5.5V, allowing operation from one lithium cell or two Ni-Cd
batteries.
The single, dual and quad feature an Input Range
Enhancement Circuit (IREC) which enables them to maintain
CMRR performance for input voltages greater than the
positive supply. The input signal is capable of swinging
0.25V above the positive supply and to 100mV below the
negative supply with only a slight degradation of the CMRR
performance. The output operation is rail-to-rail.
The parts draw minimal supply current (900µA per amplifier)
while meeting excellent DC accuracy, AC performance,
noise and output drive specifications. The ISL28148 features
an enable pin that can be used to turn the device off and
reduce the supply current to a maximum of 16µA. Operation
is guaranteed over -40°C to +125°C temperature range.
FN6337.4
Features
• 4.5MHz gain bandwidth product
• 900µA supply current (per amplifier)
• 1.8mV maximum offset voltage
• 1pA typical input bias current
• Down to 2.4V single supply operation
• Rail-to-rail input and output
• Enable pin (ISL28148 SOT-23 package only)
• -40°C to +125°C operation
• Pb-free (RoHS compliant)
Applications
• Low-end audio
• 4mA to 20mA current loops
• Medical devices
• Sensor amplifiers
• ADC buffers
• DAC output amplifiers
Ordering Information
PART NUMBER
(Note)
PACKAGE
(Pb-Free)
PART MARKING
PKG.
DWG. #
ISL28148FHZ-T7*
GABT (Note 2)
6 Ld SOT-23 (Tape and Reel)
P6.064A
ISL28148FHZ-T7A*
GABT (Note 2)
6 Ld SOT-23 (Tape and Reel)
P6.064A
ISL28248FBZ
28248 FBZ
8 Ld SOIC
M8.15E
ISL28248FBZ-T7*
28248 FBZ
8 Ld SOIC (Tape and Reel)
M8.15E
ISL28248FUZ
8248Z
8 Ld MSOP
M8.118A
ISL28248FUZ-T7*
8248Z
8 Ld MSOP (Tape and Reel)
M8.118A
Coming Soon, ISL28448FVZ
MXZ
14 Ld TSSOP
M14.173
Coming Soon, ISL28448FVZ-T7*
MXZ
14 Ld TSSOP (Tape and Reel)
M14.173
*Please refer to TB347 for details on reel specifications.
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
2. The part marking is located on the bottom of the part.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2007, 2008, 2010. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL28148, ISL28248, ISL28448
Pinouts
ISL28248
(8 LD SOIC)
TOP VIEW
ISL28148
(6 LD SOT-23)
TOP VIEW
OUT 1
V- 2
+ -
IN+ 3
6 V+
OUT_A 1
5 EN
IN-_A 2
4 IN-
IN+_A 3
8 V+
7 OUT_B
- +
6 IN-_B
+ -
V- 4
ISL28448
(14 LD TSSOP)
TOP VIEW
ISL28248
(8 LD MSOP)
TOP VIEW
OUT_A 1
8 V+
- +
IN+_A 3
+ -
V- 4
7 OUT_B
IN-_A 2
6 IN-_B
IN+_A 3
5 IN+_B
14 OUT_D
OUT_A 1
- +
+ -
11 V-
V+ 4
IN+_B 5
OUT_B 7
2
10 IN+_C
+ -
IN-_B 6
13 IN-_D
12 IN+_D
- +
IN-_A 2
5 IN+_B
9 IN-_C
8 OUT_C
FN6337.4
September 21, 2010
ISL28148, ISL28248, ISL28448
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.75V
Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/µs
Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1200V
Thermal Resistance (Typical, Note 3)
θJA (°C/W)
6 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . .
230
8 Ld SO Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
125
8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . .
175
14 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . .
115
Ambient Operating Temperature Range . . . . . . . . .-40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VOS
V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open, TA = +25°C unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data
established by characterization.
DESCRIPTION
Input Offset Voltage
ΔV OS
--------------ΔT
Input Offset Voltage vs Temperature
IOS
Input Offset Current
IB
CONDITIONS
MIN
(Note 4)
TYP
MAX
(Note 4)
UNIT
ISL28148
-1.8
-2
0
1.8
2
mV
ISL28248 and ISL28448
-1.8
-2.8
0
1.8
2.8
mV
0.03
µV/°C
-35
-80
±5
35
80
pA
TA = -40°C to +85°C
-30
-80
±1
30
80
pA
TA = -40°C to +85°C
Input Bias Current
CMIR
Common-Mode Voltage Range
Guaranteed by CMRR
0
CMRR
Common-Mode Rejection Ratio
VCM = 0V to 5V
75
70
98
5
dB
V
PSRR
Power Supply Rejection Ratio
V+ = 2.4V to 5.5V
80
75
98
dB
AVOL
Large Signal Voltage Gain
VO = 0.5V to 4.5V, RL = 100kΩ to VCM
200
150
580
V/mV
VO = 0.5V to 4.5V, RL = 1kΩ to VCM
50
VOUT
Maximum Output Voltage Swing
Output low, RL = 100kΩ to VCM
3
6
8
mV
Output low, RL = 1kΩ to VCM
50
70
110
mV
V/mV
Output high, RL = 100kΩ to VCM
4.994
4.99
4.998
V
Output high, RL = 1kΩ to VCM
4.93
4.89
4.95
V
IS,ON
Quiescent Supply Current, Enabled
Per Amplifier
0.9
1.25
1.4
mA
IS,OFF
Quiescent Supply Current, Disabled
ISL28148 SOT-23 package only
10
14
16
µA
IO+
Short-Circuit Output Source Current
RL = 10Ω to VCM
3
48
45
75
mA
FN6337.4
September 21, 2010
ISL28148, ISL28248, ISL28448
Electrical Specifications
PARAMETER
V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open, TA = +25°C unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data
established by characterization. (Continued)
DESCRIPTION
CONDITIONS
IO-
Short-Circuit Output Sink Current
RL = 10Ω to VCM
VSUPPLY
Supply Operating Range
V+ to V-
VENH
EN Pin High Level
ISL28148 SOT-23 package only
VENL
EN Pin Low Level
ISL28148 SOT-23 package only
IENH
EN Pin Input High Current
V EN = V+, ISL28148 SOT-23 package
only
IENL
EN Pin Input Low Current
MIN
(Note 4)
TYP
-68
2.4
MAX
(Note 4)
UNIT
-48
-45
mA
5.5
V
2
V
0.8
V
1
1.5
1.6
µA
V EN = V-, ISL28148 SOT-23 package only
12
25
30
nA
AC SPECIFICATIONS
GBW
Gain Bandwidth Product
AV = 100, RF = 100kΩ, RG = 1kΩ,
RL = 10kΩ to VCM
4.5
MHz
Unity Gain
Bandwidth
-3dB Bandwidth
AV =1, RF = 0Ω, VOUT = 10mVP-P,
RL = 10kΩ to VCM
13
MHz
eN
Input Noise Voltage Peak-to-Peak
f = 0.1Hz to 10Hz
2
µVPP
iN
Input Noise Voltage Density
fO = 1kHz
28
nV/√Hz
Input Noise Current Density
fO = 1kHz
0.016
pA/√Hz
VCM = 1VP-P, RL = 10kΩ to VCM
85
dB
PSRR- @
120Hz
CMRR @ 60Hz Input Common Mode Rejection Ratio
Power Supply Rejection Ratio (V-)
V+, V- = ±1.2V and ±2.5V,
VSOURCE = 1VP-P, RL = 10kΩ to VCM
-82
dB
PSRR+ @
120Hz
Power Supply Rejection Ratio (V+)
V+, V- = ±1.2V and ±2.5V
VSOURCE = 1VP-P, RL = 10kΩ to VCM
-100
dB
±4
V/µs
TRANSIENT RESPONSE
SR
Slew Rate
tr, tf, Large
Signal
Rise Time, 10% to 90%, VOUT
AV = +2, VOUT = 3VP-P, RG = RF = 10kΩ
RL = 10kΩ to VCM
530
ns
Fall Time, 90% to 10%, VOUT
AV = +2, VOUT = 3VP-P, RG = RF = 10kΩ
RL = 10kΩ to VCM
530
ns
Rise Time, 10% to 90%, VOUT
AV = +2, VOUT = 10mVP-P,
RG = RF = RL = 10kΩ to VCM
50
ns
Fall Time, 90% to 10%, VOUT
AV = +2, VOUT = 10mVP-P,
RG = RF = RL = 10kΩ to VCM
50
ns
Enable to Output Turn-on Delay Time, 10% EN = 5V to 0V, AV = +2,
EN to 10% VOUT, (ISL28148)
RG = RF = RL = 1k to VCM
5
µs
Enable to Output Turn-off Delay Time, 10% VEN = 0V to 5V, AV = +2,
EN to 10% VOUT, (ISL28148)
RG = RF = RL = 1k to VCM
0.2
µs
tr, tf, Small
Signal
tEN
NOTE:
4. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
4
FN6337.4
September 21, 2010
ISL28148, ISL28248, ISL28448
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open
15
1
Rf = Rg = 100k
Rf = Rg = 10k
5
0
V+ = 5V
-5 RL = 1k
CL = 16.3pF
-10 AV = +2
VOUT = 10mVP-P
-15
100
1k
10k
Rf = Rg = 1k
100k
1M
10M
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
0
10
100M
VOUT = 100mV
-1
-2
VOUT = 50mV
-3
VOUT = 10mV
-4
VOUT = 1V
-5
-6 V = 5V
+
-7 RL = 1k
CL = 16.3pF
-8
AV = +1
-9
1k
10k
FREQUENCY (Hz)
10M
100M
FIGURE 2. GAIN vs FREQUENCY vs VOUT, RL = 1k
1
1
0
0
-1
VOUT = 100mV
-2
VOUT = 50mV
-3
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
1M
FREQUENCY (Hz)
FIGURE 1. GAIN vs FREQUENCY vs FEEDBACK RESISTOR
VALUES Rf/Rg
VOUT = 10mV
-4
VOUT = 1V
-5
-6
V+ = 5V
RL = 10k
CL = 16.3pF
AV = +1
-7
-8
-9
1k
10k
-2
VOUT = 50mV
-3
VOUT = 10mV
-4
1M
10M
-6
-7
-9
100M
VOUT = 1V
-5
-8
100k
VOUT = 100mV
-1
V+ = 5V
RL = 100k
CL = 16.3pF
AV = +1
1k
10k
FREQUENCY (Hz)
60
-1
AV = 101
GAIN (dB)
RL = 100k
-3
-4
-5
-9
100M
V+ = 5V
VOUT = 10mVP-P
CL = 16.3pF
AV = +1
1k
10k
AV = 1, Rg = INF, Rf = 0
AV = 10, Rg = 1k, Rf = 9.09k
AV = 101, Rg = 1k, Rf = 100k
AV = 1001, Rg = 1k, Rf = 1M
AV = 1001
50
RL = 10k
-2
-8
10M
FIGURE 4. GAIN vs FREQUENCY vs VOUT, RL = 100k
RL = 1k
0
-7
1M
70
1
-6
100k
FREQUENCY (Hz)
FIGURE 3. GAIN vs FREQUENCY vs VOUT, RL = 10k
NORMALIZED GAIN (dB)
100k
40
V+ = 5V
CL = 16.3pF
RL = 10k
VOUT = 10mVP-P
30
AV = 10
20
10
0
100k
1M
10M
FREQUENCY (Hz)
FIGURE 5. GAIN vs FREQUENCY vs RL
5
100M
-10
100
AV = 1
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 6. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
FN6337.4
September 21, 2010
ISL28148, ISL28248, ISL28448
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open
1
V+ = 5V
-1
-2
V+ = 2.4V
-3
-4
-5
-6
-7
-8
RL = 10k
CL = 16.3pF
AV = +1
VOUT = 10mVP-P
-9
10k
100k
1M
10M
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
0
100M
(Continued)
8
7
6
5
4
3
2
1
0
-1
-2
-3 V+ = 5V
-4 RL = 1k
-5 A = +1
V
-6
VOUT = 10mVP-P
-7
-8
10k
100k
FREQUENCY (Hz)
CL = 51.7pF
CL = 43.7pF
CL = 37.7pF
CL = 26.7pF
CL = 16.7pF
CL = 4.7pF
1M
10M
100M
FREQUENCY (Hz)
FIGURE 8. GAIN vs FREQUENCY vs CL
FIGURE 7. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
10
20
0
0
-10
PSRR (dB)
CMRR (dB)
-30
-40
-50
V+ = 2.4V, 5V
RL = 1k
CL = 16.3pF
AV = +1
VCM = 1VP-P
-60
-70
-80
-90
100
1k
10k
100k
FREQUENCY (Hz)
1M
-60
PSRR+
-100
-120
100
10M
20
1k
10k
100k
FREQUENCY (Hz)
V+, V- = ±1.2V
RL = 1k
CL = 16.3pF
AV = +1
VCM = 1VP-P
1M
10M
FIGURE 10. PSRR vs FREQUENCY, V+, V- = ±1.2V
PSRR-
-20
-40
-60
PSRR+
-80
-100
1k
10k
100k
V+, V- = ±2.5V
RL = 1k
CL = 16.3pF
AV = +1
VCM = 1VP-P
1M
FREQUENCY (Hz)
FIGURE 11. PSRR vs FREQUENCY V+, V- = ±2.5V
6
10M
INPUT VOLTAGE NOISE (nV/√Hz)
1000
0
PSRR (dB)
-40
-80
FIGURE 9. CMRR vs FREQUENCY; V+ = 2.4V AND 5V
-120
100
PSRR-
-20
-20
V+ = 5V
Rf = 1k Rg = 1k
AV = +2
100
10
1
10
100
1k
FREQUENCY (Hz)
10k
100k
FIGURE 12. INPUT VOLTAGE NOISE DENSITY vs FREQUENCY
FN6337.4
September 21, 2010
ISL28148, ISL28248, ISL28448
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open
(Continued)
0
0.1
-0.5
INPUT NOISE (µV)
INPUT CURRENT NOISE (pA/√Hz)
V+ = 5V
Rf = 1k Rg = 1k
AV = +2
-1.0
-1.5
-2.0
RL = 10k
V+ = 5V
CL = 16.3pF AV = 10k
Rg = 10
Rf = 100k
-2.5
0.01
1
10
100
1k
10k
-3.0
100k
0
1
2
3
4
FREQUENCY (Hz)
5
6
TIME (s)
7
8
9
10
FIGURE 14. INPUT VOLTAGE NOISE 0.1Hz TO 10Hz
FIGURE 13. INPUT CURRENT NOISE DENSITY vs FREQUENCY
0.025
2.0
SMALL SIGNAL (V)
1.0
0.5
0
V+, V- = ±2.5V
RL = 1k
CL = 16.3pF
Rg = Rf = 10k
AV = 2
VOUT = 3VP-P
-1.0
-1.5
-2.0
0
1
2
3
4
5
6
TIME (µs)
7
8
9
0.020
0.010
10
V+, V- = ±2.5V
RL = 1k
CL = 16.3pF
Rg= Rf = 10k
AV = 2
VOUT = 10mVP-P
0.015
0
1
2
3
4
5
6
7
8
9
10
TIME (µs)
FIGURE 15. LARGE SIGNAL STEP RESPONSE
FIGURE 16. SMALL SIGNAL STEP RESPONSE
1.2
3.5
VOUT
VEN
3.0
1.0
2.5
0.8
V+ = 5V
Rg = Rf = 10k
CL = 16.3pF
AV = +2
VOUT = 1VP-P
2.0
1.5
1.0
0.5
0.6
0.4
0.2
RL = 10k
0
0
-0.5
OUTPUT (V)
-0.5
VENABLE (V)
LARGE SIGNAL (V)
1.5
0
10
20
30
40
50
60
TIME (µs)
70
80
90
-0.2
100
FIGURE 17. ISL28148 ENABLE TO OUTPUT RESPONSE
7
FN6337.4
September 21, 2010
ISL28148, ISL28248, ISL28448
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open
100
800
V+ = 5V
RL = OPEN
Rf = 100k, Rg = 100
AV = +1k
600
60
40
200
0
-200
20
0
-20
-40
-400
-60
-600
-80
0
1
2
3
VCM (V)
4
5
-1
1.2
10.5
1.1
9.5
MEDIAN
0.9
0.8
MIN
0.7
2
3
VCM (V)
4
5
6
MAX
8.5
MEDIAN
7.5
6.5
MIN
5.5
4.5
-20
0
20
40
60
80
TEMPERATURE (°C)
100
3.5
-40
120
FIGURE 20. SUPPLY CURRENT ENABLED vs TEMPERATURE
V+, V- = ±2.5V
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 21. SUPPLY CURRENT DISABLED vs
TEMPERATURE V+, V- = ±2.5V
2.0
2.0
MAX
1.5
MAX
1.5
1.0
1.0
VOS (mV)
0.5
MEDIAN
0
-0.5
0.5
MEDIAN
0
-0.5
-1.0
-1.0
MIN
-1.5
-2.0
-40
1
MAX
1.0
0.6
-40
0
FIGURE 19. INPUT BIAS CURRENT vs COMMON MODE
INPUT VOLTAGE
CURRENT (µA)
CURRENT (mA)
-100
6
FIGURE 18. INPUT OFFSET VOLTAGE vs COMMON MODE
INPUT VOLTAGE
VOS (mV)
V+ = 5V
RL = OPEN
Rf = 100k, Rg = 100
AV = +1k
80
IBIAS (pA)
VOS (µV)
400
-800
-1
(Continued)
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 22. VOS vs TEMPERATURE VIN = 0V, V+, V- = ±2.75V
8
MIN
-1.5
-2.0
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 23. VOS vs TEMPERATURE VIN = 0V, V+, V- = ±2.5V
FN6337.4
September 21, 2010
ISL28148, ISL28248, ISL28448
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open
2.0
300
MAX
1.5
250
1.0
200
IBIAS- (pA)
VOS (mV)
0.5
MEDIAN
0
-0.5
MIN
-20
0
MIN
0
20
40
60
80
TEMPERATURE (°C)
100
-50
-40
120
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 25. IBIAS- vs TEMPERATURE V+, V- = ±2.5V
FIGURE 24. VOS vs TEMPERATURE VIN = 0V, V+, V- = ±1.2V
250
10
0
200
MAX
150
MEDIAN
100
50
MAX
-10
IOS (pA)
IBIAS- (pA)
MEDIAN
100
50
-1.5
MIN
-20
MEDIAN
-30
MIN
-40
-50
0
-50
-40
MAX
150
-1.0
-2.0
-40
(Continued)
-60
-20
0
20
40
60
80
TEMPERATURE (°C)
100
-70
-40
120
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 27. IOS vs TEMPERATURE V+, V- = ±2.5V
FIGURE 26. IBIAS- vs TEMPERATURE V+, V- = ±1.2V
20
1750
10
1550
MAX
-10
-20
AVOL (V/mV)
IOS (pA)
0
MEDIAN
-30
MIN
1350
1150
950
-40
550
-50
350
-60
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 28. IOS vs TEMPERATURE V+, V- = ±1.2V
9
MAX
750
150
-40
MEDIAN
MIN
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 29. AVOL vs TEMPERATURE RL = 100k, V+, V- = ±2.5V,
VO = -2V TO +2V
FN6337.4
September 21, 2010
ISL28148, ISL28248, ISL28448
80
140
70
130
MAX
50
MEDIAN
40
MAX
110
MEDIAN
100
90
30
20
-40
(Continued)
120
60
CMRR (dB)
AVOL (V/mV)
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open
MIN
-20
0
20
40
60
80
TEMPERATURE (°C)
MIN
80
100
70
-40
120
FIGURE 30. AVOL vs TEMPERATURE RL = 1k, V+, V- = ±2.5V,
VO = -2V TO +2V
-20
0
20
40
60
80
TEMPERATURE (°C)
4.970
130
4.965
MAX
MAX
120
4.960
VOUT (V)
PSRR (dB)
120
FIGURE 31. CMRR vs TEMPERATURE VCM = -2.5V TO +2.5V,
V+, V- = ±2.5V
140
110
100
MEDIAN
MIN
80
70
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
MEDIAN
MIN
4.945
100
4.940
-40
120
FIGURE 32. PSRR vs TEMPERATURE V+, V- = ±1.2V TO ±2.75V
-20
0
100
120
75
70
4.9992
MAX
MAX
65
VOUT (mV)
4.9990
4.9988
MEDIAN
60
MEDIAN
55
50
MIN
MIN
4.9984
4.9982
-40
20
40
60
80
TEMPERATURE (°C)
FIGURE 33. VOUT HIGH vs TEMPERATURE RL = 1k,
V+, V- = ±2.5V
4.9994
4.9986
4.955
4.950
90
VOUT (V)
100
45
-20
0
20
40
60
80
TEMPERATURE (°C)
100
FIGURE 34. VOUT HIGH vs TEMPERATURE RL = 100k,
V+, V- = ±2.5V
10
120
40
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 35. VOUT LOW vs TEMPERATURE RL = 1k,
V+, V- = ±2.5V
FN6337.4
September 21, 2010
ISL28148, ISL28248, ISL28448
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open
95
3.3
+ OUTPUT SHORT CIRCUIT
CURRENT (mA)
3.1
VOUT (mV)
2.9
MAX
2.7
2.5
2.3
MEDIAN
2.1
MIN
1.9
1.7
1.5
-40
(Continued)
-20
0
20
40
60
80
TEMPERATURE (°C)
100
90
MAX
85
80
MEDIAN
75
70
MIN
65
60
-40
120
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 37. + OUTPUT SHORT CIRCUIT CURRENT vs
TEMPERATURE VIN = 2.55V, RL = 10,
V+, V- = ±2.5V
FIGURE 36. VOUT LOW vs TEMPERATURE RL = 100k,
V+, V- = ±2.5V
- OUTPUT SHORT CIRCUIT
CURRENT (mA)
-50
-55
MAX
-60
MEDIAN
-65
-70
MIN
-75
-80
-85
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 38. - OUTPUT SHORT CIRCUIT CURRENT vs TEMPERATURE VIN = -2.55V, RL = 10, V+, V- = ±2.5V
Pin Descriptions
ISL28148
(6 Ld SOT-23)
ISL28248
(8 Ld SO)
(8 Ld MSOP)
ISL28448
(14 Ld TSSOP)
PIN NAME
2 (A)
6 (B)
9 (C)
13 (D)
ININ-_A
IN-_B
IN-_C
IN-_D
4
2 (A)
6 (B)
FUNCTION
EQUIVALENT CIRCUIT
inverting input
V+
IN-
IN+
VCircuit 1
3
3 (A)
5 (B)
11
3 (A)
5 (B)
10 (C)
12 (D)
IN+
IN+_A
IN+_B
IN+_C
IN+_D
Non-inverting input
(See circuit 1)
FN6337.4
September 21, 2010
ISL28148, ISL28248, ISL28448
Pin Descriptions (Continued)
ISL28148
(6 Ld SOT-23)
ISL28248
(8 Ld SO)
(8 Ld MSOP)
ISL28448
(14 Ld TSSOP)
PIN NAME
2
4
11
V-
FUNCTION
Negative supply
EQUIVALENT CIRCUIT
V+
CAPACITIVELY
COUPLED
ESD CLAMP
VCircuit 2
1
1 (A)
7 (B)
1 (A)
7 (B)
8 (C)
14 (D)
OUT
OUT_A
OUT_B
OUT_C
OUT_D
Output
V+
OUT
VCircuit 3
6
8
5
4
V+
Positive supply
-
EN
Chip enable
(See circuit 2)
V+
EN
VCircuit 4
Applications Information
Introduction
The ISL28148, ISL28248 and ISL28448 are single, dual and
quad channel CMOS rail-to-rail input, output (RRIO)
micropower precision operational amplifiers. The parts are
designed to operate from single supply (2.4V to 5.5V) or dual
supply (±1.2V to ±2.75V). The parts have an input common
mode range that extends 0.25V above the positive rail and
100mV below the negative supply rail. The output can swing
within about 3mV of the supply rails with a 100kΩ load.
Rail-to-Rail Input
Many rail-to-rail input stages use two differential input pairs,
a long-tail PNP (or PFET) and an NPN (or NFET). Severe
penalties have to be paid for this circuit topology. As the
input signal moves from one supply rail to another, the
operational amplifier switches from one input pair to the
other causing drastic changes in input offset voltage and an
undesired change in magnitude and polarity of input offset
current.
The parts achieve input rail-to-rail operation without
sacrificing important precision specifications and degrading
distortion performance. The devices’ input offset voltage
exhibits a smooth behavior throughout the entire
common-mode input range. The input bias current vs the
common-mode voltage range gives us an undistorted
12
behavior from typically 100mV below the negative rail and
0.25V higher than the V+ rail.
Rail-to-Rail Output
A pair of complementary MOS devices are used to achieve
the rail-to-rail output swing. The NMOS sinks current to swing
the output in the negative direction. The PMOS sources
current to swing the output in the positive direction. The
devices’ with a 100kΩ load will swing to within 3mV of the
positive supply rail and within 3mV of the negative supply rail.
Results of Overdriving the Output
Caution should be used when overdriving the output for long
periods of time. Overdriving the output can occur in two ways:
1. The input voltage times the gain of the amplifier exceeds the
supply voltage by a large value or
2. The output current required is higher than the output stage
can deliver. These conditions can result in a shift in the Input
Offset Voltage (VOS) as much as 1µV/hr. of exposure under
these condition.
IN+ and IN- Input Protection
All input terminals have internal ESD protection diodes to both
positive and negative supply rails, limiting the input voltage to
within one diode beyond the supply rails. They also contain
back-to-back diodes across the input terminals (“Pin
Descriptions” table - Circuit 1 on page 11). For applications
where the input differential voltage is expected to exceed
FN6337.4
September 21, 2010
ISL28148, ISL28248, ISL28448
0.5V, an external series resistor must be used to ensure the
input currents never exceed 5mA (Figure 39).
VIN
VOUT
RIN
RL
+
FIGURE 39. INPUT CURRENT LIMITING
Enable/Disable Feature
The ISL28148 offers an EN pin that disables the device
when pulled up to at least 2.0V. In the disabled state (output
in a high impedance state), the part consumes typically 10µA
at room temperature. By disabling the part, multiple
ISL28148 parts can be connected together as a MUX. In this
configuration, the outputs are tied together in parallel and a
channel can be selected by the EN pin. The loading effects
of the feedback resistors of the disabled amplifier must be
considered when multiple amplifier outputs are connected
together. Note that feed-through from the IN+ to IN- pins
occurs on any Mux Amp disabled channel where the input
differential voltage exceeds 0.5V (e.g., active channel
VOUT = 1V, while disabled channel VIN = GND), so the mux
implementation is best suited for small signal applications. If
large signals are required, use series IN+ resistors, or large
value RF, to keep the feed-through current low enough to
minimize the impact on the active channel. See “Limitations
of the Differential Input Protection” on page 13 for more
details.The EN pin also has an internal pull-down. If left
open, the EN pin will pull to the negative rail and the device
will be enabled by default. When not used, the EN pin should
either be left floating or connected directly to the V- pin.
Limitations of the Differential Input Protection
If the input differential voltage is expected to exceed 0.5V, an
external current limiting resistor must be used to ensure the
input current never exceeds 5mA. For non-inverting unity gain
applications the current limiting can be via a series IN+ resistor,
or via a feedback resistor of appropriate value. For other gain
configurations, the series IN+ resistor is the best choice, unless
the feedback (RF) and gain setting (RG) resistors are both
sufficiently large to limit the input current to 5mA.
Large differential input voltages can arise from several
sources:
visible distortion occurs on the input and output signals. To
avoid this issue, keep the input slew rate below 4.8V/µs, or
use appropriate current limiting resistors.
Large (>2V) differential input voltages can also cause an
increase in disabled ICC.
Using Only One Channel
If the application does not use all channels, then the user
must configure the unused channel(s) to prevent them from
oscillating. The unused channel(s) will oscillate if the input
and output pins are floating. This will result in higher than
expected supply currents and possible noise injection into
the channel being used. The proper way to prevent this
oscillation is to short the output to the negative input and
ground the positive input (as shown in Figure 40).
+
FIGURE 40. PREVENTING OSCILLATIONS IN UNUSED
CHANNELS
Proper Layout Maximizes Performance
To achieve the maximum performance of the high input
impedance and low offset voltage, care should be taken in
the circuit board layout. The PC board surface must remain
clean and free of moisture to avoid leakage currents
between adjacent traces. Surface coating of the circuit board
will reduce surface moisture and provide a humidity barrier,
reducing parasitic resistance on the board. When input
leakage current is a concern, the use of guard rings around
the amplifier inputs will further reduce leakage currents.
Figure 41 shows a guard ring example for a unity gain
amplifier that uses the low impedance amplifier output at the
same voltage as the high impedance input to eliminate
surface leakage. The guard ring does not need to be a
specific width, but it should form a continuous loop around
both inputs. For further reduction of leakage currents,
components can be mounted to the PC board using Teflon
standoff insulators.
.
HIGH IMPEDANCE INPUT
V+
IN
• During open loop (comparator) operation. Used this way,
the IN+ and IN- voltages don’t track, so differentials arise.
• When the amplifier is disabled but an input signal is still
present. An RL or RG to GND keeps the IN- at GND, while
the varying IN+ signal creates a differential voltage. Mux
Amp applications are similar, except that the active
channel VOUT determines the voltage on the IN- terminal.
• When the slew rate of the input pulse is considerably
faster than the op amp’s slew rate. If the VOUT can’t keep
up with the IN+ signal, a differential voltage results, and
13
FIGURE 41. GUARD RING EXAMPLE FOR UNITY GAIN
AMPLIFIER
Current Limiting
These devices have no internal current-limiting circuitry. If
the output is shorted, it is possible to exceed the Absolute
Maximum Rating for output current or power dissipation,
potentially resulting in the destruction of the device.
FN6337.4
September 21, 2010
ISL28148, ISL28248, ISL28448
Power Dissipation
where:
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power-supply
conditions. It is therefore important to calculate the
maximum junction temperature (TJMAX) for all applications
to determine if power supply voltages, load conditions, or
package type need to be modified to remain in the safe
operating area. These parameters are related in Equation 1:
• TMAX = Maximum ambient temperature
T JMAX = T MAX + ( θ JA xPD MAXTOTAL )
(EQ. 1)
where:
• θJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation of 1 amplifier
• VS = Supply voltage (Magnitude of V+ and V-)
• IMAX = Maximum supply current of 1 amplifier
• VOUTMAX = Maximum output voltage swing of the
application
• RL = Load resistance
• PDMAXTOTAL is the sum of the maximum power
dissipation of each amplifier in the package (PDMAX)
• PDMAX for each amplifier can be calculated as shown in
Equation 2:
V OUTMAX
PD MAX = 2*V S × I SMAX + ( V S - V OUTMAX ) × ---------------------------RL
(EQ. 2)
14
FN6337.4
September 21, 2010
ISL28148, ISL28248, ISL28448
Package Outline Drawing
P6.064A
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 0, 2/10
1.90
0-3°
0.95
D
0.08-0.20
A
5
6
4
PIN 1
INDEX AREA
2.80
3
1.60
3
0.15 C D
2x
5
(0.60)
1
3
2
0.20 C
2x
0.40 ±0.05
B
SEE DETAIL X
3
0.20 M C A-B
D
TOP VIEW
2.90
5
END VIEW
10° TYP
(2 PLCS)
0.15 C A-B
2x
H
1.14 ±0.15
1.45 MAX
C
SIDE VIEW
0.10 C
0.05-0.15
SEATING PLANE
DETAIL "X"
(0.25) GAUGE
PLANE
0.45±0.1
4
(0.60)
(1.20)
NOTES:
(2.40)
(0.95)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
3.
Dimension is exclusive of mold flash, protrusions or gate burrs.
4.
Foot length is measured at reference to guage plane.
5.
This dimension is measured at Datum “H”.
6.
Package conforms to JEDEC MO-178AA.
(1.90)
TYPICAL RECOMMENDED LAND PATTERN
15
FN6337.4
September 21, 2010
ISL28148, ISL28248, ISL28448
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.10 C
0.175 ± 0.075
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
(5.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5.
The pin #1 identifier may be either a mold or mark feature.
6.
Reference to JEDEC MS-012.
TYPICAL RECOMMENDED LAND PATTERN
16
FN6337.4
September 21, 2010
ISL28148, ISL28248, ISL28448
Package Outline Drawing
M8.118A
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP)
Rev 0, 9/09
A
3.0±0.1
8
0.25
CAB
3.0±0.1
4.9±0.15
DETAIL "X"
1.10 Max
PIN# 1 ID
B
SIDE VIEW 2
1
0.18 ± 0.05
2
0.65 BSC
TOP VIEW
0.95 BSC
0.86±0.09
GAUGE
PLANE
H
C
0.25
SEATING PLANE
0.33 +0.07/ -0.08
0.08 C A B
0.10 ± 0.05
3°±3°
0.10 C
0.55 ± 0.15
DETAIL "X"
SIDE VIEW 1
5.80
NOTES:
4.40
3.00
1.
Dimensions are in millimeters.
2.
Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSE Y14.5m-1994.
3.
Plastic or metal protrusions of 0.15mm max per side are not
included.
4.
Plastic interlead protrusions of 0.25mm max per side are not
included.
5.
Dimensions “D” and “E1” are measured at Datum Plane “H”.
6.
This replaces existing drawing # MDP0043 MSOP 8L.
0.65
0.40
1.40
TYPICAL RECOMMENDED LAND PATTERN
17
FN6337.4
September 21, 2010
ISL28148, ISL28248, ISL28448
Thin Shrink Small Outline Plastic Packages (TSSOP)
M14.173
N
INDEX
AREA
E
0.25(0.010) M
E1
2
SYMBOL
3
0.05(0.002)
-A-
INCHES
GAUGE
PLANE
-B1
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
B M
0.25
0.010
SEATING PLANE
L
A
D
-C-
α
e
A1
b
A2
c
0.10(0.004)
0.10(0.004) M
C A M
B S
MIN
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
MILLIMETERS
MIN
MAX
NOTES
A
-
0.047
-
1.20
-
A1
0.002
0.006
0.05
0.15
-
A2
0.031
0.041
0.80
1.05
-
b
0.0075
0.0118
0.19
0.30
9
c
0.0035
0.0079
0.09
0.20
-
D
0.195
0.199
4.95
5.05
3
E1
0.169
0.177
4.30
4.50
4
e
0.026 BSC
0.65 BSC
-
E
0.246
0.256
6.25
6.50
-
L
0.0177
0.0295
0.45
0.75
6
8o
0o
N
NOTES:
MAX
α
14
0o
14
7
8o
Rev. 2 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
18
FN6337.4
September 21, 2010