ISL28148, ISL28248, ISL28448 ® Data Sheet March 13, 2008 4.5MHz, Single Dual and Quad Precision Rail-to-Rail Input-Output (RRIO) Op Amps with Very Low Input Bias Current The ISL28148, ISL28248 and ISL28448 are 4.5MHz low-power single, dual and quad operational amplifiers. The parts are optimized for single supply operation from 2.4V to 5.5V, allowing operation from one lithium cell or two Ni-Cd batteries. The single, dual and quad feature an Input Range Enhancement Circuit (IREC) which enables them to maintain CMRR performance for input voltages greater than the positive supply. The input signal is capable of swinging 0.25V above the positive supply and to 100mV below the negative supply with only a slight degradation of the CMRR performance. The output operation is rail-to-rail. The parts draw minimal supply current (900µA per amplifier) while meeting excellent DC accuracy, AC performance, noise and output drive specifications. The ISL28148 features an enable pin that can be used to turn the device off and reduce the supply current to a maximum of 16µA. Operation is guaranteed over -40°C to +125°C temperature range. FN6337.2 Features • 4.5MHz gain bandwidth product • 900µA supply current (per amplifier) • 1.8mV maximum offset voltage • 1pA typical input bias current • Down to 2.4V single supply operation • Rail-to-rail input and output • Enable pin (ISL28148 SOT-23 package only) • -40°C to +125°C operation • Pb-free (RoHS compliant) Applications • Low-end audio • 4mA to 20mA current loops • Medical devices • Sensor amplifiers • ADC buffers • DAC output amplifiers Ordering Information PART NUMBER PACKAGE (Pb-free) PART MARKING PKG. DWG. # ISL28148FHZ-T7* (Note 1) GABT 6 Ld SOT-23 (Tape and Reel) MDP0038 ISL28148FHZ-T7A* (Note 1) GABT 6 Ld SOT-23 (Tape and Reel) MDP0038 Coming Soon, ISL28148FIZ-T7 (Note 2) 178Z 6 Ld WLCSP (1.5mmx1.0mm) W3x2.6C Coming Soon, ISL28248FBZ (Note 1) 28248BZ 8 Ld SOIC MDP0027 Coming Soon, ISL28248FBZ-T7* (Note 1) 28248BZ 8 Ld SOIC (Tape and Reel) MDP0027 Coming Soon, ISL28248FUZ (Note 1) 8248Z 8 Ld MSOP MDP0043 Coming Soon, ISL28248FUZ-T7* (Note 1) 8248Z 8 Ld MSOP (Tape and Reel) MDP0043 Coming Soon, ISL28448FVZ (Note 1) MXZ 14 Ld TSSOP MDP0044 Coming Soon, ISL28448FVZ-T7* (Note 1) MXZ 14 Ld TSSOP (Tape and Reel) MDP0044 *Please refer to TB347 for details on reel specifications. NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. These Intersil Pb-free WLCSP and BGA packaged products products employ special Pb-free material sets; molding compounds/die attach materials and SnAgCu - e1 solder ball terminals, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free WLCSP and BGA packaged products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2007, 2008. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL28148, ISL28248, ISL28448 Pinouts ISL28148 (6 LD SOT-23) TOP VIEW OUT 1 6 V+ V- 2 5 EN + - IN+ 3 4 IN- ISL28148 (6 LD WLCSP) TOP VIEW 1 2 A NC OUT B V+ V- C IN - IN + ISL28248 (8 LD MSOP) TOP VIEW ISL28248 (8 LD SOIC) TOP VIEW OUT_A 1 - + IN+_A 3 + - V- 4 OUT_A 1 7 OUT_B IN-_A 2 6 IN-_B IN+_A 3 5 IN+_B V- 4 8 V+ 7 OUT_B - + + - 6 IN-_B 5 IN+_B ISL28448 (14 LD TSSOP) TOP VIEW OUT_A 1 IN-_A 2 14 OUT_D - + + - IN+_A 3 V+ 4 11 V- IN+_B 5 OUT_B 7 2 10 IN+_C + - IN-_B 6 13 IN-_D 12 IN+_D - + IN-_A 2 8 V+ 9 IN-_C 8 OUT_C FN6337.2 March 13, 2008 ISL28148, ISL28248, ISL28448 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.75V Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/μs Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V Thermal Resistance (Typical, Note 3) θJA (°C/W) 6 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . . 230 6 Ld WLCSP Package . . . . . . . . . . . . . . . . . . . . . . . 130 8 Ld SO Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . 175 14 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 115 Ambient Operating Temperature Range . . . . . . . . .-40°C to +125°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VOS V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open, TA = +25°C unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. DESCRIPTION CONDITIONS Input Offset Voltage CSP package ΔV OS --------------ΔT Input Offset Voltage vs Temperature IOS Input Offset Current IB MIN (Note 4) TYP MAX (Note 4) -1.8 -2 0 1.8 2 -1.0 -1.2 -0.1 1.0 1.2 0.03 UNIT mV µV/°C -35 -80 ±5 35 80 pA TA = -40°C to +85°C -30 -80 ±1 30 80 pA TA = -40°C to +85°C -40 -90 ±1 30 80 Input Bias Current CSP package CMIR Common-Mode Voltage Range Guaranteed by CMRR 0 CMRR Common-Mode Rejection Ratio VCM = 0V to 5V 75 70 98 dB PSRR Power Supply Rejection Ratio V+ = 2.4V to 5.5V 80 75 98 dB AVOL Large Signal Voltage Gain VO = 0.5V to 4.5V, RL = 100kΩ to VCM 200 150 580 V/mV VO = 0.5V to 4.5V, RL = 1kΩ to VCM 50 V/mV Output low, RL = 100kΩ to VCM 3 6 8 mV Output low, RL = 1kΩ to VCM 50 70 110 mV VOUT Maximum Output Voltage Swing 3 5 V Output high, RL = 100kΩ to VCM 4.994 4.99 4.998 V Output high, RL = 1kΩ to VCM 4.93 4.89 4.95 V FN6337.2 March 13, 2008 ISL28148, ISL28248, ISL28448 Electrical Specifications PARAMETER V+ = 5V, V- = 0V,VCM = 2.5V, RL = Open, TA = +25°C unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued) DESCRIPTION CONDITIONS MIN (Note 4) TYP 0.7 0.4 MAX (Note 4) UNIT IS,ON Quiescent Supply Current, Enabled 0.9 1.1 1.4 mA IS,OFF Quiescent Supply Current, Disabled ISL28148 SOT-23 package only 10 14 16 µA IO+ Short-Circuit Output Source Current RL = 10Ω to VCM 48 45 75 mA IO- Short-Circuit Output Sink Current RL = 10Ω to VCM 50 45 68 mA VSUPPLY Supply Operating Range V+ to V- 2.4 VENH EN Pin High Level ISL28148 SOT-23 package only VENL EN Pin Low Level ISL28148 SOT-23 package only IENH EN Pin Input High Current V EN = V+,ISL28148 SOT-23 package only IENL EN Pin Input Low Current 5.5 2 V V 0.8 V 1 1.5 1.6 µA V EN = V-, ISL28148 SOT-23 package only 12 25 30 nA AC SPECIFICATIONS GBW Gain Bandwidth Product AV = 100, RF = 100kΩ, RG = 1kΩ, RL = 10kΩ to VCM 4.5 MHz Unity Gain Bandwidth -3dB Bandwidth AV =1, RF = 0Ω, VOUT = 10mVP-P, RL = 10kΩ to VCM 13 MHz eN Input Noise Voltage Peak-to-Peak f = 0.1Hz to 10Hz 2 µVPP Input Noise Voltage Density fO = 1kHz 28 nV/√Hz Input Noise Current Density fO = 1kHz 0.016 pA/√Hz iN CMRR @ 60Hz Input Common Mode Rejection Ratio VCM = 1VP-P, RL = 10kΩ to VCM 85 dB PSRR- @ 120Hz Power Supply Rejection Ratio (V-) V+, V- = ±1.2V and ±2.5V, VSOURCE = 1VP-P, RL = 10kΩ to VCM -82 dB PSRR+ @ 120Hz Power Supply Rejection Ratio (V+) V+, V- = ±1.2V and ±2.5V VSOURCE = 1VP-P, RL = 10kΩ to VCM -100 dB ±4 V/µs TRANSIENT RESPONSE SR Slew Rate tr, tf, Large Signal Rise Time, 10% to 90%, VOUT AV = +2, VOUT = 3VP-P, RG = RF = 10kΩ RL = 10kΩ to VCM 530 ns Fall Time, 90% to 10%, VOUT AV = +2, VOUT = 3VP-P, RG = RF = 10kΩ RL = 10kΩ to VCM 530 ns Rise Time, 10% to 90%, VOUT AV = +2, VOUT = 10mVP-P, RG = RF = RL = 10kΩ to VCM 50 ns Fall Time, 90% to 10%, VOUT AV = +2, VOUT = 10mVP-P, RG = RF = RL = 10kΩ to VCM 50 ns Enable to Output Turn-on Delay Time, 10% EN = 5V to 0V, AV = +2, EN to 10% VOUT, (ISL28148) RG = RF = RL = 1k to VCM 5 µs Enable to Output Turn-off Delay Time, 10% VEN = 0V to 5V, AV = +2, EN to 10% VOUT, (ISL28148) RG = RF = RL = 1k to VCM 0.2 µs tr, tf, Small Signal tEN NOTE: 4. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested. 4 FN6337.2 March 13, 2008 ISL28148, ISL28248, ISL28448 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open 15 1 Rf = Rg = 100k Rf = Rg = 10k 5 0 V+ = 5V -5 RL = 1k CL = 16.3pF -10 AV = +2 VOUT = 10mVP-P -15 100 1k Rf = Rg = 1k 10k 100k 1M 10M NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 0 10 100M VOUT = 100mV -1 -2 VOUT = 50mV -3 VOUT = 10mV -4 VOUT = 1V -5 -6 V = 5V + -7 RL = 1k CL = 16.3pF -8 AV = +1 -9 1k 10k FREQUENCY (Hz) 10M 100M FIGURE 2. GAIN vs FREQUENCY vs VOUT, RL = 1k 1 1 0 0 -1 VOUT = 100mV -2 VOUT = 50mV -3 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 1M FREQUENCY (Hz) FIGURE 1. GAIN vs FREQUENCY vs FEEDBACK RESISTOR VALUES Rf/Rg VOUT = 10mV -4 VOUT = 1V -5 -6 V+ = 5V RL = 10k CL = 16.3pF AV = +1 -7 -8 -9 1k 10k -2 VOUT = 50mV -3 VOUT = 10mV -4 1M 10M -6 -7 -9 100M VOUT = 1V -5 -8 100k VOUT = 100mV -1 V+ = 5V RL = 100k CL = 16.3pF AV = +1 1k 10k FREQUENCY (Hz) 1 RL = 10k -2 AV = 101 GAIN (dB) -4 -5 -6 -7 -8 -9 V+ = 5V VOUT = 10mVP-P CL = 16.3pF AV = +1 1k 10k 100M AV = 1, Rg = INF, Rf = 0 AV = 10, Rg = 1k, Rf = 9.09k AV = 101, Rg = 1k, Rf = 100k AV = 1001, Rg = 1k, Rf = 1M AV = 1001 50 RL = 100k -3 10M 70 60 -1 1M FREQUENCY (Hz) RL = 1k 0 100k FIGURE 4. GAIN vs FREQUENCY vs VOUT, RL = 100k FIGURE 3. GAIN vs FREQUENCY vs VOUT, RL = 10k NORMALIZED GAIN (dB) 100k 40 V+ = 5V CL = 16.3pF RL = 10k VOUT = 10mVP-P 30 AV = 10 20 10 0 100k 1M 10M FREQUENCY (Hz) FIGURE 5. GAIN vs FREQUENCY vs RL 5 100M -10 100 AV = 1 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 6. FREQUENCY RESPONSE vs CLOSED LOOP GAIN FN6337.2 March 13, 2008 ISL28148, ISL28248, ISL28448 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open 1 V+ = 5V -1 -2 V+ = 2.4V -3 -4 -5 -6 -7 -8 RL = 10k CL = 16.3pF AV = +1 VOUT = 10mVP-P -9 10k 100k 1M 10M NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 0 100M (Continued) 8 7 6 5 4 3 2 1 0 -1 -2 -3 V+ = 5V -4 RL = 1k -5 A = +1 V -6 VOUT = 10mVP-P -7 -8 10k 100k FREQUENCY (Hz) CL = 51.7pF CL = 43.7pF CL = 37.7pF CL = 26.7pF CL = 16.7pF CL = 4.7pF 1M 10M 100M FREQUENCY (Hz) FIGURE 7. GAIN vs FREQUENCY vs SUPPLY VOLTAGE FIGURE 8. GAIN vs FREQUENCY vs CL 10 20 0 0 -10 PSRR (dB) CMRR (dB) -30 -40 -50 V+ = 2.4V, 5V RL = 1k CL = 16.3pF AV = +1 VCM = 1VP-P -60 -70 -80 -90 100 1k 10k 100k FREQUENCY (Hz) 1M -60 PSRR+ -100 -120 100 10M 20 1k 10k 100k FREQUENCY (Hz) V+, V- = ±1.2V RL = 1k CL = 16.3pF AV = +1 VCM = 1VP-P 1M 10M FIGURE 10. PSRR vs FREQUENCY, V+, V- = ±1.2V PSRR- -20 -40 -60 PSRR+ -80 -100 1k 10k 100k V+, V- = ±2.5V RL = 1k CL = 16.3pF AV = +1 VCM = 1VP-P 1M FREQUENCY (Hz) FIGURE 11. PSRR vs FREQUENCY V+, V- = ±2.5V 6 10M INPUT VOLTAGE NOISE (nV/√Hz) 1000 0 PSRR (dB) -40 -80 FIGURE 9. CMRR vs FREQUENCY; V+ = 2.4V AND 5V -120 100 PSRR- -20 -20 V+ = 5V Rf=1k Rg=1k AV = +2 100 10 1 10 100 1k FREQUENCY (Hz) 10k 100k FIGURE 12. INPUT VOLTAGE NOISE DENSITY vs FREQUENCY FN6337.2 March 13, 2008 ISL28148, ISL28248, ISL28448 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open 0.1 (Continued) INPUT CURRENT NOISE (pA/÷Hz) 0 INPUT NOISE (µV) -0.5 V+ = 5V Rf=1k Rg=1k AV = +2 -1.0 -1.5 -2.0 RL = 10k V+ = 5V CL = 16.3pF AV = 10k Rg = 10 Rf = 100k -2.5 0.01 1 10 100 1k 10k -3.0 100k 0 1 2 3 4 FREQUENCY (Hz) FIGURE 13. INPUT CURRENT NOISE DENSITY vs FREQUENCY 5 6 TIME (s) 7 8 9 10 FIGURE 14. INPUT VOLTAGE NOISE 0.1Hz TO 10Hz 0.025 2.0 SMALL SIGNAL (V) 1.0 0.5 0 V+, V- = ±2.5V RL = 1k CL = 16.3pF Rg = Rf = 10k AV = 2 VOUT = 3VP-P -1.0 -1.5 -2.0 0 1 2 3 4 5 6 TIME (µs) 7 8 9 0.020 0.010 10 V+, V- = ±2.5V RL = 1k CL = 16.3pF Rg= Rf = 10k AV = 2 VOUT = 10mVP-P 0.015 0 1 2 3 4 5 6 7 8 9 10 TIME (µs) FIGURE 15. LARGE SIGNAL STEP RESPONSE FIGURE 16. SMALL SIGNAL STEP RESPONSE 1.2 3.5 VOUT VEN 3.0 1.0 2.5 0.8 V+ = 5V Rg = Rf = 10k CL = 16.3pF AV = +2 VOUT = 1VP-P 2.0 1.5 1.0 0.5 0.6 0.4 0.2 RL = 10k 0 0 -0.5 OUTPUT (V) -0.5 VENABLE (V) LARGE SIGNAL (V) 1.5 0 10 20 30 40 50 60 TIME (µs) 70 80 90 -0.2 100 FIGURE 17. ISL28148 ENABLE TO OUTPUT RESPONSE 7 FN6337.2 March 13, 2008 ISL28148, ISL28248, ISL28448 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open 100 800 V+ = 5V RL = OPEN Rf = 100k, Rg = 100 AV = +1k 600 400 V+ = 5V RL = OPEN Rf = 100k, Rg = 100 AV = +1k 80 60 40 200 IBIAS (pA) VOS (µV) (Continued) 0 -200 20 0 -20 -40 -400 -60 -600 -800 -1 -80 0 1 2 3 VCM (V) 4 5 -100 6 FIGURE 18. INPUT OFFSET VOLTAGE vs COMMON MODE INPUT VOLTAGE 4 5 6 MAX 9.5 CURRENT (µA) CURRENT (µA) 2 3 VCM (V) MAX 1.0 MEDIAN 0.9 0.8 MIN 0.7 8.5 MEDIAN 7.5 6.5 MIN 5.5 4.5 -20 0 20 40 60 80 TEMPERATURE (°C) 100 3.5 -40 120 FIGURE 20. SUPPLY CURRENT ENABLED vs TEMPERATURE V+, V- = ±2.5V -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 21. SUPPLY CURRENT DISABLED vs TEMPERATURE V+, V- = ±2.5V 2.0 2.0 MAX 1.5 MAX 1.5 1.0 1.0 0.5 VOS (mV) VOS (mV) 1 10.5 1.1 MEDIAN 0 -0.5 -1.0 0.5 MEDIAN 0 -0.5 -1.0 MIN -1.5 -2.0 -40 0 FIGURE 19. INPUT BIAS CURRENT vs COMMON MODE INPUT VOLTAGE 1.2 0.6 -40 -1 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 22. VOS vs TEMPERATURE VIN = 0V, V+, V- = ±2.75V 8 MIN -1.5 -2.0 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 23. VOS vs TEMPERATURE VIN = 0V, V+, V- = ±2.5V FN6337.2 March 13, 2008 ISL28148, ISL28248, ISL28448 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open 2.0 (Continued) 1.5 MAX MAX 1.5 1 0.5 MEDIAN 0 0.5 VOS (mV) VOS (mV) 1.0 -0.5 MEDIAN 0 -0.5 -1.0 -2.0 -40 -1 MIN -1.5 MIN -1.5 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 24. VOS vs TEMPERATURE VIN = 0V, V+, V- = ±1.2V -40 -20 0 MAX 1 0.5 0.5 VOS (mV) VOS (mV) 1 MEDIAN 0 MEDIAN 0 -0.5 -0.5 -1 -1 MIN MIN -1.5 -1.5 -20 0 20 40 60 80 TEMPERATURE (°C) 100 -40 120 FIGURE 26. CSP PACKAGE VOS vs TEMPERATURE VIN = 0V, V+, V- = ±2.5V 250 250 200 IBIAS- (pA) MAX 150 MEDIAN 100 -20 0 100 120 MAX 150 MEDIAN 100 50 50 20 40 60 80 TEMPERATURE (°C) FIGURE 27. CSP PACKAGE VOS vs TEMPERATURE VIN = 0V, V+, V- = ±1.2V 300 200 IBIAS- (pA) 120 1.5 MAX MIN MIN 0 0 -50 -40 100 FIGURE 25. CSP PACKAGE VOS vs TEMPERATURE VIN = 0V, V+, V- = ±2.75V 1.5 -40 20 40 60 80 TEMPERATURE (°C) -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 28. IBIAS- vs TEMPERATURE V+, V- = ±2.5V 9 -50 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 29. IBIAS- vs TEMPERATURE V+, V- = ±1.2V FN6337.2 March 13, 2008 ISL28148, ISL28248, ISL28448 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open 350 400 350 IBIAS - (pA) IBIAS -(pA) 200 150 150 100 MIN 50 0 0 -20 0 20 40 60 80 Temperature (C) 100 -50 -40 120 10 20 0 10 MAX -10 -20 IOS (pA) MIN -40 MAX -20 MEDIAN -30 -40 -60 -50 0 20 40 60 80 Temperature (C) -10 -50 -20 0 100 120 0 MEDIAN -30 -20 FIGURE 31. CSP PACKAGE IBIAS- vs TEMPERATURE V+, V- = ±1.2V FIGURE 30. CSP PACKAGE IBIAS- vs TEMPERATURE V+, V- = ±2.5V IOS (pA) 200 MIN 50 -70 -40 MEDIAN 250 MEDIAN 250 100 MAX 300 MAX 300 -50 -40 (Continued) 20 40 60 80 TEMPERATURE (°C) 100 -60 -40 120 FIGURE 32. IOS vs TEMPERATURE V+, V- = ±2.5V MIN -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 33. IOS vs TEMPERATURE V+, V- = ±1.2V 80 1750 70 1350 AVOL (V/mV) AVOL (V/mV) 1550 1150 950 MAX 750 550 MEDIAN 60 MAX 50 MEDIAN 40 30 MIN 350 150 -40 MIN -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 34. AVOL vs TEMPERATURE RL = 100k, V+, V- = ±2.5V, VO = -2V TO +2V 10 20 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 35. AVOL vs TEMPERATURE RL = 1k, V+, V- = ±2.5V, VO = -2V TO +2V FN6337.2 March 13, 2008 ISL28148, ISL28248, ISL28448 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open 140 140 MAX 130 130 MAX 120 PSRR (dB) CMRR (dB) 120 110 MEDIAN 100 90 110 100 MEDIAN 90 MIN MIN 80 80 70 -40 (Continued) -20 0 20 40 60 80 TEMPERATURE (°C) 100 70 -40 120 FIGURE 36. CMRR vs TEMPERATURE VCM = -2.5V TO +2.5V, V+, V- = ±2.5V -20 0 20 40 60 80 TEMPERATURE (°C) 4.9994 4.9992 4.965 MAX MAX 4.9990 VOUT (V) VOUT (V) 4.960 4.955 MEDIAN 4.945 0 4.9984 20 40 60 80 TEMPERATURE (°C) 100 120 4.9982 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 39. VOUT HIGH vs TEMPERATURE RL = 100k, V+, V- = ±2.5V FIGURE 38. VOUT HIGH vs TEMPERATURE RL = 1k, V+, V- = ±2.5V 3.3 75 3.1 70 2.9 MAX VOUT (mV) 65 VOUT (mV) MEDIAN MIN MIN -20 4.9988 4.9986 4.950 60 MEDIAN 55 MAX 2.7 2.5 2.3 MEDIAN 2.1 50 MIN MIN 1.9 45 40 -40 120 FIGURE 37. PSRR vs TEMPERATURE V+, V- = ±1.2V TO ±2.75V 4.970 4.940 -40 100 1.7 -20 0 20 40 60 80 TEMPERATURE (°C) 100 FIGURE 40. VOUT LOW vs TEMPERATURE RL = 1k, V+, V- = ±2.5V 11 120 1.5 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 41. VOUT LOW vs TEMPERATURE RL = 100k, V+, V- = ±2.5V FN6337.2 March 13, 2008 ISL28148, ISL28248, ISL28448 95 90 MAX 85 80 MEDIAN 75 70 MIN 65 60 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 - OUTPUT SHORT CIRCUIT CURRENT (mA) + OUTPUT SHORT CIRCUIT CURRENT (mA) Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open (Continued) -50 -55 MAX -60 MEDIAN -65 -70 MIN -75 -80 -85 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 43. - OUTPUT SHORT CIRCUIT CURRENT vs TEMPERATURE VIN = -2.55V, RL = 10, V+, V- = ±2.5V FIGURE 42. + OUTPUT SHORT CIRCUIT CURRENT vs TEMPERATURE VIN = -2.55V, RL = 10, V+, V- = ±2.5V Pin Descriptions ISL28148 (6 Ld SOT-23) 4 ISL28148 6 Ld WLCSP ISL28248 (8 Ld SO) (8 Ld MSOP) ISL28448 (14 Ld TSSOP) C1 2 (A) 6 (B) 2 (A) 6 (B) 9 (C) 13 (D) PIN NAME FUNCTION NC Not connected ININ-_A IN-_B IN-_C IN-_D inverting input EQUIVALENT CIRCUIT V+ IN- IN+ VCircuit 1 3 2 3 (A) 5 (B) 3 (A) 5 (B) 10 (C) 12 (D) IN+ IN+_A IN+_B IN+_C IN+_D 4 11 V- C2 B2 Non-inverting input Negative supply (See circuit 1) V+ CAPACITIVELY COUPLED ESD CLAMP VCircuit 2 1 A2 1 (A) 7 (B) 1 (A) 7 (B) 8 (C) 14 (D) OUT OUT_A OUT_B OUT_C OUT_D Output V+ OUT VCircuit 3 6 B1 8 12 4 V+ Positive supply (See circuit 2) FN6337.2 March 13, 2008 ISL28148, ISL28248, ISL28448 Pin Descriptions (Continued) ISL28148 (6 Ld SOT-23) ISL28148 6 Ld WLCSP ISL28248 (8 Ld SO) (8 Ld MSOP) 5 ISL28448 (14 Ld TSSOP) PIN NAME - EN FUNCTION EQUIVALENT CIRCUIT Chip enable V+ EN VCircuit 4 A1 NC Connect pin to the most Negative Supply Applications Information Results of Over-Driving the Output Introduction Caution should be used when over-driving the output for long periods of time. Over-driving the output can occur in two ways: 1. The input voltage times the gain of the amplifier exceeds the supply voltage by a large value or The ISL28148, ISL28248 and ISL28448 are single, dual and quad channel CMOS rail-to-rail input, output (RRIO) micropower precision operational amplifiers. The parts are designed to operate from single supply (2.4V to 5.5V) or dual supply (±1.2V to ±2.75V). The parts have an input common mode range that extends 0.25V above the positive rail and 100mV below the negative supply rail. The output operation can swing within about 3mV of the supply rails with a 100kΩ load. Rail-to-Rail Input Many rail-to-rail input stages use two differential input pairs, a long-tail PNP (or PFET) and an NPN (or NFET). Severe penalties have to be paid for this circuit topology. As the input signal moves from one supply rail to another, the operational amplifier switches from one input pair to the other causing drastic changes in input offset voltage and an undesired change in magnitude and polarity of input offset current. The parts achieve input rail-to-rail operation without sacrificing important precision specifications and degrading distortion performance. The devices’ input offset voltage exhibits a smooth behavior throughout the entire common-mode input range. The input bias current vs the common-mode voltage range gives us an undistorted behavior from typically 100mV below the negative rail and 0.25V higher than the V+ rail. Rail-to-Rail Output A pair of complementary MOS devices are used to achieve the rail-to-rail output swing. The NMOS sinks current to swing the output in the negative direction. The PMOS sources current to swing the output in the positive direction. The devices’ with a 100kΩ load will swing to within 3mV of the positive supply rail and within 3mV of the negative supply rail. 13 2. The output current required is higher than the output stage can deliver. These conditions can result in a shift in the Input Offset Voltage (VOS) as much as 1µV/hr. of exposure under these condition. IN+ and IN- Input Protection All input terminals have internal ESD protection diodes to both positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. They also contain back-to-back diodes across the input terminals (“Pin Descriptions” table - Circuit 1 on page 12). For applications where the input differential voltage is expected to exceed 0.5V, an external series resistor must be used to ensure the input currents never exceed 5mA (Figure 44). VIN VOUT RIN + RL FIGURE 44. INPUT CURRENT LIMITING Enable/Disable Feature The ISL28148 offers an EN pin that disables the device when pulled up to at least 2.0V. In the disabled state (output in a high impedance state), the part consumes typically 10µA at room temperature. By disabling the part, multiple ISL28148 parts can be connected together as a MUX. In this configuration, the outputs are tied together in parallel and a channel can be selected by the EN pin. The loading effects of the feedback resistors of the disabled amplifier must be considered when multiple amplifier outputs are connected together. Note that feed through from the IN+ to IN- pins occurs on any Mux Amp disabled channel where the input differential voltage exceeds 0.5V (e.g., active channel VOUT = 1V, while disabled channel VIN = GND), so the mux FN6337.2 March 13, 2008 ISL28148, ISL28248, ISL28448 implementation is best suited for small signal applications. If large signals are required, use series IN+ resistors, or large value RF, to keep the feed through current low enough to minimize the impact on the active channel. See “Limitations of the Differential Input Protection” on page 14 for more details.The EN pin also has an internal pull-down. If left open, the EN pin will pull to the negative rail and the device will be enabled by default. When not used, the EN pin should either be left floating or connected directly to the V- pin. Limitations of the Differential Input Protection If the input differential voltage is expected to exceed 0.5V, an external current limiting resistor must be used to ensure the input current never exceeds 5mA. For non-inverting unity gain applications the current limiting can be via a series IN+ resistor, or via a feedback resistor of appropriate value. For other gain configurations, the series IN+ resistor is the best choice, unless the feedback (RF) and gain setting (RG) resistors are both sufficiently large to limit the input current to 5mA. Proper Layout Maximizes Performance To achieve the maximum performance of the high input impedance and low offset voltage, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. When input leakage current is a concern, the use of guard rings around the amplifier inputs will further reduce leakage currents. Figure 46 shows a guard ring example for a unity gain amplifier that uses the low impedance amplifier output at the same voltage as the high impedance input to eliminate surface leakage. The guard ring does not need to be a specific width, but it should form a continuous loop around both inputs. For further reduction of leakage currents, components can be mounted to the PC board using Teflon standoff insulators. . Large differential input voltages can arise from several sources: HIGH IMPEDANCE INPUT IN • During open loop (comparator) operation. Used this way, the IN+ and IN- voltages don’t track, so differentials arise. • When the amplifier is disabled but an input signal is still present. An RL or RG to GND keeps the IN- at GND, while the varying IN+ signal creates a differential voltage. Mux Amp applications are similar, except that the active channel VOUT determines the voltage on the IN- terminal. • When the slew rate of the input pulse is considerably faster than the op amp’s slew rate. If the VOUT can’t keep up with the IN+ signal, a differential voltage results, and visible distortion occurs on the input and output signals. To avoid this issue, keep the input slew rate below 4.8V/μs, or use appropriate current limiting resistors. Large (>2V) differential input voltages can also cause an increase in disabled ICC. Using Only One Channel If the application does not use all channels, then the user must configure the unused channel(s) to prevent them from oscillating. The unused channel(s) will oscillate if the input and output pins are floating. This will result in higher than expected supply currents and possible noise injection into the channel being used. The proper way to prevent this oscillation is to short the output to the negative input and ground the positive input (as shown in Figure 45). - V+ FIGURE 46. GUARD RING EXAMPLE FOR UNITY GAIN AMPLIFIER Current Limiting These devices have no internal current-limiting circuitry. If the output is shorted, it is possible to exceed the Absolute Maximum Rating for output current or power dissipation, potentially resulting in the destruction of the device. Power Dissipation It is possible to exceed the +150°C maximum junction temperatures under certain load and power-supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related in Equation 1: T JMAX = T MAX + ( θ JA xPD MAXTOTAL ) (EQ. 1) where: • PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) • PDMAX for each amplifier can be calculated as shown in Equation 2: + FIGURE 45. PREVENTING OSCILLATIONS IN UNUSED CHANNELS 14 V OUTMAX PD MAX = 2*V S × I SMAX + ( V S - V OUTMAX ) × ---------------------------RL (EQ. 2) FN6337.2 March 13, 2008 ISL28148, ISL28248, ISL28448 where: • TMAX = Maximum ambient temperature • θJA = Thermal resistance of the package • PDMAX = Maximum power dissipation of 1 amplifier • VS = Supply voltage (Magnitude of V+ and V-) • IMAX = Maximum supply current of 1 amplifier • VOUTMAX = Maximum output voltage swing of the application • RL = Load resistance 15 FN6337.2 March 13, 2008 ISL28148, ISL28248, ISL28448 SOT-23 Package Family MDP0038 e1 D SOT-23 PACKAGE FAMILY A MILLIMETERS 6 N SYMBOL 4 E1 2 E 3 0.15 C D 1 2X 2 3 0.20 C 5 2X e 0.20 M C A-B D B b NX 0.15 C A-B 1 3 SOT23-5 SOT23-6 A 1.45 1.45 MAX A1 0.10 0.10 ±0.05 A2 1.14 1.14 ±0.15 b 0.40 0.40 ±0.05 c 0.14 0.14 ±0.06 D 2.90 2.90 Basic E 2.80 2.80 Basic E1 1.60 1.60 Basic e 0.95 0.95 Basic e1 1.90 1.90 Basic L 0.45 0.45 ±0.10 L1 0.60 0.60 Reference N 5 6 Reference D 2X TOLERANCE Rev. F 2/07 NOTES: C A2 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. SEATING PLANE A1 0.10 C 1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. NX 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only). (L1) 6. SOT23-5 version has no center lead (shown as a dashed line). H A GAUGE PLANE c L 16 0.25 0° +3° -0° FN6337.2 March 13, 2008 ISL28148, ISL28248, ISL28448 Wafer Level Chip Scale Package (WLCSP) W3x2.6C 3x2 ARRAY 6 BALL WAFER LEVEL CHIP SCALE PACKAGE E D PIN 1 ID TOP VIEW A2 A A1 SYMBOL MILLIMETERS A 0.51 Min, 0.55 Max A1 0.225 ±0.015 A2 0.305 ±0.013 b Φ0.323 ±0.025 D 0.955 ±0.020 D1 0.50 BASIC E 1.455 ±0.020 E1 1.00 BASIC e 0.50 BASIC SD 0.25 BASIC SE 0.00 BASIC Rev. 3 03/08 b NOTES: SIDE VIEW 1. All dimensions are in millimeters. E1 e SE D1 2 SD 1 b C B A BOTTOM VIEW 17 FN6337.2 March 13, 2008 ISL28148, ISL28248, ISL28448 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150”) 8 14 16 Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 18 FN6337.2 March 13, 2008 ISL28148, ISL28248, ISL28448 Mini SO Package Family (MSOP) 0.25 M C A B D MINI SO PACKAGE FAMILY (N/2)+1 N E MDP0043 A E1 MILLIMETERS PIN #1 I.D. 1 B (N/2) e H C SEATING PLANE 0.10 C N LEADS SYMBOL MSOP8 MSOP10 TOLERANCE NOTES A 1.10 1.10 Max. - A1 0.10 0.10 ±0.05 - A2 0.86 0.86 ±0.09 - b 0.33 0.23 +0.07/-0.08 - c 0.18 0.18 ±0.05 - D 3.00 3.00 ±0.10 1, 3 E 4.90 4.90 ±0.15 - E1 3.00 3.00 ±0.10 2, 3 e 0.65 0.50 Basic - L 0.55 0.55 ±0.15 - L1 0.95 0.95 Basic - N 8 10 Reference - 0.08 M C A B b Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. L1 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. A 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c SEE DETAIL "X" A2 GAUGE PLANE A1 L 0.25 3° ±3° DETAIL X 19 FN6337.2 March 13, 2008 ISL28148, ISL28248, ISL28448 Thin Shrink Small Outline Package Family (TSSOP) MDP0044 0.25 M C A B D THIN SHRINK SMALL OUTLINE PACKAGE FAMILY A (N/2)+1 N MILLIMETERS SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE PIN #1 I.D. E E1 1 (N/2) B 0.20 C B A 2X N/2 LEAD TIPS TOP VIEW 0.05 e C SEATING PLANE H A 1.20 1.20 1.20 1.20 1.20 Max A1 0.10 0.10 0.10 0.10 0.10 ±0.05 A2 0.90 0.90 0.90 0.90 0.90 ±0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 D 5.00 5.00 6.50 7.80 9.70 ±0.10 E 6.40 6.40 6.40 6.40 6.40 Basic E1 4.40 4.40 4.40 4.40 4.40 ±0.10 e 0.65 0.65 0.65 0.65 0.65 Basic L 0.60 0.60 0.60 0.60 0.60 ±0.15 L1 1.00 1.00 1.00 1.00 1.00 Reference Rev. F 2/07 0.10 M C A B b 0.10 C N LEADS SIDE VIEW NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. SEE DETAIL “X” 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c END VIEW L1 A A2 GAUGE PLANE 0.25 L A1 0° - 8° DETAIL X All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 20 FN6337.2 March 13, 2008