SUD50N03-06AP-DS

SPICE Device Model SUD50N03-06AP
Vishay Siliconix
N-Channel 30-V (D-S) MOSFET
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-V to 10-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 68100
S-80150Rev. A, 28-Jan-08
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SPICE Device Model SUD50N03-06AP
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Symbol
Test Condition
Simulated
Data
Gate Threshold Voltage
VGS(th)
VDS = VGS, ID = 250 µA
1.6
Drain-Source On-State Resistancea
rDS(on)
Parameter
Measured
Data
Unit
Static
V
VGS = 10 V, ID = 20 A
0.0047
0.0046
VGS = 4.5 V, ID = 20 A
0.0062
0.0062
Ω
Forward Transconductancea
gfs
VDS = 15 V, ID = 20 A
63
70
S
Forward Voltagea
VSD
IF = 6.7 A
0.83
0.90
V
3763
3800
651
615
Dynamicb
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
VDS = 15 V, VGS = 0 V, f = 1 MHz
224
VDS = 15 V, VGS = 10 V, ID = 30 A
VDS = 15 V, VGS = 4.5 V, ID =30 A
pF
305
57
62
29
30
11
11
9
9
nC
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
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Document Number: 68100
S-80150Rev. A, 28-Jan-08
SPICE Device Model SUD50N03-06AP
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 68100
S-80150Rev. A, 28-Jan-08
www.vishay.com
3
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Disclaimer
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Document Number: 91000
Revision: 18-Jul-08
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