82C83H CMOS Octal Latching Inverting Bus Driver March 1997 Features Description • Full 8-Bit Parallel Latching Buffer The Intersil 82C83H is a high performance CMOS Octal Latching Buffer manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C83H provides an 8bit parallel latch/buffer in a 20 lead pin package. The active high strobe (STB) input allows transparent transfer of data and latches data on the negative transition of this signal. The active low output enable (OE) permits simple interface to microprocessor systems. The 82C83H provides inverted data at the outputs. • Bipolar 8283 Compatible • Three-State Inverting Outputs • Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 25ns Max • Gated Inputs - Reduce Operating Power - Eliminate the Need for Pull-Up Resistors • Single 5V Power Supply Ordering Information • Low Power Operation - ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA • Operating Temperature Ranges - C82C83H . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC PART NO. CP82C83H PACKAGE 20 Ld PDIP IP82C83H CS82C83H - I82C83H . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC IS82C83H - M82C83H . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC CD82C83H 20 Ld PLCC 20 Pad CLCC 84067022A SMD# -40oC to +85oC E20.3 0oC to +70oC N20.35 -40oC to +85oC N20.35 F20.3 F20.3 -55oC to +125oC F20.3 -55oC to +125oC J20.A -55oC to +125oC J20.A MD82C83H/B MR82C83H/B E20.3 -40oC to +85oC 0oC to +70oC ID82C83H SMD# PKG. NO 0oC to +70oC 0oC to +70oC 20 Ld CERDIP 8406702RA TEMP RANGE F20.3 Pinouts DI2 3 18 DO1 DI3 4 17 DO2 DI4 5 16 DO3 DI5 6 DI6 7 DI7 OE DO0 19 DO0 VCC 20 VCC 2 DI0 1 DI1 DI1 DI0 82C83H (PLCC, CLCC) TOP VIEW DI2 82C83H (PDIP, CERDIP) TOP VIEW 3 2 1 20 19 5 17 DO2 15 DO4 DI5 6 16 DO3 14 DO5 DI6 7 15 DO4 8 13 DO6 DI7 8 14 DO5 9 12 DO7 GND 10 11 STB OE 9 11 12 13 PIN NAMES TRUTH TABLE STB OE DI DO X H X HI-Z H L L H H L H L ↓ L X † H = Logic One L = Logic Zero X = Don‘t Care 10 DO6 DI4 DO7 18 DO1 STB 4 GND DI3 PIN HI-Z = High Impedance ↓ = Negative Transition † = Latched to Value of Last Data DESCRIPTION DI0 - DI7 Data Input Pins DO0 - DO7 Data Output Pins STB Active High Strobe OE Active Low Output Enable CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 4-281 File Number 2971.1 82C83H Functional Diagram DI0 D Q CLK state). The 82C8X series gated inputs mean that this condition will occur only during the time the device is in the transparent mode (STB = logic one). ICC remains below the maximum ICC standby specification of 10µA during the time inputs are disabled, thereby greatly reducing the average power dissipation of the 82C8X series devices. DO0 DI1 DO1 DI2 DO2 DI3 DO3 DI4 DO4 DI5 DO5 OE DI6 DO6 DATA IN DI7 DO7 VCC P P VCC INTERNAL DATA N P N N OE STB FIGURE 2. 82C86H/87H GATED INPUTS Gated Inputs Decoupling Capacitors During normal system operation of a latch, signals on the bus at the device inputs will become high impedance or make transitions unrelated to the operation of the latch. These unrelated input transitions switch the input circuitry and typically cause an increase in power dissipation in CMOS devices by creating a low resistance path between VCC and GND when the signal is at or near the input switching threshold. Additionally, if the driving signal becomes high impedance (``float'' condition), it could create an indeterminate logic state at the inputs and cause a disruption in device operation. The Intersil 82C8X series of bus drivers eliminates these conditions by turning off data inputs when data is latched (STB = logic zero for the 82C82/83H) and when the device is disabled (OE = logic one for the 82C86H/87H). These gated inputs disconnect the input circuitry from the VCC and ground power supply pins by turning off the upper P-channel and lower N-channel (See Figures 1 and 2). No current flow from VCC to GND occurs during input transitions and invalid logic states from floating inputs are not transmitted. The next stage is held to a valid logic level internal to the device. VCC The transient current required to charge and discharge the 300pF load capacitance specified in the 82C83H data sheet is determined by I = CL (dv/dt) Assuming that all outputs change state at the same time and that dv/dt is constant; (V CC × 80 percent ) I = C L -------------------------------------------------------t ⁄t R where tR = 20ns, VCC = 5.0V, CL = 300pF on each eight outputs. I = (8 x 300 x 10-12) x (5.0V x 0.8)/(20 x 10-9) = 480mA This current spike may cause a large negative voltage spike on VCC which could cause improper operation of the device. To filter out this noise, it is recommended that a 0.1µF ceramic disc capacitor be placed between VCC and GND at each device, with placement being as near to the device as possible. ALE MULTIPLEXED BUS ICC VCC P (EQ. 1) F ADDRESS ADDRESS P STB VCC N P P INTERNAL DATA DATA IN VCC P N STB N N P INTERNAL DATA DATA IN N FIGURE 1. 82C82/83H D.C. input voltage levels can also cause an increase in ICC if these input levels approach the minimum VIH or maximum VIL conditions. This is due to the operation of the input circuitry in its linear operating region (partially conducting 4-282 N FIGURE 3. SYSTEM EFFECTS OF GATED INPUTS 82C83H Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND 0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical) θJAoC/W θJCoC/W CERDIP Package . . . . . . . . . . . . . . . . 70 16 CLCC Package . . . . . . . . . . . . . . . . . . 80 20 PDIP Package . . . . . . . . . . . . . . . . . . . 75 N/A PLCC Package . . . . . . . . . . . . . . . . . . 75 N/A Storage Temperature Range . . . . . . . . . . . . . . . . . .-65oC to +150oC Max Junction Temperature Ceramic Package . . . . . . . . . . . . . . +175oC Max Junction Temperature Plastic Package. . . . . . . . . . . . . . . . +150oC Lead Temperature (Soldering 10s) (PLCC - Lead Tips Only) . . +300oC Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range C82C83H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC I82C83H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC M82C83H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. DC Electrical Specifications SYMBOL VCC = 5.0V ± 10%; TA = 0oC to +70oC (C82C83H); TA = -40oC to +85oC (I82C83H); TA = -55oC to +125oC (M82C83H) PARAMETER VIH Logical One Input Voltage VIL Logical Zero Input Voltage VOH Logical One Output Voltage VOL Logical Zero Output Voltage MIN MAX UNITS 2.0 2.2 - V 0.8 V - V IOH = -8mA, IOH = -100mA, OE = GND 0.45 V IOL = 20mA, OE = GND 3.0 VCC -0.4V TEST CONDITIONS C82C83H, I82C83H, M82C83H, (Note 1) II Input Leakage Current -10 10 µA VIN = GND or VCC, DIP Pins 1-9,11 IO Output Leakage Current -10 10 µA VO = GND or OE ≥ VCC -0.5V DIP Pins 12-19 VIN = VCC or GND VCC = 5.5V Outputs Open lCCSB Standby Power Supply Current - 10 µA IC COP Operating Power Supply Current - 1 mA/ MHz TA = +25oC, VCC = 5V, Typical (See Note 2) NOTES: 1. VIH is measured by applying a pulse of magnitude = VlHMIN to one data Input at a time and checking the corresponding device output for a valid logical 1 - during valid input high time. Control pins (STB, CE) are tested separately with all device data input pins at VCC -0.4V. 2. Typical ICCOP = 1 mA/MHz of STB cycle time. (Example: 5MHz µP, ALE = 1.25MHz, ICCOP = 1.25mA). Capacitance SYMBOL CIN COUT TA = +25oC PARAMETER TYPICAL UNITS TEST CONDITIONS Input Capacitance 13 pF Output Capacitance 20 pF FREQ = 1MHz, all measurements are referenced to device GND 4-283 82C83H VCC = 5.0V ±10%; CL = 300pF (Note 1), FREQ = 1MHz TA = 0oC to +70oC (C82C83H); TA = -40oC to +85oC (l82C83H); TA = -55oC to +125oC (M82C83H) AC Electrical Specifications LIMITS SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS (1) TlVOV Propagation Delay Input to Output 5 25 ns See Notes 2, 3 (2) TSHOV Propagation Delay STB to Output 10 50 ns See Notes 2, 3 (3) TEHOZ Output Disable Time 5 22 ns See Notes 2, 3 (4) TELOV Output Enable Time 10 45 ns See Notes 2, 3 (5) TlVSL Input to STB Set Up Time 0 - ns See Notes 2, 3 (6) TSLIX Input to STB Hold Time 30 - ns See Notes 2, 3 (7) TSHSL STB High Time 15 - ns See Notes 2, 3 (8) TR, TF Input Rise/Fall Times - 20 ns See Notes 2, 3 NOTES: 1. Output load capacitance is rated 300pF for both ceramic and plastic packages. 2. All AC Parameters tested as per test load circuits. Input rise and tall times are driven at 1ns/V. 3. Input test signals must switch between VIL -0.4V and VlH +0.4V. Timing Waveforms TR, TF (8) INPUTS 2.0V 0.8V TIVSL (5) TSLIX (6) STB TSHSL (7) OE TIVOV (1) TELOV (4) TEHOZ (3) VOH -0.1V OUTPUTS 3.0V 0.45V VOL +0.1V TSHOV (2) All Timing measurements are made at 1.5V unless otherwise noted. FIGURE 4. TIMING WAVEFORMS Test Load Circuits 2.27V 1.5V 91Ω OUTPUT 180Ω TEST POINT OUTPUT 300pF (SEE NOTE) TEST POINT 300pF (SEE NOTE) FIGURE 5. TIVOV, TSHOV FIGURE 6. TELOV OUTPUT HIGH ENABLE 4-284 82C83H Test Load Circuits (Continued) 1.5V 2.27V 51Ω 91Ω TEST POINT OUTPUT TEST POINT OUTPUT 300pF (SEE NOTE) 50pF (SEE NOTE) NOTE: Includes jig and stray capacitance. FIGURE 8. TEHOZ OUTPUT LOW/HIGH DISABLE FIGURE 7. TELOV OUTPUT LOW ENABLE Burn-In Circuits F2 F2 R1 R1 R1 A 4 17 5 A 6 15 A 7 14 A 8 13 A 12 10 11 F2 A 16 9 3 R1 A F1 F2 VCC F2 R2 A F2 F2 R4 R4 R4 R4 R4 2 VCC R4 F2 F2 1 20 19 18 5 17 6 16 7 15 8 14 9 R2 2 4 F0 R3 F0 R1 A 18 10 11 12 13 R4 F2 R1 19 3 2 F2 R1 2 R4 F2 R1 F1 F2 R1 C1 20 VCC F2 R4 C1 1 R3 F2 R4 VCC R1 R4 F2 VCC FIGURE 10. MR82C83H CLCC FIGURE 9. MD82C83H CERDIP NOTES: 1. VCC = 5.5V ± 0.5V GND = 0V 2. VIH = 4.5V ± 10% 3. VIL = -0.2 to 0.4V 4. R1 = 47kW ± 5% 5. R2 = 2.0kW ± 5% 6. R3 = 1.0kW ± 5% 7. R4 = 5.0kW ± 5% 8. C1 = 0.01µF Minimum 9. F0 = 100kHz ± 10% 10. F1 = F0/2, F2 = F1/2, F3 = F2/2 4-285 R4 R4 R4 R4 R4 VCC 2 82C83H Die Characteristics DIE DIMENSIONS: 138.6 x 155.5 x 19 ± 1 mils GLASSIVATION: Type: SiO2 Thickness: 8kÅ ± 1kÅ METALLIZATION: Type: Silicon - Aluminum Thickness: 11kÅ ± 2kÅ WORST CASE CURRENT DENSITY: 2.0 x 105 A/cm2 Metallization Mask Layout 82C83H DI2 DI1 DI2 VCC DO0 DO1 DO2 DI3 DO3 DI4 DO4 DI5 DO5 DI6 DI7 OE GND STB DO7 DO6 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 4-286