HI1386 8-Bit, 75 MSPS, Flash A/D Converter August 1997 Features Description • Differential Linearity Error ±0.5 LSB or Less The HI1386 is an 8-bit, high-speed flash analog-to-digital converter IC capable of digitizing analog signals at a maximum rate of 75 MSPS. The digital I/O levels of this A/D converter are compatible with ECL 100K/10KH/10K. • Integral Linearity Error ±0.5 LSB or Less • Built-In Integral Linearity Compensation Circuit • High-Speed Operation with Maximum Conversion Rate (Min) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 MSPS • Low Input Capacitance (Typ) . . . . . . . . . . . . . . . . . 17pF The HI1386 is available in the commercial and industrial temperature range and is supplied in 28 lead plastic DIP and 44 lead ceramic LCC packages. • Wide Analog Input Bandwidth (Min for Full Scale Input) . . . . . . . . . . . . . . . . . . 150MHz Ordering Information • Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . -5.2V PART NUMBER • Low Power Consumption (Typ) . . . . . . . . . . . . .580mW TEMP. RANGE (oC) PACKAGE PKG. NO. • Low Error Rate • Operable at 50% Clock Duty Cycle • Capable of Driving 50Ω Loads HI1386JCP -20 to 75 28 Ld PDIP E28.6A-S HI1386AIL -20 to 100 44 Ld CLCC J44.B • Direct Replacement for CXA1386 Applications • Video Digitizing • RGB Graphics Processing • HDTV (High Definition TV) • Radar Systems • Communication Systems • Direct RF Down-Conversion • Digital Oscilloscopes Pinouts (LSB) D0 4 D1 5 26 AVEE 25 AGND 24 VIN AVEE AVEE 3 2 1 44 43 42 41 40 NC 4 VRT 5 NC 6 AVEE 27 VRT LINV DVEE 2 DGND 3 NC 28 AVEE DVEE LINV 1 DGND1 HI1386 (CLCC) TOP VIEW DGND2 HI1386 (PDIP) TOP VIEW NC 7 39 NC (LSB) D0 8 38 NC D1 9 37 AGND D2 10 36 VIN D3 11 35 AGND D2 6 23 AGND D3 7 22 VRM D4 12 34 VRM D4 8 21 AGND D5 13 33 AGND D5 9 20 VIN D6 14 32 VIN D6 10 19 AGND CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 4-1148 AVEE AVEE NC VRB NC CLK CLK 15 CLK MINV 16 CLK MINV 14 29 NC 18 19 20 21 22 23 24 25 26 27 28 DVEE DVEE 13 30 NC NC 17 17 VRB NC DGND 12 31 AGND DGND2 16 18 AVEE DGND1 (MSB) D7 11 (MSB) D7 15 File Number 3583.4 HI1386 Functional Block Diagram MINV R1 COMPARATOR VRT R/2 R 1 R D7 (MSB) 2 R D6 63 D5 R 64 VIN R D4 65 OUTPUT D3 R 126 D2 R 127 R2 VRM ENCODE LOGIC R D1 128 R D0 (LSB) 129 R 191 R 192 VIN R 193 R 254 R 255 VRB CLK CLK R3 R/2 CLOCK DRIVER LINV 4-1149 HI1386 Pin Descriptions PIN NUMBER DIP LCC SYMBOL I/O STANDARD VOLTAGE LEVEL 19, 21, 23, 25 31, 33, 35, 37 AGND - 0V Analog GND. Used as GND for input buffers and latches of comparators. Isolated from DGND, DGND1, and DGND2. 18, 26, 28 27, 28, 40, 41, 44 AVEE - -5.2V Analog VEE -5.2V (Typ). Internally connected to DVEE (Resistance: 4Ω to 6Ω). Bypass with 0.1µF to AGND. 16 23 CLK I ECL EQUIVALENT CIRCUIT DESCRIPTION CLK Input. DGND, DGND1 15 22 CLK Input Complementary to CLK. When open pulled down to -1.3V. Device is operable without CLK input, but use of complementary inputs of CLK and CLK is recommended to obtain stable high speed operation. R R R CLK R CLK DVEE R R 3, 12 - DGND - 0V Digital GND (used for internal circuits and output transistors). - 5, 19 DGND1 - 0V Digital GND (used for internal circuits and output transistors). - 6, 16 DGND2 - 0V Digital GND (used for output buffers). 2, 13 4, 20 DVEE - -5.2V Digital VEE . Internally connected to AVEE (resistance: 4Ω to 6Ω). Bypass with 0.1µF to DGND 4 8 D0 O ECL DGND 5 9 D1 6 10 D2 7 11 D3 8 12 D4 9 13 D5 10 14 D6 11 15 D7 LSB of Data Outputs. External pull-down resistor is required. Data Outputs. External pull-down resistors are required. D1 DVEE 4-1150 MSB of Data Outputs. External pull-down resistor is required. HI1386 Pin Descriptions (Continued) PIN NUMBER DIP LCC SYMBOL I/O STANDARD VOLTAGE LEVEL 1 3 LINV I ECL EQUIVALENT CIRCUIT DESCRIPTION Input Pin for D0 (LSB) to D6 Output Polarity Inversion (see A/D Output Code Table). Pulled low when left open. DGND, DGND1 14 21 MINV I ECL Input Pin for D7 (MSB) Output Polarity Inversion (see A/D Output Code Table). Pulled low when left open. R R 20, 24 32, 36 VIN I LINV OR MINV R DVEE R -1.3V VRT to VRB AGND VIN Analog Input Pins. These two pins must be connected externally, since they are not internally connected. See Application Note for precautions. VIN AVEE 17 26 VRB I VRM I -2V VRT Reference Voltage (Bottom). Typically -2V. Bypass with a 0.1µF and 10µF to AGND. R1 R/2 22 34 VRB/2 R COMPARATOR 1 Reference Voltage Mid Point. Can be used as a pin for integral linearity compensation. R 27 42 VRT I 0V COMPARATOR 2 R VRM COMPARATOR 127 R2 R COMPARATOR 128 R COMPARATOR 129 R COMPARATOR 130 R COMPARATOR 255 VRB R3 4-1151 R/2 Reference Voltage (Top) Typically 0V. HI1386 Absolute Maximum Ratings TA = 25oC Thermal Information Supply Voltage (AVEE , DVEE) . . . . . . . . . . . . . . . . . . . -7V to +0.5V Analog Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V Reference Input Voltage VRT , VRB , VRM . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V |VRT -VRB | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V Digital Input Voltage CLK, CLK, MINV, LINV . . . . . . . . . . . . . . . . . . . . . . . -4V to +0.5V |CLK-CLK | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V VRM Pin Input Current (IVRM) . . . . . . . . . . . . . . . . . . -3mA to +3mA Digital Output Current (ID0 to ID7) . . . . . . . . . . . . . . . -30mA to 0mA Thermal Resistance (Typical, Note 1) θJAoC/W θJCoC/W PDIP Package . . . . . . . . . . . . . . . . . . . 58 N/A CLCC Package . . . . . . . . . . . . . . . . . . 45 11 Maximum Junction Temperature CLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range (TSTG) . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Conditions Temperature Ranges (Note 4) PDIP Package (TA) . . . . . . . . . . . . . . . . . . . . . . . . . -20oC to 75oC CLCC Package (TC) . . . . . . . . . . . . . . . . . . . . . . . -20oC to100oC Supply Voltage AVEE , DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5V to -4.95V AVEE - DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V AGND - DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V Reference Input Voltage VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.1V to 0.1V VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.2V to -1.8V Analog Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . VRB to VRT Pulse Width of Clock tPW1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6ns (Min) tPW0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6ns (Min) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER TA = 25oC, AVEE = DVEE = -5.2V, VRT = 0V, VRB = -2V (Note 1) TEST CONDITIONS MIN TYP MAX UNIT - 8 - Bits SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL fC = 75MHz - ±0.3 ±0.5 LSB Differential Linearity Error, DNL fC = 75MHz - ±0.3 ±0.5 LSB Signal to Noise and Distortion Ratio, SINAD Input = 1MHz, Full Scale fC = 75MHz RMS Signal = -----------------------------------------------------------------RMS Noise + Distor tion Input = 18.75MHz, Full Scale fC = 75MHz - 46 - dB - 40 - dB Error Rate Input = 18.749MHz, Full Scale Error > 16 LSB, fC = 75MHz - - 10-9 TPS (Note 2) Differential Gain Error, DG - 1.0 - % Differential Phase Error, DP NTSC 40 IRE Mod. Ramp, fC = 75 MSPS Maximum Conversion Rate, fC Error Rate of 10-9 TPS (Note 2) DYNAMIC CHARACTERISTICS - 0.5 - Degree 75 - - MSPS Aperture Jitter, tAJ - 10 - ps Sampling Delay, tDS - 3.0 - ns 150 - - MHz - 17 - pF - 390 - kΩ - - 200 µA 75 110 155 Ω ANALOG INPUT Input Bandwidth VIN = 2VP-P (-3dB) Analog Input Capacitance, CIN VIN = 1V + 0.07VRMS Analog Input Resistance, RIN Input Bias Current, IIN VIN = -1V REFERENCE INPUTS Reference Resistance, RREF 4-1152 HI1386 Electrical Specifications TA = 25oC, AVEE = DVEE = -5.2V, VRT = 0V, VRB = -2V (Note 1) (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Offset Voltage EOT VRT 8 18 32 mV EOB VRB 0 10 24 mV DIGITAL INPUTS Logic H Level, VIH -1.13 - - V Logic L Level, VIL - - -1.50 V Logic H Current, IIH -0.8V is Applied to Input 0 - 50 µA Logic L Current, IIL -1.6V is Applied to Input -50 - 50 µA - 7 - pF Input Capacitance DIGITAL OUTPUTS Logic H Level, VOH RL = 620Ω to DVEE -1.03 - - V Logic L Level, VOL RL = 620Ω to DVEE - - -1.62 V H Pulse Width of Clock, tPW1 6.6 - - ns L Pulse Width of Clock, tPW0 6.6 - - ns - 0.9 - ns TIMING CHARACTERISTICS Output Rise Time, tr RL = 620Ω to DVEE , 20% to 80% Output Fall Time, tf RL = 620Ω to DVEE , 20% to 80% Output Delay, tOD - 2.1 - ns 4.0 6.5 9.0 ns -150 -104 - mA - 580 - mW POWER SUPPLY CHARACTERISTICS Supply Current, IEE Power Consumption, PD Note 3 NOTES: 1. Electrical Specifications guaranteed within stated operating conditions. 2. TPS: Times Per Sample. 2 ( V RT- V RB ) 3. P D = I EE • V EE + ------------------------------------R REF 4. TA specified in still air and without heat sink. To extend temperature range, appropriate heat management techniques must be employed. Timing Diagram tDS ANALOG IN N+1 N N+2 tPW1 tPW0 CLK CLK DIGITAL OUT N-1 20% 80% tr tOD FIGURE 1. 4-1153 N 80% N+1 20% tf HI1386 A/D OUTPUT CODE TABLE MINV 1 LINV 1 VIN (NOTE 1) STEP D7 0V -1V 0 1 D0 1 0 D7 D0 D7 0 0 D0 D7 D0 000 • • • • • 00 100 • • • • • 00 011 • • • • • 11 111 • • • • • 11 0 000 • • • • • 00 100 • • • • • 00 011 • • • • • 11 111 • • • • • 11 1 000 • • • • • 01 100 • • • • • 01 011 • • • • • 10 111 • • • • • 10 • • • • • • • • • • • • 127 011 • • • • • 11 111 • • • • • 11 000 • • • • • 00 100 • • • • • 00 128 100 • • • • • 00 000 • • • • • 00 111 • • • • • 11 011 • • • • • 11 • • • • • • • • • • • • 111 • • • • • 10 011 • • • • • 10 100 • • • • • 01 000 • • • • • 01 254 255 -2V 111 • • • • • 11 011 • • • • • 11 100 • • • • • 00 000 • • • • • 00 111 • • • • • 11 011 • • • • • 11 100 • • • • • 00 000 • • • • • 00 NOTE: 5. VRT = 0V, VRB = -2V. Test Circuits SIGNAL SOURCE fCLK 4 VIN 8 CLK A ECL LATCH HI1386 B PULSE COUNTER COMPARATOR A>B CLK -1kHz ECL LATCH + 2VP-P SINEWAVE DATA 16 SIGNAL SOURCE fCLK/A fCLK FIGURE 2. MAXIMUM CONVERSION RATE TEST CIRCUIT +V S2 VIN AMP NTSC SIGNAL SOURCE DUT HI1386 CLK 8 ECL LATCH HI20201 - 10-BIT D/A + 8 S1 : A < B : ON S2 : A > B : ON S1 CLK -V A<B DELAY SG (CW) 50 VBB VECTOR SCOPE VIN DUT A>B COMPARATOR 8 A8 B8 A1 A0 B1 B0 8 BUFFER HI1386 DG/DP DVM “0” CLK (75MHz) FIGURE 3. DIFFERENTIAL GAIN AND PHASE ERROR TEST CIRCUIT CONTROLLER “1” 8 00000000 TO 11111110 FIGURE 4. INTEGRAL AND DIFFERENTIAL LINEARITY ERROR TEST CIRCUIT 4-1154 HI1386 Test Circuits (Continued) -1V A IIN -1V IIN A IEE 1 28 2 27 3 26 7 39 4 25 8 38 5 24 9 37 6 23 10 36 22 11 35 21 12 9 20 13 10 19 14 32 11 18 15 31 12 17 16 30 7 A -5.2V 6 HI1386JCP 8 -2V 2 1 44 43 42 41 40 34 HI1386AIL, CXA1386K 33 29 18 15 14 3 17 16 13 4 5 19 20 21 22 23 24 25 A IEE 26 27 28 -2V -5.2V FIGURE 5A. FIGURE 5B. FIGURE 5. ANALOG INPUT BIAS AND POWER SUPPLY CURRENT TEST CIRCUITS 0V -1V VIN -2V 37.5MHz AMP CLK OSC1 φ: VARIABLE VIN fR HI1386 CLK OSC2 37.5MHz 8 ∆υ ∆t LOGIC ANALYZER t VIN 1024 SAMPLES ECL BUFFER CLK 129 128 127 126 125 σ (LSB) APERTURE JITTER Aperture jitter is defined as follows: ∆υ 256 t AJ = σ ⁄ ------- = σ ⁄ ---------- × 2πf , 2 ∆t Where σ (unit: LSB) is the deviation of the output codes when the input frequency is exactly the same as the clock and is sampled at the largest slew rate point. FIGURE 6A. FIGURE 6B. APERTURE JITTER TEST METHOD FIGURE 6. SAMPLING DELAY AND APERTURE JITTER TEST CIRCUIT 4-1155 HI1386 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 4-1156 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029