HI1166 September 1998 8-Bit, 250 MSPS, Flash A/D Converter Features • Differential Linearity Error . . . . . . . . . . ±0.5 LSB or Less The HI1166 is an 8-bit, ultra high speed, flash Analog-toDigital converter IC capable of digitizing analog signals at a maximum rate of 250 MSPS. The digital I/O levels of the converter are compatible with ECL 100K/10KH/10K. • Integral Linearity Error . . . . . . . . . . . . . ±0.5 LSB or Less • Built-In Integral Linearity Compensation Circuit • Ultra High Speed Operation with Maximum Conversion Rate (Min) . . . . . . . . . . . . . . . . . . . 250 MSPS Applications • Spectrum Analyzers • Radar Systems • Direct RF Down-Conversion • Low Input Capacitance 18pF (Typ) • Video Digitizing • Communication Systems • Digital Oscilloscopes • Wide Analog Input Bandwidth (Min for Full Scale Input) . . . . . . . . . . . . . . . . . . . 250MHz • Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . . -5.2V Ordering Information PART NUMBER File Number 3579.4 TEMP. RANGE (oC) HI1166AIL -20 to 100 HI1166-EV 25 • Low Power Consumption . . . . . . . . . . . . . . . . . 1.4W (Typ) PACKAGE • Low Error Rate PKG. NO. 68 Ld CLCC • Capable of Driving 50Ω Loads J68.A • Evaluation Board Available Evaluation Board • Direct Replacement for Sony CXA1166K Pinout 9 8 7 6 5 4 3 2 AGND AVEE VRTS VRT NC AVEE D1 D1 D0 D0 OR OR LINV NC AVEE NC DVEE HI1166 (CLCC) TOP VIEW 1 68 67 66 65 64 63 62 61 NC 10 NC D2 D2 D3 D3 DGND2 DGND2 DGND1 D4 D4 D5 D5 NC NC NC NC 60 NC 11 59 NC 12 58 AVEE 13 57 NC 14 56 AGND 15 16 55 VIN1 54 VIN1 17 53 AGND 18 52 VRM 19 51 AGND 20 50 VIN2 21 49 VIN2 22 48 AGND 23 47 NC 24 46 NC 25 45 NC 44 NC 26 1 AGND NC AVEE AVEE VRBS VRB NC AVEE CLK D7 D7 MINV CLK D6 D6 NC DVEE 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 HI1166 Functional Block Diagram MINV 33 R1 COMPARATOR VRT 64 R/2 VRTS 65 R2 0 2 OR R 3 OR 1 R 31 D7 (MSB) 2 32 D7 R 29 D6 30 D6 63 21 D5 R VIN1 54 22 D5 64 55 R 19 D4 65 OUTPUT 20 D4 14 D3 R 15 D3 126 12 D2 R 13 D2 127 R3 VRM 52 ENCODE LOGIC R 6 D1 128 7 D1 R 4 D0 (LSB) 129 5 R 191 R 192 VIN2 49 R 50 193 R 254 R R4 VRBS 39 255 R/2 VRB 40 R5 CLK 35 CLOCK DRIVER CLK 34 1 LINV 2 D0 HI1166 Absolute Maximum Ratings TA = 25oC Thermal Information Supply Voltage (AVEE, DVEE) . . . . . . . . . . . . . . . . . . . . -7V to +0.5V Analog Input Voltage (VIN). . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V Reference Input Voltage VRT, VRB, VRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V |VRT -VRB | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V Digital Input Voltage MINV, LINV, CLK, CLK . . . . . . . . . . . . . . . . . . . . . . . . -4V to +0.5V |CLK-CLK| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V VRM Pin Input Current (IVRM) . . . . . . . . . . . . . . . . . . -3mA to +3mA Digital Output Current (ID0 to ID7, IOR, ID0 to ID7, IOR) . . . . . . . . . . . . . -30mA to 0mA Temperature Range, TA (Note 5) . . . . . . . . . . . . . . . -20oC to 100oC TC . . . . . . . . . . . . . . . . . . . . . -20oC to 125oC Thermal Resistance (Typical, Note 2) θJAoC/W θJCoC/W CLCC Package. . . . . . . . . . . . . . . . . . . 38 10 Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .2.1W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .175oC Maximum Storage Temperature Range (TSTG). . . . -65oC to 150oC Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . .300oC Operating Conditions (Note 1) Supply Voltage MIN AVEE, DVEE . . . . . . . . . . . . . . . . . . . . . . . -5.5V AVEE - DVEE . . . . . . . . . . . . . . . . . . . . . . -0.05V AGND - DGND . . . . . . . . . . . . . . . . . . . . . -0.05V TYP -5.2 0 0 MAX -4.95V 0.05V 0.05V Reference Input Voltage MIN TYP MAX VRT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.1V -2 0.1V VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.2V -2 -1.8V Analog Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . .VRB to VRT CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Electrical Specifications guaranteed within stated operating conditions. 2. θJA is measured with the component mounted on an evaluation PC board in free air. TA = 25oC, AVEE = DVEE = -5.2V, VRT, VRTS = 0V, VRB , VRBS = -2V (Note 1) Electrical Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT - 8 - Bits SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL fC = 250 MSPS - ±0.3 ±0.5 LSB Differential Linearity Error, DNL fC = 250 MSPS - ±0.3 ±0.5 LSB Input = 1kHz, Full Scale fC = 250MHz 44 46 - dB Input = 60kHz, Full Scale fC = 250MHz - 37 - dB Input = 50MHz, Full Scale Error > 16 LSB, fC = 250MHz - - 10-9 TPS (Note 3) Input = 62.499MHz, Full Scale Error > 16 LSB, fC = 250MHz - 10-8 10-6 TPS (Note 3) NTSC 40 IRE Mod. Ramp, fC = 250 MSPS - 1.0 - % - 0.5 - Degree DYNAMIC CHARACTERISTICS Signal to Noise Ratio, SINAD RMS Signal = -----------------------------------------------------------------RMS Noise + Distortion Error Rate Differential Gain Error, DG Differential Phase Error, DP Overrange Recovery Time Maximum Conversion Rate, fC Aperture Jitter, tAJ Sampling Delay, tDS - 1.0 - ns 250 - - MSPS - 9 - ps 0.4 1.4 2.4 ns ANALOG INPUT Analog Input Capacitance, CIN VIN - 1V + 0.07VRMS Analog Input Resistance, RIN - 18 - pF 50 120 - kΩ Input Bias Current, IIN VIN = -1V 20 - 450 µA Full Scale Input Bandwidth VIN = 2VP-P 200 250 - MHz 83 125 182 Ω REFERENCE INPUTS Reference Resistance, RREF 3 HI1166 TA = 25oC, AVEE = DVEE = -5.2V, VRT, VRTS = 0V, VRB , VRBS = -2V (Note 1) (Continued) Electrical Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.1 0.6 2.0 Ω R2 300 500 700 Ω R3 0.5 2.0 5.0 Ω R4 300 500 700 Ω R5 0.1 0.6 2.0 Ω Logic H Level, VIH -1.13 - - V Logic L Level, VIL - - -1.5 V Residual Resistance R1 Note 2 DIGITAL INPUTS Logic H Current, IIH Input Connected to GND Logic L Current, IIL Input Connected to -2V Input Capacitance 0 - 70 µA -50 - 50 µA - 4 - pF DIGITAL OUTPUTS Logic H Level, VOH RL = 50Ω -1.0 - - V Logic L Level, VOL RL = 50Ω - - -1.6 V 1.8 - - ns TIMING CHARACTERISTICS H Pulse Width of Clock, tPW1 L Pulse Width of Clock, tPW0 1.8 - - ns Output Rise Time, tr RL = 50Ω - 0.6 1.5 ns Output Fall Time, tf RL = 50Ω - 0.6 1.5 ns Output Delay, tOD RL = 50Ω 1.8 2.5 3.2 ns -360 -270 - mA - 1.4 1.9 W POWER SUPPLY CHARACTERISTICS Supply Current, IEE Power Consumption, PD Note 4 NOTES: 1. Electrical Specifications guaranteed within stated operating conditions. 2. See Functional Block Diagram. 3. TPS: Times Per Sample. 2 ( V RT – V RB ) 4. PD = I EEA • AV EE + I EED • DV EE + ------------------------------------R REF 5. TA is specified in still air and without heat sink. To extend temperature range, appropriate heat management techniques must be employed (See Figure 2). Timing Diagram tSD ANALOG IN N+1 N N+2 tPW1 tPW0 CLK CLK DIGITAL OUT N-1 tOD 80% tr FIGURE 1. 4 20% N 80% N+1 20% tf HI1166 Typical Performance Curves 25 INPUT CAPACITANCE (pF) THERMAL RESISTANCE θJA (oC/W) 50 SOCKET AMP: 173061-5 (WITHOUT HEAT SINK) 40 SOCKET AMP: 173257-3 (WITH HEAT SINK) 30 1.0 2.0 AIR FLOW (m/s) 10 -2.0 3.0 FIGURE 2. THERMAL RESISTANCE OF THE CONVERTER MOUNTED ON A BOARD -1.5 -1.0 INPUT VOLTAGE (V) -0.5 0 FIGURE 3. VIN PIN CAPACITANCE vs VOLTAGE CHARACTERISTICS 200 150 125 IIN (µA) ANALOG INPUT RESISTANCE (kΩ) 15 SOCKET: YAMAICHI ELECTRONICS CO., LTD IC61-0684-048 0 100 100 10 -2.0 -1.5 -1.0 INPUT VOLTAGE (V) -0.5 0 -2.0 0 -1.0 INPUT VOLTAGE (V) -0.5 0 -12 RESISTOR STRING CURRENT (mA) 200 150 100 50 0 -50 -1.5 FIGURE 5. VIN PIN INPUT CURRENT vs VOLTAGE CHARACTERISTICS FIGURE 4. VIN PIN INPUT RESISTANCE vs VOLTAGE CHARACTERISTICS INPUT CURRENT (µA) 20 0 50 100 CASE TEMPERATURE (oC) FIGURE 6. VIN PIN INPUT CURRENT vs TEMPERATURE CHARACTERISTICS 5 150 -14 -16 -18 -20 -22 -24 -50 0 50 100 CASE TEMPERATURE (oC) 150 FIGURE 7. RESISTOR STRING CURRENT vs TEMPERATURE CHARACTERISTICS HI1166 (Continued) -1.25 -0.7 -1.30 -0.8 VOH (V) CLK OPEN VOLTAGE (V) Typical Performance Curves -1.35 -1.40 -0.9 -1.0 -1.45 -1.1 -50 0 50 100 CASE TEMPERATURE (oC) 150 -50 FIGURE 8. CLK OPEN VOLTAGE vs TEMPERATURE CHARACTERISTICS 0 50 100 CASE TEMPERATURE (oC) 150 FIGURE 9. VOH vs TEMPERATURE CHARACTERISTICS -1.7 50 45 SINAD (dB) VOL (V) -1.8 -1.9 40 35 -2.0 30 -2.1 -50 25 0 50 100 CASE TEMPERATURE (oC) 150 FIGURE 10. VOL vs TEMPERATURE CHARACTERISTICS 1 FIGURE 11. SINAD vs INPUT FREQUENCY RESPONSE CHARACTERISTICS 300 CLOCK FREQUENCY = 250MHz -30 250 THIRD HARMONIC -40 CLK (MHz) HIGH FREQUENCY DISTORTION (dB) 10 100 INPUT FREQUENCY (MHz) -50 SECOND HARMONIC -60 -70 -80 0.1 200 150 1 10 100 INPUT FREQUENCY (MHz) 1000 FIGURE 12. HARMONIC DISTORTION vs INPUT FREQUENCY RESPONSE CHARACTERISTICS 6 ERROR RATE = 10-8 TPS INPUT FREQUENCY = CLOCK FREQUENCY/4 - 1kHz ERROR RATE > 16 LSB -25 25 75 125 AMBIENT TEMPERATURE (oC) FIGURE 13. MAXIMUM CONVERSION RATE vs TEMPERATURE CHARACTERISTICS HI1166 Typical Performance Curves (Continued) INPUT FREQUENCY = CLOCK FREQUENCY/4 - 1kHz ERROR RATE > 16 LSB INPUT = 125MHz, FULL SCALE CLK = 250MHz, ERROR RATE > 16 LSB ERROR RATE (TPS) ERROR RATE (TPS) 10-7 10-8 10-9 10-10 200 250 10-7 10-8 10-9 25 300 35 30 CLOCK FREQUENCY (MHz) FIGURE 14. ERROR RATE vs CONVERSION RATE 50 40 45 55 CLK DUTY CYCLE (%) 60 65 70 FIGURE 15. ERROR RATE vs CLOCK DUTY CYCLE SUPPLY CURRENT (mA) -200 -250 -300 -350 -50 0 50 100 150 CASE TEMPERATURE (oC) FIGURE 16. SUPPLY CURRENT vs TEMPERATURE CHARACTERISTICS Pin Descriptions PIN NUMBER SYMBOL I/O STANDARD VOLTAGE LEVEL 4, 5 D0, D0 O ECL EQUIVALENT CIRCUIT DESCRIPTION DGND2 16 6, 7 D1, D1 12, 13 D2, D2 14, 15 D3, D3 19, 20 D4, D4 21, 22 D5, D5 29, 30 D6, D6 31, 32 D7, D7 2, 3 OR, OR LSB and complementary LSB output. D1 to D6: Data Output. D1 to D6: Complementary Data Output. Di Di MSB Complementary MSB Data Output. 8 DVEE 7 28 Overrange and Complementary Overrange Output. HI1166 Pin Descriptions (Continued) PIN NUMBER SYMBOL I/O STANDARD VOLTAGE LEVEL 1 LINV I ECL 33 MINV I ECL EQUIVALENT CIRCUIT DESCRIPTION Polarity selection for LSBs (refer to the A/D Output Code Table.) Pulled low when left open. DGND1 18 R Polarity selection for MSB (refer to the A/D Output Code Table). Pulled low when left open. R R -1.3V LINV 1 OR MINV 33 R 8 DVEE 28 35 CLK I ECL 34 CLK I ECL CLK Input. DGND1 18 Complementary CLK Input. Pulled down to -1.3V when left open. R R R CLK R 35 34 CLK DVEE 8 R R 28 64 VRT I 0V VRT 65 VRTS O 0V VRTS VRM I Analog Reference Voltage (Top) (0V Typ). 64 52 39 40 VRBS VRB VRB/2 O R2 R1 Reference Voltage Sense (Top). R/2 Reference Voltage Mid Point. Can be used for linearity compensation. R Reference Voltage Sense (Bottom). 65 -2V I -2V Analog Reference Voltage (Bottom). VRM R3 52 R R VRBS R4 R/2 39 VRB 40 8 R5 TO COMPARATORS HI1166 Pin Descriptions (Continued) PIN NUMBER SYMBOL I/O STANDARD VOLTAGE LEVEL 49, 50 VIN2 I VRTS to VRBS 54, 55 EQUIVALENT CIRCUIT VIN2 VIN1 DESCRIPTION 43, 48, 51, 53, 56, 61 AGND 49 Analog Input. All of the pins must be wired externally. TO COMP. 128 TO 255 50 54 0 TO 127 55 VIN1 43, 48, 51, 53, 56, 61 AGND 0V 37, 38, 42, 58, 62, 66, 67 AVEE -5.2V 18 DGND1 0V 16, 17 DGND2 0V 8, 28 DVEE AGND DGND1 61 48 53 43 51 56 INTERNAL ANALOG CIRCUIT DGND2 18 16 17 Analog supply. Internally connected to DVEE (resistance: 4Ω to 6Ω). INTERNAL DIGITAL CIRCUIT Digital ground. Digital ground for output drive. 4Ω TO 6Ω -5.2V 42 37 58 62 38 66 AVEE 67 Analog ground. D1 D1 8 Digital supply. Internally connected to AVEE (resistance: 4Ω to 6Ω). 28 DVEE TABLE 1. A/D OUTPUT CODE VIN (NOTE 6) STEP OR 0 1 0 1 1 127 128 1 1 254 255 1 1 1 0V -1V -2V NOTE: MINV 1, LINV 1 D7 D0 000 • • • • • 00 000 • • • • • 00 000 • • • • • 01 • • • 011 • • • • • 11 100 • • • • • 00 • • • 111 • • • • • 10 111 • • • • • 11 111 • • • • • 11 OR 0 1 1 1 1 1 1 1 6. VRT = VRTS = 0V, VRM = -1V or open, VRB = VRBS = -2V. 9 0, 1 D7 D0 100 • • • • • 00 100 • • • • • 00 100 • • • • • 01 • • • 111 • • • • • 11 000 • • • • • 00 • • • 011 • • • • • 10 011 • • • • • 11 011 • • • • • 11 OR 0 1 1 1 1 1 1 1 1, 0 D7 D0 011 • • • • • 11 011 • • • • • 11 011 • • • • • 10 • • • 000 • • • • • 00 111 • • • • • 11 • • • 100 • • • • • 01 100 • • • • • 00 100 • • • • • 00 OR 0 1 1 1 1 1 1 1 0, 0 D0 D7 111 • • • • • 11 111 • • • • • 11 111 • • • • • 10 • • • 100 • • • • • 00 011 • • • • • 11 • • • 000 • • • • • 01 000 • • • • • 00 000 • • • • • 00 HI1166 Test Circuits and Waveforms FUNC. GENERATOR 100 VIN 1 2 AMP 2Ω 8 DUT HI1166 8 ECL LATCH 110 NTSC SIGNAL SOURCE HI20201 100 AMP fms 10-BIT D/A 0V 110 -2V CLK CLK 2 1 -4.5V DIVIDER SG (CW) VECTOR SCOPE OSCILLOSCOPE DG/DP MAXIMUM CONVERSION RATE SWITCH POSITION 1. MAXIMUM CONVERSION RATE 2. DG/DP 50 DUTY FIGURE 17. MAXIMUM CONVERSION RATE TEST CIRCUIT +V S2 - S1 : A < B : ON S2 : A > B : ON S1 + -V A<B A>B COMPARATOR VIN DUT HI1166 8 DVM “0” CLK (250MHz) A8 TO A1 A0 B8 TO B1 B0 CONTROLLER 8 BUFFER “1” 8 000 • • • 00 TO 111 • • • 10 FIGURE 18. INTEGRAL AND DIFFERENTIAL LINEARITY ERROR TEST CIRCUIT 10 HI1166 Test Circuits and Waveforms (Continued) IIN A -1V 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 HI1166 -2V 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A IEEA A IEED -5.2V -5.2V FIGURE 19. POWER SUPPLY AND ANALOG INPUT BIAS CURRENT TEST CIRCUIT 0V -1V VIN -2V CLK ∆υ ∆t t VIN 60MHz AMP 129 128 127 126 125 σ (LSB) OSC1 φ: VARIABLE CLK VIN fR HI1166 CLK OSC2 60MHz 8 LOGIC ANALYZER 1024 SAMPLES ECL BUFFER FIGURE 20A. APERTURE JITTER APERTURE JITTER IS DEFINED AS FOLLOWS: ∆υ 256 t AJ = σ ⁄ ------- = σ ⁄ ---------- × 2 π f 2 ∆t Where σ (unit: LSB) is the deviation of the output codes when the input frequency is exactly the same as the clock and is sampled at the largest slew rate point. FIGURE 20B. APERTURE JITTER TEST METHOD FIGURE 20. SAMPLING DELAY AND APERTURE JITTER TEST CIRCUIT 11 HI1166 Ceramic Leadless Chip Carrier Packages (CLCC) J68.A 0.010 S E H S 68 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE D INCHES D3 j x 45o E3 B E h x 45o 0.010 S E F S A MIN MAX MIN MAX NOTES A 0.067 0.087 1.70 2.20 6, 7 A1 0.058 0.072 1.47 1.83 - B - - - - - B1 0.033 0.039 0.85 0.99 2, 4 B3 0.006 0.022 0.15 0.56 - D 0.940 0.965 23.88 24.51 0.800 BSC 20.32 BSC - D2 0.400 BSC 10.16 BSC - D3 0.616 0.632 15.65 16.05 2 E 0.940 0.965 23.88 24.51 - E1 E3 PLANE 2 e e1 PLANE 1 -E- 0.007 M E F S H S B1 e L -H- j 0.800 BSC 20.32 BSC 0.400 BSC 0.616 0.632 10.16 BSC 15.65 0.050 BSC 0.015 - - 0.040 Ref - 16.05 1.27 BSC 0.38 2 - - 2 1.00 Ref 5 L 0.045 0.055 1.14 1.40 - L1 0.045 0.055 1.14 1.40 - L2 0.075 0.095 1.91 2.41 - L3 0.003 0.015 0.08 ND L3 - D1 E2 A1 MILLIMETERS SYMBOL 17 0.38 17 3 NE 17 17 3 N 68 68 3 Rev. 0 5/18/94 -FB3 E1 E2 L2 B2 L1 D2 e1 D1 NOTES: 1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol “N” is the maximum number of terminals. Symbols “ND” and “NE” are the number of terminals along the sides of length “D” and “E”, respectively. 4. The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer’s option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension “A” controls the overall package thickness. The maximum “A” dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per ANSI Y14.5M-1982. 9. Controlling dimension: INCH. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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