AK4688EN

[AKD4688-A]
AKD4688-A
Evaluation board Rev.0 for AK4688
GENERAL DESCRIPTION
AKD4688-A is an evaluation board for AK4688, which is a single chip 24bit CODEC with a 2ch ADC and
a 2ch DAC. It is possible to evaluate not only A/D and D/A of the AK4688, but also asynchronous
operation characteristics. Also, the board could be connected to a digital’s audio equipment easily with
S/PDIF connectors.
 Ordering guide
AKD4688-A ---
Evaluation board for AK4688
(Cable for connecting with printer port of IBM-AT compatible PC and control software
are packed with this. This control software does not operate on Windows NT.)
FUNCTION
 Compatible with 2 types of digital audio interface
- Optical (S/PDIF) input/output with DIT/DIR (AK4118A)
- 10pin headers for interfacing with external data source
 Separate power supply or regulator power supply
 10pin header for register control
VSS3
DVDD
LOUT ROUT
+5V
REG
AK4118A
(DIR)
Digital Input
PORT 6
10pin Header
AVDD2
AVSS2
AK4688
AK4687
PORT4
10pin Header
AK4118A
(DIT)
AVSS1
Digital Output
AVDD1
RIN3 LIN3 RIN2 LIN2 RIN1LIN1
Control Data
10pin Header
Figure 1. AKD4688 Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
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Board Outline Chart
 Outline Chart
J11
J10
AK4688
4688 Mode
AKD4688-A Rev.0 Evaluation Board
Asahi Kasei Microdevices Corporation
Figure 2. AKD4688-A Outline Chart
 Comment
(1) J1, J2, J3, J4, J5, J6, J7, J8, J10, J11 (RCA JACKS)
J1(white): Analog signal input RCA-Jacks. The signals are input to LIN1 pin.
J2 (red): Analog signal input RCA-Jacks. The signals are input to RIN1 pin.
J3,J4, J5,J6:Unused
J7 (white): An analog signal output RCA-Jack. The signal is output from LOUT pin.
J8 (red): An analog signal output RCA-Jack. The signal is output from ROUT pin.
J10 (black): A digital signal output RCA-Jack. The signal is output through U5 (AK4118A).
J11 (black): A digital signal input RCA-Jack. The signal is input through U6 (AK4118A).
(2) +5V, AVDD1, AVDD2, DVDD, D3.3V, AVSS1, AVSS2, VSS3, DGND
The power supply connectors which should be connected to power supplies.
Refer to the setup of power supply in Page3 for more details.
(3) PORT1 (10 pin header)
Control port. Connect the 10 wire flat cable bundled to this port.
(4) PORT4, PORT6 (10 pin header)
Audio Interfaces that clocks and data can be input and output with.
(5) PORT3, PORT5 (Optical Connecter)
PORT5 (Input): Optical digital signal is input to U6 (AK4118A).
PORT3 (Output): Optical digital signal is output from U5 (AK4118A).
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 Operation sequence
1) Set up the power supply lines.
1-1) When AVDD1, AVDD2, DVDD and D3.3V are supplied from the regulator. <Default>
Set up the jumper pins.
JP7
AVDD1_SEL
JP8
AVDD2_SEL
JP16
D3.3V_SEL
REG AVDD1 REG AVDD2 REG
D3.3V
Set up the power supply lines.
Name
Color
Voltage
Comments
+5V
Red
+5V
Power supply for the regulator.
AVDD1
Orange
Open
Power supply for AVDD1 of AK4688.
AVDD2
Orange
Open
Power supply for AVDD2 of AK4688.
DVDD
Orange
Open
Power supply for DVDD of AK4688.
D3.3V
Orange
Open
Power supply for logic circuit.
AVSS1
Black
0V
Analog ground for ADC of AK4688
AVSS2
Black
0V
Analog ground for DAC of AK4688.
VSS3
Black
0V
Digital ground of AK4688.
DGND
Black
0V
Logic circuit ground.
Table 1 Setup of power supply
1-2) When AVDD1, AVDD2, DVDD, and D3.3V are supplied from the power supply connectors.
Set up the jumper pins.
JP7
AVDD1_SEL
JP8
AVDD2_SEL
JP16
D3.3V_SEL
REG AVDD1 REG AVDD2 REG
D3.3V
Set up the power supply lines.
Name
Color
Voltage
Comments
+5V
Red
Open
The regulator is not used.
AVDD1
Orange
3.0V~3.6V (typ3.3V)
Power supply for AVDD1 of AK4688.
AVDD2
Orange
3.0V~3.6V (typ3.3V)
Power supply for AVDD2 of AK4688.
DVDD
Orange
3.0V~3.6V (typ3.3V)
Power supply for DVDD of AK4688.
D3.3V
Orange
3.0V~3.6V (typ3.3V)
Power supply for logic circuit.
AVSS1
Black
3.0V~3.6V (typ3.3V)
Analog ground for ADC of AK4688
AVSS2
Black
0V
Analog ground for DAC of AK4688.
VSS3
Black
0V
Digital ground of AK4688.
DGND
Black
0V
Logic circuit ground.
Table 2 Setup of power supply
* Each supply line should be distributed from the power supply unit.
AVDD1 and AVDD2 should be supplied as the same voltage level.
The difference of voltage level between AVDD1, AVDD2 and DVDD should be under 0.3V.
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2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.)
3) Power on.
AK4688 and AK4118A should be reset once bringing SW1, SW2, SW3, SW5 “L” upon power-up.
 Evaluation mode
In case of AK4688 evaluation by using AK4118A, it is necessary to correspond to audio interface format for
AK4688 and AK4118A. About audio interface format of AK4688, refer to the datasheet of AK4688. About audio
interface format of AK4118A, refer to the datasheet of AK4118A.
Applicable Evaluation Mode
(1) Evaluation of A/D and D/A by using DIR/DIT.
(2) All interface signals are fed externally.
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(1) Evaluation of A/D and D/A by using DIR/DIT
a) Set up of A/D
J10 TX (RCA-Jack) or PORT3 (Optical connector) is used.
Nothing should be connected to PORT4.
JP5
MCLK1_SEL
JP6
BICK1_SEL
JP7
LRCK1_SEL
JP8
SDTO
MCLK2 MCLK1 BICK2 BICK1 LRCK2 LRCK1
b) Set up of D/A
J11 RX (RCA-Jack) or PORT5 (Optical connector) is used.
Nothing should be connected to PORT6.
JP12
MCLK2
JP14
LRCK2
JP13
BICK2
JP15
SDTI
(2) All interface signals are fed externally.
a) Set up A/D
PORT4 is used.
Nothing should be connected to J10 TX (RCA-Jack) or PORT3 (Optical connector).
JP5
MCLK1_SEL
JP6
BICK1_SEL
JP7
LRCK1_SEL
JP8
SDTO
MCLK2 MCLK1 BICK2 BICK1 LRCK2 LRCK1
b)
Set up of D/A
PORT6 is used.
Nothing should be connected to J11 RX (RCA-Jack) or PORT5 (Optical connector).
JP12
MCLK2
JP14
LRCK2
JP13
BICK2
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SDTI
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 DIP Switch set up
[SW4] (4688 Mode): Mode settings of AK4688
No.
Name
OFF (“L”)
ON (“H”)
1
I2C
H/W Control
I2C Control
2
AIN1
Analog Input Selector Control (I2C = “L” )
(Refer to Table 7)
3
AIN0
4
MSN
ADC Slave Mode
ADC Master Mode
CAD Address pin Control (I2C = “H” )
5
CAD0/CKS
ADC Master Clock Speed Control (I2C = “L” )
6
TEST1
For AK4688’s TEST MODE (Fixed to “L”)
7
TEST2
For AK4688’s TEST MODE (Fixed to “L” )
Table 3. Mode settings of AK4688
X
AK4688
Register Settings
L
L
L
AK4118A (U5)
SW6 Settings
Audio I/F Format
DIF1
DIF0
L
L
24bit, Left justified
L
H
24bit, I 2 S
H
L
24bit, Left justified
H
H
24bit, I 2 S
Table 4. ADC Audio I/F Format Settings
MSN pin
DIF1 bit
L
L
H
H
0
1
0
1
AK4688
Register Settings
DIF21
DIF20
bit
bit
Default
L
L
L
L
AK4118A (U6)
SW7 Settings
DIF2
DIF1
DIF0
P
P
P
P
<Default>
Audio I/F Format
0
0
L
L
L
16bit, Right justified
0
1
1
1
0
1
L
H
H
H
L
L
H
L
H
24bit, Right justified
24bit, Left justified
24bit, I2S
<Default>
Table 5. DAC Audio I/F Format Settings
No.
0
1
2
3
MCKO1
X’tal
OCKS0
fs (max)
L
256fs
256fs
96kHz
H
256fs
256fs
96kHz
L
512fs
512fs
48kHz
H
128fs
128fs
192kHz
Table 6. AK4118A Master Clock Speed Control
OCKS1
L
L
H
H
AIN1 pin
L
L
H
H
AIN0 pin
L
H
L
H
Input Selector
LIN1 / RIN1
Reserved
Reserved
Reserved
<Default>
Table 7. ADC Input Selector Control (H/W Control Mode)
CKS pin
L
H
Master Clock Speed
256fs
768fs
<Default>
Table 8. ADC Master Clock Speed Control (Master Mode, H/W Control Mode)
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 Other jumper pins set up
1. JP1 (GND)
OPEN
SHORT
: Analog ground and digital ground are separated.
: Analog ground and digital ground are shorted. <Default>
2. JP1 (SCL/AIN0)
SCL
AIN0
: Select I2C control mode.
: Select H/W control mode. < Default >
3. JP2 (SDA/AIN1)
SDA
AIN1
: Select I2C control mode.
: Select H/W control mode. < Default >
4. JP9 (TX)
BNC
OPT
: Digital signals are output via the BNC connector. < Default >
: Digital signals are output via the optical connector.
5. JP10 (RX)
BNC
OPT
: Digital signals are output via the BNC connector. < Default >
: Digital signals are output via the optical connector.
 The function of the toggle SW
[SW1] (4688 PDN1) : Power down control for ADC of AK4688. Keep “H” during normal operation.
AK4688 should be reset once bringing SW1 “L” upon power-up.
[SW2] (4688 PDN2) : Power down control for DAC of AK4688. Keep “H” during normal operation.
AK4688 should be reset once bringing SW1 “L” upon power-up.
[SW3] (DIT PDN)
: Power down control of U5 (AK4118A). Keep “H” during normal operation.
Keep “L” when AK4118A is not used.
[SW5] (DIR PDN)
: Power down control of U6 (AK4118A). Keep “H” during normal operation.
Keep “L” when AK4118A is not used.
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 Serial Control
The AK4688 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT1
(CTRL) with PC by 10 wire flat cable packed with the AKD4688-A
PORT1
CTRL
10 wire
flat Cable
10
PC
Connect
Red
10pin Connector
9
SCL
SDA
SDA(ACK)
AKD4687-A
2 ▲
10pin Header
Figure 3. Connect of 10 wire flat cable
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 Analog Input/Output Circuits
(1) Input Circuits
J1
LIN1
J2
2
3
1
LIN1
RIN1
2
3
1
RIN1
MR-552LS
MR-552LS
AVSS1
AVSS1
Figure 4. Analog Input Circuit
(2) Output Circuits
R19
J7
470
2
3
1
LOUT
R21
(OPEN)
C11
(OPEN)
AVSS2
AVSS2
C12
2.2n
MR-552LS
AVSS2
AVSS2
R20
J8
470
C13
(OPEN)
AVSS2 AVSS2
ROUT
2
3
1
ROUT
R22
(OPEN)
LOUT
C14
2.2n
MR-552LS
AVSS2
AVSS2
Figure 5. Analog Output Circuit
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Control Soft Manual
■ Evaluation Board and Control Soft Settings
1. Set an evaluation board properly.
2. Connect the evaluation board to an IBM PC/AT compatible PC by a 10 wire flat cable. Be care of the direction of the
10pin header. Before running this control soft on Windows 2000/XP, the driver included in the CD must be installed.
Refer to the “Driver Control Install Manual for AKM Device Control Software” for installation of the driver. When
running this control soft on Windows 95/98/ME or via an AKDUSBIF-B interface board, driver installing is not
necessary.
3. Continue to evaluate by following steps.
■ Operation Screen
1. Start up the control program, and the operation screen is shown below.
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■ Operation Overview
Register map and testing tool can be controlled by this control soft. These controls are selected by upper tabs.
Buttons which are frequently used such as register initializing button “Write Default”, are located outside of the switching
tab window. Refer to the “■ Dialog Boxes” for details of each dialog box setting.
1. [Port Reset]: For when connecting to USB I/F board (AKDUSBIF-A)
Click this button after the control soft starts up when connecting USB I/F board (AKDUSBIF-A).
2. [Write Default]: Register Initializing
When the device is reset by a hardware reset, use this button to initialize the registers.
3. [All Write]: Executing write commands for all registers displayed.
4. [All Read]: Executing read commands for all registers displayed.
5. [Save]: Saving current register settings to a file.
6. [Load]: Executing data write from a saved file.
7. [All Reg Write]: “All Reg Write” dialog box is popped up.
8. [Data R/W]: “Data R/W” dialog box is popped up.
9. [Sequence]: “Sequence” dialog box is popped up.
10.
[Sequence(File)]: “Sequence(File)” dialog box is popped up.
11.
[Read]: Reading current register settings and display on to the Register area (on the right of the main window).
This is different from [All Read] button, it does not reflect to a register map, only displaying hexadecimal.
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■ Tab Functions
1. [REG 0H～5H]: Register Map
This tab is for register writing and reading.
Each bit on the register map is a push-button switch.
Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red).
Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray)
The registers which is not defined in the datasheet are indicated as “---”.
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[Write]: Data Writing Dialog
It is for when changing two or more bits on the same address at the same time.
Click [Write] button located on the right of the each corresponded address for a pop-up dialog box.
When checking the checkbox, the register will be “H” or “1”, when not checking the register will be “L” or ”0”.
Click [OK] to write setting value to the registers, or click [Cancel] to cancel this setting.
[Read]: Data Read
Click [Read] button located on the right of the each corresponded address to execute register reading.
After register reading, the display will be updated regarding to the register status.
Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red).
Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray)
Please be aware that button statuses will be changed by Read command.
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2. [Tool]: Testing Tools
This tab screen is for evaluation testing tool.
Click buttons for each testing tool.
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■ Dialog Boxes
1. [All Req Write]: All Req Write dialog box
Click [All Reg Write] button in the main window to open register setting files.
Register setting files saved by [SAVE] button can be applied.
[Open (left)]: Selecting a register setting file (*.akr).
[Write]: Executing register writing.
[Write All]: Executing all register writings.
Writings are executed in descending order.
[Help]: Help window is popped up.
[Save]: Saving the register setting file assignment. The file name is “*.mar”.
[Open (right)]: Opening a saved register setting file assignment “*. mar”.
[Close]: Closing the dialog box and finish the process.
*Operating Suggestions
(1) Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mar” should be stored in the
same folder.
(2) When register settings are changed by [Save] button in the main window, re-read the file to reflect new register settings.
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2. [Data R/W]: Data R/W Dialog Box
Click the [Data R/W] button in the main window for data read/write dialog box.
Data write is available to specified address.
Address Box: Input data address in hexadecimal numbers for data writing.
Data Box: Input data in hexadecimal numbers.
Mask Box: Input mask data in hexadecimal numbers.
This is “AND” processed input data.
[Write]: Writing to the address specified by “Address” box.
[Read]: Reading from the address specified by “Address” box.
The result will be shown in the Read Data Box in hexadecimal numbers.
[Close]: Closing the dialog box and finish the process.
Data writing can be cancelled by this button instead of [Write] button.
*The register map will be updated after executing [Write] or [Read] commands.
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3. [Sequence]: Sequence Dialog Box
Click [Sequence] button to open register sequence setting dialog box.
Register sequence can be set in this dialog box.
Sequence Setting
Set register sequence by following process bellow.
(1)Select a command
Use [Select] pull-down box to choose commands.
Corresponding boxes will be valid.
< Select Pull-down menu >
· No_use: Not using this address
· Register: Register writing
· Reg(Mask): Register writing (Masked)
· Interval: Taking an interval
· Stop: Pausing the sequence
· End: Finishing the sequence
(1) Input sequence
[Address]: Data address
[Data]: Writing data
[Mask]: Mask
[Data] box data is ANDed with [Mask] box data. This is the actual writing data.
When Mask = 0x00, current setting is hold.
When Mask = 0xFF, the 8bit data which is set in the [Data] box is written.
When Mask =0x0F, lower 4bit data which is set in the [Data] box is written.
Upper 4bit is hold to current setting.
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[ Interval ]: Interval time
Valid boxes for each process command are shown bellow.
· No_use: None
· Register: [Address], [Data], [Interval]
· Reg(Mask): [Address], [Data], [Mask], [Interval]
· Interval: [Interval]
· Stop: None
· End: None
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Control Buttons
The function of Control Button is shown bellow.
[Start]: Executing the sequence
[Help]: Opening a help window
[Save]: Saving sequence settings as a file. The file name is “*.aks”.
[Open]: Opening a sequence setting file “*.aks”.
[Close]: Closing the dialog box and finish the process.
Stop of the sequence
When “Stop” is selected in the sequence, processing is paused and it starts again when [Start] button is clicked.
Restarting step number is shown in the “Start Step” box. When finishing the process until the end of sequence, “Start
Step” will return to “1”.
The sequence can be started from any step by writing the step number to the “Start Step” box.
Write “1” to the “Start Step” box and click [Start] button, when restarting the process from the beginning.
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4. [Sequence(File)]: Sequence Setting File Dialog Box
Click [Sequence(File)] button to open sequence setting file dialog box.
Those files saved in the “Sequence setting dialog” can be applied in this dialog.
[Open (left)]: Opening a sequence setting file (*.aks).
[Start]: Executing the sequence setting.
[Start All]: Executing all sequence settings.
Sequences are executed in descending order.
[Help]: Pop up the help window.
[Save]: Saving sequence setting file assignment. The file name is “*.mas”.
[Open(right)]: Opening a saved sequence setting file assignment “*. mas”.
[Close]: Closing the dialog box and finish the process.
*Operating Suggestions
(1) Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mas” should be stored
in the same folder.
(2) When “Stop” is selected in the sequence the process will be paused and a pop-up message will appear. Click “OK”
to continue the process.
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MEASUREMENT RESULTS
1. ADC part
[Measurement condition]
 Measurement unit
 MCLK
 BICK
 fs
 BW
 Bit
 Power Supply
 Temperature
 Rf
 Ri
 Input Voltage
: Audio Precision SYS-2722
: 256fs
: 64fs
: 48kHz
: 20Hz20kHz (fs=48kHz)
: 24bit
: AVDD1=AVDD2=DVDD=3.3V
: Room
: 39kΩ
: 47kΩ
: 2.34Vrms
Parameter
Input signal
Measurement filter
S/(N+D)
1kHz, -1dBFS
DR
1kHz, -60dBFS
S/N
No signal
20kHz LPF
20kHz LPF,
A-weighted
20kHz LPF,
A-weighted
Results [dB]
Lch
Rch
85.1
84.0
98.2
99.2
98.3
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2. DAC part
[Measurement condition]
 Measurement unit
 MCLK
 BICK
 fs
 BW
 Resolution
 Power Supply
 Temperature
: Audio Precision SYS-2722
: 512fs (fs=48kHz), 256fs (fs=96kHz), 128fs (fs=192kHz)
: 64fs
: 48kHz, 96kHz, 192kHz
: 20Hz20kHz (fs=48kHz), 20Hz40kHz (fs=96kHz), 20Hz40kHz (fs=192kHz)
: 24bit
: AVDD1=AVDD2=DVDD=3.3V
: Room
fs=48kHz
Parameter
Input signal
Measurement filter
S/(N+D)
1kHz, 0dB
20kHz SPCL
DR
1kHz, -60dB
S/N
“0” data
20kHz SPCL,
A-weighted
20kHz SPCL,
A-weighted
Results [dB]
Lch
Rch
95.4
94.8
105.5
105.5
105.8
105.8
fs=96kHz
Parameter
Input signal
Measurement filter
S/(N+D)
1kHz, 0dB
DR
1kHz, -60dB
S/N
“0” data
Results [dB]
Lch
Rch
40kHz SPCL
94.4
94.0
40kHz SPCL,
A-weighted
40kHz SPCL,
A-weighted
105.5
105.6
105.7
105.8
fs=192kHz
Results [dB]
Parameter
Input signal
Measurement filter
Lch
Rch
S/(N+D)
1kHz, 0dB
40kHz SPCL
94.4
93.9
DR
1kHz, -60dB
105.6
105.6
S/N
“0” data
40kHz SPCL,
A-weighted
40kHz SPCL,
A-weighted
105.6
105.6
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1. ADC部
+0
-10
-20
-30
-40
-50
-60
d
B
F
S
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 6. FFT (Input Frequency =1kHz, Input Level=-1dBFS)
+0
-10
-20
-30
-40
-50
-60
d
B
F
S
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
Hz
Figure 7. FFT(Input Frequency =1kHz, Input Level=-60dBFS)
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+0
-10
-20
-30
-40
-50
-60
d
B
F
S
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 8. FFT(noise floor)
-60
-65
-70
-75
-80
-85
-90
d
B
F
S
-95
-100
-105
-110
-115
-120
-125
-130
-135
-140
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 9. THD + N vs Input Level (Input Frequency =1kHz)
<KM109900>
2011/12
- 24 -
[AKD4688-A]
-60
-65
-70
-75
-80
-85
-90
d
B
F
S
-95
-100
-105
-110
-115
-120
-125
-130
-135
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 10. THD + N vs Input Frequency (Input Level=-1.0dBFS)
+0
T
TT
TT
-10
-20
-30
-40
-50
-60
d
B
F
S
-70
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 11. Linearity (Input Frequency =1kHz)
<KM109900>
2011/12
- 25 -
[AKD4688-A]
-0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
d
B
F
S
-0.9
-1
-1.1
-1.2
-1.3
-1.4
-1.5
-1.6
-1.7
-1.8
-1.9
-2
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 12. Frequency Response (Input Level=-1.0dBFS)
-60
TT
T
T
-65
-70
-75
-80
-85
-90
-95
d
B
-100
-105
-110
-115
-120
-125
-130
-135
-140
20
50
100
200
500
1k
2k
5k
Hz
Figure 13. Crosstalk (Input Level=-1.0dBFS)
<KM109900>
2011/12
- 26 -
[AKD4688-A]
2-1. DAC部(fs=48kHz)
+0
-10
-20
-30
-40
-50
d
B
r
-60
A
-80
-70
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 14. FFT(Input Frequency =1kHz, Input Level=0dBFS)
+0
-10
-20
-30
-40
-50
d
B
r
-60
A
-80
-70
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
Hz
Figure 15. FFT(Input Frequency =1kHz, Input Level=-60dBFS)
<KM109900>
2011/12
- 27 -
[AKD4688-A]
+0
-10
-20
-30
-40
-50
d
B
r
-60
A
-80
-70
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 16. FFT(noise floor)
+0
-10
-20
-30
-40
-50
d
B
r
-60
A
-80
-70
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
50k
100k
Hz
Figure 17. FFT(out-of-band noise)
<KM109900>
2011/12
- 28 -
[AKD4688-A]
-60
-65
-70
-75
-80
-85
d
B
r
-90
A
-95
-100
-105
-110
-115
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 18. THD+N vs Input Level (Input Frequency =1kHz)
-60
-65
-70
-75
-80
-85
d
B
r
-90
A
-95
-100
-105
-110
-115
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 19. THD+N vs Input Frequency (Input Level=0dBFS)
<KM109900>
2011/12
- 29 -
[AKD4688-A]
+0
-10
-20
-30
-40
-50
d
B
r
-60
A
-80
-70
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 20. Linearity (Input Frequency =1kHz)
+1
+0.9
+0.8
+0.7
+0.6
+0.5
+0.4
+0.3
+0.2
d
B
r
A
+0.1
+0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 21. Frequency Response (Input Level=0dBFS, including external RC Filter)
<KM109900>
2011/12
- 30 -
[AKD4688-A]
-60
-65
-70
-75
-80
-85
-90
-95
d
B
-100
-105
-110
-115
-120
-125
-130
-135
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 22. Cross-talk (Input Level=0dBFS)
<KM109900>
2011/12
- 31 -
[AKD4688-A]
2-2. DAC部(fs=96kHz)
+0
-10
-20
-30
-40
-50
d
B
r
-60
A
-80
-70
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
40k
10k
20k
40k
Hz
Figure 23. FFT(Input Frequency =1kHz, Input Level=0dBFS)
+0
-10
-20
-30
-40
-50
d
B
r
-60
A
-80
-70
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
Hz
Figure 24. FFT(Input Frequency =1kHz, Input Level=-60dBFS)
<KM109900>
2011/12
- 32 -
[AKD4688-A]
+0
-10
-20
-30
-40
-50
d
B
r
-60
A
-80
-70
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 25. FFT(noise floor)
+0
-10
-20
-30
-40
-50
d
B
r
-60
A
-80
-70
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
50k
100k
Hz
Figure 26. FFT (Out of band Noise)
<KM109900>
2011/12
- 33 -
[AKD4688-A]
-60
-65
-70
-75
-80
-85
d
B
r
-90
A
-95
-100
-105
-110
-115
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 27. THD+N vs Input Level (Input Frequency =1kHz)
-60
-65
-70
-75
-80
-85
d
B
r
-90
A
-95
-100
-105
-110
-115
-120
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 28. THD+N vs fin (Input Level=0dBFS)
<KM109900>
2011/12
- 34 -
[AKD4688-A]
+0
-10
-20
-30
-40
-50
d
B
r
-60
A
-80
-70
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 29. Linearity (Input Frequency =1kHz)
+1
+0.9
+0.8
+0.7
+0.6
+0.5
+0.4
+0.3
+0.2
d
B
r
A
+0.1
+0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 30. Frequency Response (Input Level=0dBFS, including external RC Filter)
<KM109900>
2011/12
- 35 -
[AKD4688-A]
-60
-65
-70
-75
-80
-85
-90
-95
d
B
-100
-105
-110
-115
-120
-125
-130
-135
-140
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 31. Cross-talk (Input Level=0dBFS)
<KM109900>
2011/12
- 36 -
[AKD4688-A]
2-3. DAC部 (fs=192kHz)
+0
-10
-20
-30
-40
-50
d
B
r
-60
A
-80
-70
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
50k 80k
20k
50k 80k
Hz
Figure 32. FFT(Input Frequency =1kHz, Input Level=0dBFS)
+0
-10
-20
-30
-40
-50
d
B
r
-60
A
-80
-70
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
Hz
Figure 33. FFT(Input Frequency =1kHz, Input Level=-60dBFS)
<KM109900>
2011/12
- 37 -
[AKD4688-A]
+0
-10
-20
-30
-40
-50
d
B
r
-60
A
-80
-70
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
50k 80k
Hz
Figure 34. FFT(noise floor)
+0
-10
-20
-30
-40
-50
d
B
r
-60
A
-80
-70
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
50k
100k
Hz
Figure 35. FFT (Out of band Noise)
<KM109900>
2011/12
- 38 -
[AKD4688-A]
-60
-65
-70
-75
-80
-85
d
B
r
-90
A
-95
-100
-105
-110
-115
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 36. THD+N vs Input Level (Input Frequency =1kHz)
-60
-65
-70
-75
-80
-85
d
B
r
-90
A
-95
-100
-105
-110
-115
-120
20
50
100
200
500
1k
2k
5k
10k
20k
50k 80k
Hz
Figure 37. THD+N vs Input Frequency (Input Level=0dBFS)
<KM109900>
2011/12
- 39 -
[AKD4688-A]
+0
-10
-20
-30
-40
-50
d
B
r
-60
A
-80
-70
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 38. Linearity ( Input Frequency =1kHz)
+2
+1.8
+1.6
+1.4
+1.2
+1
+0.8
+0.6
+0.4
d
B
r
A
+0.2
+0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
20
50
100
200
500
1k
2k
5k
10k
20k
50k 80k
Hz
Figure 39. Frequency Response (Input Level=0dBFS, including external RC Filter)
<KM109900>
2011/12
- 40 -
[AKD4688-A]
-60
-65
-70
-75
-80
-85
-90
-95
d
B
-100
-105
-110
-115
-120
-125
-130
-135
-140
20
50
100
200
500
1k
2k
5k
10k
20k
50k 80k
Hz
Figure 40. Cross-talk (Input Level=0dBFS)
<KM109900>
2011/12
- 41 -
[AKD4688-A]
REVISION HISTORY
Date
(yy/mm/dd)
2011/12/12
Manual
Board
Reason
Revision Revision
KM109900
0
First Edition
Page
Contents
IMPORTANT NOTICE
 These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
 Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
 Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
 AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
 It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
<KM109900>
2011/12
- 42 -
5
4
3
LOUT
ROUT
VSS3
2
DVDD
TEST2
1
TEST1
CN101
CL102
CL101
12
11
10
9
8
7
6
5
4
3
2
1
48pin_1
1
D
1
2
2
D
Cut Land open
Cut Land short
VSS3
CVSS
R101
R102
0
0
AVSS2
CVSS
VSS3
C101
+
CN102
C104
1u
10u
1u
0.1u
VSS2
C
19
3
CAD0/CKS
10
R104
SDTI
11
CAD0
12
TEST1
13
TEST2
14
1
DVDD
15
16
DVSS
2
CP
17
CN
CVEE
CVSS
18
1
AVDD2
CN103
C102
+
+
C103
SDTI
2
51
R103
ROUT
LRCK2
9
LRCK2
3
C
51
R105
VSS5
20
4
LOUT
BICK2
8
VSS4
VSS1
51
R106
21
5
C107
+1u
22
AVSS1
+
MCLK2
U101
AVDD2
C106
23
0.1u
10u
7
VREF2
7
MCLK2
5
51
6
C105
AVDD1
BICK2
4
AVSS2
PDN2
AVSS2
PDN1
6
PDN2
6
5
PDN1
7
R107
24
8
C108
C109
MCLK1
4
MCLK1
8
51
R108
+
10u
9
AK4688
AVSS1
25
0.1u
AVDD1
BICK1
3
BICK1
9
51
R109
26
10
B
RI
LRCK1
2
LRCK1
10
R110
B
51
R111
39k
27
11
RO
SDTO
1
SDTO
11
MSN
R112
48pin_2
MSN
12
36
SCL
SCL
SDA
34
33
I2C
LIN1
32
31
NC
RIN1
30
29
28
12
LI
LO
51
48pin_3
4
NC
RIN1
LIN1
NC
1
5
LIN2
2
6
47k
7
R114
47k
8
LIN3
9
11
RIN3
10
12
CN104
R113
3
AVSS1
39k
48pin_4
A
A
NC
RIN2
I2C
SDA/AIN1
SCL/AIN0
Title
Size
A3
- 43 5
4
3
Date:
2
AKD4688-A-36QFN-SUB
Document Number
Rev
0
AK4688 Plastic
Thursday, November 24, 2011
Sheet
1
1
of
1
5
4
3
J1
LIN1
MR-552LS
D
AVSS1
AVSS1
J3
LIN2
J4
2
3
1
LIN2
RIN1
2
3
1
RIN1
MR-552LS
D
1
J2
2
3
1
LIN1
2
RIN2
2
3
1
RIN2
MR-552LS
MR-552LS
AVSS1
AVSS1
C
C
J5
LIN3
J6
2
3
1
LIN3
MR-552LS
MR-552LS
AVSS1
AVSS1
R19
B
R20
J7
470
LOUT
R21
(OPEN)
AVSS2
RIN3
2
3
1
RIN3
C11
C12
2.2n
(OPEN)
2
3
1
ROUT
R22
(OPEN)
MR-552LS
AVSS2
AVSS2
J8
470
LOUT
AVSS2
C13
(OPEN)
AVSS2 AVSS2
C14
2.2n
ROUT
B
2
3
1
MR-552LS
AVSS2
AVSS2
A
A
Title
- 44 5
4
3
Size
A4
Date:
2
AKD4688-A
Document Number
Rev
0
Analog Input / Output
Tuesday, December 13, 2011
Sheet
2
1
of
6
5
4
3
2
1
2
D3.3V
R23
1
D1
HSU119
10k
1
3
5
9
11
13
14
7
D
1
H
3
L
C15
0.1u
D3.3V
1A
2A
3A
4A
5A
6A
VCC
GND
2
SW1
ATE1D-2M3
4687 PDN1
U2
1Y
2Y
3Y
4Y
5Y
6Y
2
4
6
8
10
12
R24
0
R25
0
PDN1
74HC14
C16
0.1u
D3.3V
DGND
D3.3V
D3.3V
2
DGND
1
R26
R27
R28
R29
10k
10k
10k
10k
JP1
PORT1
10
8
6
4
2
R30
D2
HSU119
D
PDN2
10k
9
7
5
3
1
U3
SCL
SDA
SDA(ACK)
R31
R34
R32
1
3
5
9
11
13
470
470
0
CTRL
1
H
3
L
C17
0.1u
C
D3.3V
14
C18
0.1u
7
1Y
2Y
3Y
4Y
5Y
6Y
2
4
6
8
10
12
R35
51
SCL/AIN0
SCL/AIN0
51
JP2
SDA/AIN1
Vcc
AIN1
SDA/AIN1
GND
C
2
SW2
ATE1D-2M3
4687 PDN2
DGND
1A
2A
3A
4A
5A
6A
AIN0
R33
DGND
74LVC07
DGND
2
D3.3V
R36
1
D3
HSU119
1
C19
0.1u
ATE1D-2M3
DIT PDN
D3.3V
2
SW3
B
1
3
5
9
11
13
14
7
H
3
L
10k
U4
1A
2A
3A
4A
5A
6A
VCC
GND
1Y
2Y
3Y
4Y
5Y
6Y
2
4
6
8
10
12
DIT PDN
DIR PDN
I2C
1
AIN1 2
AIN0 3
MSN 4
CAD0/CKS 5
TEST1 6
TEST2 7
74HC14
C20
0.1u
VDD
SW4
14
13
12
11
10
9
8
B
AK4687 MODE
DGND
D3.3V
2
DGND
RP1
7
6
5
4
3
2
1
R37
1
D4
HSU119
I2C
AIN1
AIN0
MSN
CAD0/CKS
TEST1
TEST2
1
H
3
L
10k
47K
C21
0.1u
SW5
2
ATE1D-2M3
DIR PDN
VSS3
DGND
A
A
Title
Size
A3
- 45 5
4
3
Date:
2
AKD4688-A
Document Number
Rev
0
CONTROL
Tuesday, December 13, 2011
Sheet
1
3
of
6
5
4
3
2
1
DGND
+
2
1
D3.3V
C24 10u
C25 0.1u
D
D
C27
0.47u
R40
10k
2
3
RP2
4
3
2
1
C
DIT OCKS1
DIT OCKS0
38
37
INT1
R
AVDD
39
40
VCOM
41
AVSS
42
RX0
43
NC
44
RX1
45
46
NC
TEST1
TP1
IPS0
DIT
4
DIT_INT0
INT0
NC
OCKS0
DIF0
OCKS1
TEST2
CM1
DIF1
CM0
36
1
1
RX2
U5
8
7
6
5
RX3
1
2
3
4
47
SW6
DIF1
DIF0
OCKS1
OCKS0
48
D3.3V
35
DIT OCKS0
34
DIT OCKS1
33
47k
C
5
32
D3.3V
DGND
AK4118A
NC
7
DIF2
PDN
31
DIT PDN
C28
XTI
30
9
10
IPS1
XTO
P/SN
DAUX
XTL0
MCKO2
29
C29
5p
2
X1
12.288MHz
8
5p
1
6
DGND
28
DIR_MCLK
27
MCLK2
JP5
MCLK1
MCLK1
MCLK1_SEL
11
XTL1
BICK
26
BICK2
JP6
DIR_BICK
BICK1
BICK1
12
25
DIR_LRCK
LRCK2
JP7
LRCK1
LRCK1
C31
(open)
24
23
C34
0.1u
22
21
20
19
18
17
16
13
C33
0.1u
14
LRCK1_SEL
DGND
JP8
SDTO
2
1
C35
10u
GND
D3.3V
D3.3V
1
OPT
TX
R41
R42
MR-552LS
1:1
SDTO
PORT4
2
4
6
8
10
GND
GND
GND
GND
GND
BNC
DGND
240
150
Title
DGND
Size
A3
- 46 5
1
3
5
7
9
MCLK1
BICK1
LRCK1
JP9
T1
DA02
2
3
1
A
A1-10PA-2.54DSA
DGND
C37
0.1u
DGND
TX
2
DGND
3
2
TOTX147
J10
C32
(open)
C36
10u
PORT3
IN
VCC
+
1
+
SDTO
D3.3V
B
C30
(open)
BICK1_SEL
LRCK
MCKO1
DVSS
DVDD
VOUT
UOUT
COUT
BOUT
TX1
DVSS
TX0
SDTO
TVDD
VIN
15
B
4
3
Date:
2
AKD4688-A
Document Number
Rev
0
DIT
Tuesday, December 13, 2011
Sheet
1
4
of
6
A
5
4
3
2
1
PORT5
VCC
GND
OUT
3
D3.3V
2
1
C38
0.1u
TORX147
C39
+
10u
DGND
R43
C40
10u
2
OPT
J11
RX
2
3
1
D
470
C41
0.1u
1
D3.3V
+
DGND
JP10
C42
0.1u
RX
BNC
R44
D
75
MR-552LS
DGND
C43
0.47u
DGND
R45
10k
DGND
38
37
INT1
R
AVDD
39
40
VCOM
41
AVSS
42
RX0
43
NC
44
RX1
45
TEST1
46
RX2
DIR_INT0
TP2
IPS0
INT0
36
1
1
NC
RX3
47
U6
10
9
8
7
6
DIF2 1
DIF1 2
DIF0 3
OCKS1 4
OCKS0 5
48
D3.3V
SW7
DIR
2
NC
OCKS0
DIF0
OCKS1
35
DIR OCKS0
RP3
7
6
5
4
3
2
1
3
DIR OCKS1
DIR OCKS0
4
TEST2
CM1
DIF1
CM0
34
DIR OCKS1
33
C
C
DGND
6
AK4118A
NC
7
DIF2
PDN
32
31
DIR PDN
C44
5p
XTI
30
1
5
47K
IPS1
XTO
P/SN
DAUX
XTL0
MCKO2
29
C45
5p
2
X2
24.576MHz
8
DGND
DGND
9
28
DGND
10
11
XTL1
BICK
27
JP12 MCLK2
MCLK2
26
JP13 BICK2
12
C46
0.1u
BICK2
LRCK
25
B
JP14 LRCK2
LRCK2
24
MCKO1
23
22
DVSS
DVDD
21
VOUT
20
UOUT
19
COUT
18
BOUT
17
TX1
16
DVSS
14
13
DGND
TX0
SDTO
TVDD
VIN
15
B
C47
0.1u
2
1
C48
10u
D3.3V
+
+
JP15 SDTI
1
SDTI
2
C49
10u
DGND
D3.3V
DIR_LRCK
DGND
1
3
5
7
9
MCLK2
BICK2
LRCK2
SDTI
DIR_BICK
PORT6
2
4
6
8
10
GND
GND
GND
GND
GND
A1-10PA-2.54DSA
DIR_MCLK
A
A
DGND
Title
Size
A3
- 47 5
4
3
Date:
2
AKD4688-A
Document Number
Rev
0
DIR
Tuesday, December 13, 2011
Sheet
1
5
of
6
5
4
3
10u
OUT
C51
1
C50
+
IN
2
1
LM1117-3.3V
GND
T2
TM_+5V
3
0.1u
R46
2
REG
JP16
C52
C53
0.1u
(short)
+
D3.3V
D3.3V_SEL
+5V1
T-45(O)
D3.3V
10u
DVDD1
T-45(O)
AVDD1
T-45(O)
AVDD2
T-45(O)
D3.3V1
T-45(O)
1
1
1
1
D
TM_D3.3V
1
D
VSS3
TM_+5V
TM_AVDD1
+
TM_DVDD
TM_AVDD1
TM_AVDD2
TM_D3.3V
C54
47u
AVSS2
T-45(B)
VSS3
T-45(B)
DGND1
T-45(B)
1
47u
AVSS1
T-45(B)
1
DGND
REG
1
AVDD1
C55
1
JP17
+
AVDD1_SEL
AVSS1
C
AVDD1
C
AVSS1
AVSS2
VSS3
DGND
TM_AVDD2
JP18
+
AVDD2
C56
REG
47u
R47
R48
R49
(open)
(open)
(open)
AVDD2_SEL
AVSS2
AVDD2
AVSS1
B
TM_DVDD
AVSS2
AVSS2
R51
1
1
2
+
C57
AVSS1
B
JP19
2
GND
Cut Land open
Cut Land short
(open)
VSS3
CL2
CL1
R50
VSS3
(short)
CVSS
47u
CVSS
AVSS2
VSS3
DGND
VSS3
VSS3
DVDD
A
A
R52
VDD
Title
(short)
- 48 5
4
3
Size
A4
Date:
2
AKD4688-A
Document Number
Rev
0
POWER
Tuesday, December 13, 2011
Sheet
6
1
of
6
㻭㻷㻰㻠㻢㻤㻤㻙㻭㻙㻿㼁㻮㻌㻾㻱㼂㻚㻜
㒊ရ㠃䝅䝹䜽ᅗ
- 49 -
㻭㻷㻰㻠㻢㻤㻤㻙㻭㻙㻿㼁㻮㻌㻾㻱㼂㻚㻜
༙⏣㠃䝅䝹䜽ᅗ
- 50 -
㻭㻷㻰㻠㻢㻤㻤㻙㻭㻙㻿㼁㻮㻌㻾㻱㼂㻚㻜
䝟䝍䞊䞁ᅗ
- 51 -
㻭㻷㻰㻠㻢㻤㻤㻙㻭㻙㻿㼁㻮㻌㻾㻱㼂㻚㻜
䝟䝍䞊䞁ᅗ
- 52 -
㻭㻷㻰㻠㻢㻤㻤㻙㻭㻙㻿㼁㻮㻌㻾㻱㼂㻚㻜
䝟䝍䞊䞁ᅗ
- 53 -
㻭㻷㻰㻠㻢㻤㻤㻙㻭㻙㻿㼁㻮㻌㻾㻱㼂㻚㻜
䝟䝍䞊䞁ᅗ
- 54 -
㻭㻷㻰㻠㻢㻤㻤㻙㻭㻌㻾㼑㼢㻚㻜
㒊ရ㠃䝅䝹䜽ᅗ
- 55 -
㻭㻷㻰㻠㻢㻤㻤㻙㻭㻌㻾㼑㼢㻚㻜
༙⏣㠃䝅䝹䜽ᅗ
- 56 -
㻭㻷㻰㻠㻢㻤㻤㻙㻭㻌㻾㼑㼢㻚㻜
䝟䝍䞊䞁ᅗ
- 57 -
㻭㻷㻰㻠㻢㻤㻤㻙㻭㻌㻾㼑㼢㻚㻜
䝟䝍䞊䞁ᅗ
- 58 -