Precision Low Noise Operational Amplifier ISL76627 Features The ISL76627 is a very high precision amplifier featuring very low noise, low offset voltage, low input bias current and low temperature drift making it the ideal choice for applications requiring both high DC accuracy and AC performance. The combination of precision, low noise, and small footprint provides the user with outstanding value and flexibility relative to similar competitive parts. • Very Low Voltage Noise . . . . . . . . . . . . . . . . . . . . . . . .2.5nV/Hz Applications for ISL76627 include precision active filters, precision power supply controls, data acquisition signal conditioning, sensor interface, instrumentation and high grade audio. Of particular interest for automotive applications is the wide range operating voltage of this op-amp combined with the combination of precision and speed. The ISL76627 is available in an 8 Ld SOIC package. The device is offered in standard pin configurations and operates over the extended temperature range of -40°C to +125°C. The ISL76627 is fully TS16949 compliant and tested to AEC-Q100 specifications. • Low Input Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70µV, Max. • Superb Offset Drift . . . . . . . . . . . . . . . . . . . . . . 0.5µV/°C, Max. • Input Bias Current . . . . . . . . . . . . . . . . . . . . . . . . . . 10nA, Max. • Wide Supply Range . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 40V • Gain-bandwidth Product . . . . . . . . . 10MHz Unity Gain Stable • No Phase Reversal Applications • Precision Active Filters • Instrumentation • Sensor Interface • PLL Loop Filtering • Precision Signal Conditioning • High Grade Audio 100 1.5nF V+ VIN R1 R2 95.3 232 68.3nF OUTPUT + C2 V- SALLEN-KEY LOW PASS FILTER (1MHz) FIGURE 1. TYPICAL APPLICATION July 12, 2011 FN7725.0 1 INPUT NOISE VOLTAGE (nV/√Hz) C1 VS = ±19V AV = 1 10 1 0.1 1 10 100 1k 10k 100k FREQUENCY (Hz) FIGURE 2. INPUT NOISE VOLTAGE SPECTRAL DENSITY CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL76627 Ordering Information . PART NUMBER (Notes 1, 2, 3) ISL76627ABZ PART MARKING VOS (MAX) (µV) TEMP RANGE (°C) 70 -40 to +125 76627 ABZ PACKAGE (Pb-Free) 8 Ld SOIC PKG. DWG. # M8.15 NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL76627. For more information on MSL please see techbrief TB363. Pin Configuration ISL76627 (8 LD SOIC) TOP VIEW NC 1 8 NC -IN_A 2 7 V+ +IN_A 3 6 VOUTA V- 4 5 NC - + Pin Descriptions ISL76627 (8 LD SOIC) PIN NAME EQUIVALENT CIRCUIT 3 +IN_A Circuit 1 Amplifier A non-inverting input 4 V- Circuit 3 Negative power supply 7 V+ Circuit 3 Positive power supply 6 VOUTA Circuit 2 Amplifier A output 2 -IN_A Circuit 1 Amplifier A inverting input 1, 5, 8 NC - Not Connected – This pin is not electrically connected internally. V+ IN- V+ V- VCIRCUIT 2 2 V+ CAPACITIVELY TRIGGERED ESD CLAMP OUT IN+ CIRCUIT 1 DESCRIPTION VCIRCUIT 3 FN7725.0 July 12, 2011 ISL76627 Absolute Maximum Ratings Thermal Information Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Maximum Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5V Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V Max/Min Input Current for Input Voltage >V+ or <V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA Output Short-Circuit Duration (1 Output at a Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indefinite ESD Tolerance Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . .4.0kV Machine Model (Tested per EIA/JESD22-A115-A) . . . . . . . . . . . . . . 500V Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . .1.5kV Di-electrically Isolated PR40 process . . . . . . . . . . . . . . . . . . . Latch-up free Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 8 Ld SOIC (Note 4, 5) . . . . . . . . . . . . . . . . . . 120 60 Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Ambient Operating Temperature Range . . . . . . . . . . . . . .-40°C to +125°C Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. For θJC, the “case temp” location is taken at the package top center. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +125°C. PARAMETER VOS DESCRIPTION CONDITIONS Offset Voltage MIN (Note 6) TYP MAX (Note 6) UNIT -70 10 70 µV -120 - 120 µV TCVOS Offset Voltage Drift -0.5 0.1 0.5 µV/°C IOS Input Offset Current -10 1 10 nA -12 - 12 nA -10 1 10 nA -12 - 12 nA -13 - 13 V -12 - 12 V IB VCM CMRR PSRR Input Bias Current Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Guaranteed by CMRR VCM = -13V to +13V 115 120 - dB VCM = -12V to +12V 115 - - dB VS = ±2.25V to ±20V 115 125 - dB VS = ±3V to ± 20V 115 - - dB AVOL Open-Loop Gain VO = -13V to +13V RL = 10kΩ to ground 1000 1500 - V/mV VOH Output Voltage High RL = 10kΩ to ground 13.5 13.65 - V 13.2 - - V 13.4 13.5 - V 13.1 - - V - -13.65 -13.5 V - - -13.2 V - -13.5 -13.4 V - - -13.1 V RL = 2kΩ to ground VOL Output Voltage Low RL = 10kΩ to ground RL = 2kΩ to ground 3 FN7725.0 July 12, 2011 ISL76627 Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) PARAMETER IS ISC VSUPPLY DESCRIPTION CONDITIONS Supply Current/Amplifier Short-Circuit RL = 0Ω to ground Supply Voltage Range Guaranteed by PSRR MIN (Note 6) TYP MAX (Note 6) UNIT - 2.2 2.8 mA - - 3.7 mA - ±45 - mA ±2.25 - ±20 V - 10 - MHz AC SPECIFICATIONS GBW Gain Bandwidth Product enp-p Voltage Noise 0.1Hz to 10Hz - 85 - nVP-P en Voltage Noise Density f = 10Hz - 3 - nV/√Hz en Voltage Noise Density f = 100Hz - 2.8 - nV/√Hz en Voltage Noise Density f = 1kHz - 2.5 - nV/√Hz en Voltage Noise Density f = 10kHz - 2.5 - nV/√Hz in Current Noise Density f = 10kHz - 0.4 - pA/√Hz Total Harmonic Distortion + Noise 1kHz, G = 1, VO = 3.5VRMS, RL = 2kΩ - 0.00022 - % Slew Rate AV = 10, RL = 2kΩ, VO = 4VP-P - ±3.6 - V/µs Rise Time 10% to 90% of VOUT AV = -1, VOUT = 100mVP-P, Rf = Rg = 2kΩ, RL = 2kΩ to VCM - 36 - ns Fall Time 90% to 10% of VOUT AV = -1, VOUT = 100mVP-P, Rf = Rg = 2kΩ, RL = 2kΩ to VCM - 38 - ns Settling Time to 0.1% 10V Step; 10% to VOUT AV = -1 VOUT = 10VP-P, Rg = Rf =10k, RL = 2kΩ to VCM - 3.4 - µs Settling Time to 0.01% 10V Step; 10% to VOUT AV = -1, VOUT = 10VP-P, RL = 2kΩ to VCM - 3.8 - µs Output Overload Recovery Time AV = 100, VIN = 0.2V RL = 2kΩ to VCM - 1.7 - µs THD + N TRANSIENT RESPONSE SR tr, tf, Small Signal tS tOL Electrical Specifications VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +125°C. PARAMETER VOS DESCRIPTION CONDITIONS Offset Voltage MIN (Note 6) TYP MAX (Note 6) UNIT -70 10 70 µV -120 - 120 µV TCVOS Offset Voltage Drift -0.5 0.1 0.5 µV/°C IOS Input Offset Current -10 1 10 nA -12 - 12 nA 10 1 10 nA -12 - 12 nA -3 - 3 V -2 - 2 V VCM = -3V to +3V 115 120 - dB VCM = -2V to +2V 115 - - dB IB VCM CMRR Input Bias Current Common Mode Input Voltage Range Common-Mode Rejection Ratio 4 Guaranteed by CMRR FN7725.0 July 12, 2011 ISL76627 Electrical Specifications VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) PARAMETER PSRR DESCRIPTION Power Supply Rejection Ratio MIN (Note 6) TYP MAX (Note 6) UNIT VS = ±2.25V to ±5V 115 125 - dB VS = ±3V to ±5V 115 - - dB 1000 1500 - V/mV CONDITIONS AVOL Open-Loop Gain VO = -3V to +3V RL = 10kΩ to ground VOH Output Voltage High RL = 10kΩ to ground 3.5 3.65 - V 3.2 - - V 3.4 3.5 - 3.1 - - V - -3.65 -3.5 V - - -3.2 V - -3.5 -3.4 - - -3.1 V - 2.2 2.8 mA - - 3.7 mA - ±45 - mA - 10 - MHz 1kHz, G = 1, Vo = 2.5VRMS, RL = 2kΩ - 0.0034 - % Slew Rate AV = 10, RL = 2kΩ - ±3.6 - V/µs Rise Time 10% to 90% of VOUT AV = -1, VOUT = 100mVP-P, Rf = Rg = 2kΩ, RL = 2kΩ to VCM - 36 - ns Fall Time 90% to 10% of VOUT AV = -1, VOUT = 100mVP-P, Rf = Rg = 2kΩ, RL = 2kΩ to VCM - 38 - ns Settling Time to 0.1% AV = -1, VOUT = 4VP-P, Rf = Rg = 2kΩ, RL = 2kΩ to VCM - 1.6 - µs Settling Time to 0.01% AV = -1, VOUT = 4VP-P, Rf = Rg = 2kΩ, RL = 2kΩ to VCM - 4.2 - µs RL = 2kΩ to ground VOL Output Voltage Low RL = 10kΩ to ground RL = 2kΩ to ground IS ISC Supply Current/Amplifier Short-Circuit AC SPECIFICATIONS GBW THD + N Gain Bandwidth Product Total Harmonic Distortion + Noise TRANSIENT RESPONSE SR tr, tf, Small Signal tS NOTE: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 5 FN7725.0 July 12, 2011 ISL76627 Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. 100 INPUT NOISE VOLTAGE (nV/√Hz) INPUT NOISE VOLTAGE (nV/√Hz) 100 80 60 40 20 0 -20 V+ = 38V RL = 10k CL = 3.5pF Rg = 10, Rf = 100k AV = 10,000 -40 -60 -80 -100 0 1 2 3 4 5 6 7 8 9 VS = ±19V AV = 1 10 1 0.1 10 1 10 TIME (s) VS = ±19V AV = 1 10 PSRR (dB) INPUT NOISE CURRENT (pA/√Hz) 100 1 1 10 100 1k 10k 100k 130 120 110 100 90 80 70 60 50 40 30 20 10 0 -10 RL = INF CL = 5.25pF AV = +1 VS = 1VP-P PSRR+ AND PSRR- VS = ±15V 10 100 1k 10k 100k 10M 1M FREQUENCY (Hz) FIGURE 6. PSRR vs FREQUENCY, VS = ±5V, ±15V FIGURE 5. INPUT NOISE CURRENT SPECTRAL DENSITY 25 VS = ±5V MEDIAN 20 VS = ±2.25V 15 VS = ±21V 10 VOS (µV) CMRR (dB) 100k PSRR+ AND PSRR- VS = ±5V FREQUENCY (Hz) 130 120 110 100 90 80 70 60 50 40 30 20 10 0 -10 10 10k FIGURE 4. INPUT NOISE VOLTAGE SPECTRAL DENSITY FIGURE 3. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz 0.1 0.1 100 1k FREQUENCY (Hz) VS = ±15V VS = ±15V 0 -5 RL = INF CL = 5.25pF AV = +1 VCM = 1VP-P 100 5 VS = ±3V -10 -15 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 7. CMRR vs FREQUENCY, VS = ±2.25, ±5V, ±15V 6 -20 -40 VS = ±5V 36 UNITS -20 0 20 40 60 80 100 120 140 160 TEMPERATURE (°C) FIGURE 8. VOS vs TEMPERATURE vs VSUPPLY FN7725.0 July 12, 2011 ISL76627 Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 3.0 4.5 50 UNITS 4.0 MEDIAN IBIAS- 2.5 2.0 MEDIAN 2.0 3.0 IBIAS (nA) IBIAS (nA) 3.5 50 UNITS 2.5 IBIAS+ 1.5 1.0 IBIAS+ IBIAS- 1.5 0.5 1.0 0.5 -40 -20 0 20 40 60 80 100 0 -40 120 -20 0 20 40 60 80 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 9. IIB vs TEMPERATURE, VS = ±15V 120 FIGURE 10. IIB vs TEMPERATURE, VS = ±5V 0.5 60 29 UNITS VS = ±5 0.0 AVERAGE 40 50 UNITS -0.5 20 -1.0 -1.5 VOS (µV) IOS (nA) 100 VS = ±15 MEDIAN -2.0 +25°C 0 +125°C -20 -2.5 -40°C -40 -3.0 -3.5 -40 -20 0 20 40 60 80 100 -60 120 -15 -10 TEMPERATURE (°C) 5 10 15 -13.1 14.2 14.1 50 UNITS -13.2 MEDIAN 50 UNITS MEDIAN -13.3 14.0 -13.4 13.9 13.8 RL = 2k -13.5 RL = 100k VOUT (V) VOUT (V) 0 FIGURE 12. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE VOLTAGE, VS = ±15V FIGURE 11. IOS vs TEMPERATURE vs SUPPLY 13.7 13.6 RL = 2k 13.5 -13.6 -13.7 RL = 100k -13.8 -13.9 13.4 -14.0 13.3 -14.1 13.2 -5 INPUT COMMON MODE VOLTAGE -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) FIGURE 13. VOH vs TEMPERATURE, VS = ±15V 7 120 -14.2 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 14. VOL vs TEMPERATURE, VS = ±15V FN7725.0 July 12, 2011 ISL76627 200 180 160 140 120 100 80 60 40 20 0 -20 R = 10k L -40 CL = 10pF -60 SIMULATION -80 -100 0.1m 1m 10m 100m 1 OPEN LOOP GAIN (dB)/PHASE(°) OPEN LOOP GAIN (dB)/PHASE (°) Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) PHASE GAIN 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) 15 Rg = 100, Rf = 100k AV = 100 VS = ±15V CL = 3.5pF RL = INF VOUT = 100mVP-P 30 20 AV = 10 Rg = 10k, Rf = 100k 10 0 NORMALIZED GAIN (dB) GAIN (dB) 40 AV = 1 -10 100 Rg = OPEN, Rf = 0 1k 10k 100k 1M FREQUENCY (Hz) 10M 5 3 VS = ±15V RL = 10k 1 CL = 3.5pF -1 A = +2 V -3 VOUT = 100mVP-P 1k 10k Rf = Rg = 100 100k 1M 10M 100M FIGURE 18. FREQUENCY RESPONSE vs FEEDBACK RESISTANCE Rf/Rg RL = 10k 6 RL = 1k 5 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 7 7 1 0 -1 RL = 499 -2 -5 1k Rf = Rg = 1k 9 FREQUENCY (Hz) 2 -4 Rf = Rg = 10k 11 -5 100M FIGURE 17. FREQUENCY RESPONSE vs CLOSED LOOP GAIN -3 10 100 1k 10k 100k 1M 10M 100M Rf = Rg = 100k 13 Rg = 1k, Rf = 100k 50 GAIN FREQUENCY (Hz) 70 AV = 1000 PHASE FIGURE 16. OPEN-LOOP GAIN, PHASE vs FREQUENCY, RL = 10kΩ, CL = 100pF FIGURE 15. OPEN-LOOP GAIN, PHASE vs FREQUENCY, RL = 10kΩ, CL = 10pF 60 200 180 160 140 120 100 80 60 40 20 0 -20 R = 10k L -40 CL = 100pF -60 SIMULATION -80 -100 0.1m 1m 10m 100m 1 VS = ±15V CL = 3.5pF AV = +1 VOUT = 100mVP-P 10k RL = 100 RL = 49.9 4 VS = ±15V RL = 10k AV = +1 VOUT = 100mVP-P 3 10M FIGURE 19. GAIN vs FREQUENCY vs RL 8 100M CL = 220pF CL = 100pF 2 CL = 25.5pF 1 0 -1 CL = 3.5pF -2 100k 1M FREQUENCY (Hz) CL = 1000pF -3 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M FIGURE 20. GAIN vs FREQUENCY vs CL FN7725.0 July 12, 2011 ISL76627 Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 6 VS = ±2.25V 5 4 0 VS = ±5V -1 VS = ±15V CL = 3.5pF RL = 10k AV = +1 VOUT = 100mVP-P -2 10k 1k VS = ±15V CL = 3.5pF AV = 1 Rf = 0 Rg = inf VOUT = 10VP-P 3 2 1 0 1 -2 -3 RL = 2k RL = 10k -4 -5 100k 1M 10M -6 100M 0 5 10 15 TIME (µs) FREQUENCY (Hz) 2.4 60 1.2 SMALL SIGNAL (mV) LARGE SIGNAL (V) 1.6 VS = ±15V, RL = 2k, 10k 0.8 0.4 0 -0.4 VS = ±5V, RL = 2k, 10k -0.8 -1.2 -1.6 CL = 3.5pF AV = 1 VOUT = 4VP-P -2.0 0 5 10 15 20 25 TIME (µs) 30 35 VS = ±15V RL = 10k CL = 3.5pF AV = 100 Rf = 100k, Rg = 1k VIN = 200mVP-P -0.18 -0.20 10 15 20 25 TIME (µs) 30 13 0.22 11 0.08 9 0.04 7 5 OUTPUT 5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 35 2 OUTPUT 0.10 0.06 3 0.02 1 -0.02 -1 40 -0.06 0 FIGURE 25. POSITIVE OUTPUT OVERLOAD RESPONSE TIME, VS = ±15V 9 RL = 2k CL = 3.5pF AV = 1 VOUT = 100mVP-P 40 0.26 INPUT (V) INPUT (V) -0.02 -0.10 20 FIGURE 24. SMALL SIGNAL TRANSIENT RESPONSE, VS = ±5V, ±15V OUTPUT (V) INPUT -0.14 VS = ±5V, ±15V 0 80 40 15 -0.06 20 TIME (ms) 0.06 0.02 40 60 FIGURE 23. LARGE SIGNAL TRANSIENT RESPONSE vs RL, VS = ±5V, ±15V 0 30 80 2.0 -0.26 25 FIGURE 22. LARGE SIGNAL 10V STEP RESPONSE, VS = ±15V FIGURE 21. GAIN vs FREQUENCY vs SUPPLY VOLTAGE -2.4 20 0 VS = ±15V RL = 10k CL = 3.5pF AV = 100 Rf = 100k, Rg = 1k VIN = 200mVP-P -2 INPUT -10 -4 -6 -8 OUTPUT (V) -3 LARGE SIGNAL(V) NORMALIZED GAIN (dB) 1 -12 5 10 15 20 25 TIME (µs) 30 35 -14 40 FIGURE 26. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME, VS = ±15V FN7725.0 July 12, 2011 ISL76627 Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 90 VS = ±15V RL = 10k AV = 1 VOUT = 100mVP-P 80 OVERSHOOT (%) 70 60 + OT HO S ER OV 50 40 T OO SH ER V O 30 20 - 10 0 10 100 1000 CAPACITANCE (pF) 10000 FIGURE 27. % OVERSHOOT vs LOAD CAPACITANCE, VS = ±15V Applications Information • The amplifier input is supplied from a low impedance source. Functional Description • The input voltage rate-of-rise (dV/dt) exceeds the maximum slew rate of the amplifier (±3.6V/µs). The ISL76627 is a single, low noise 10MHz BW precision op amp. The device is fabricated in a new precision 40V complementary bipolar DI process. A super-beta NPN input stage with input bias current cancellation provides low input bias current (1nA typical), low input offset voltage (10µV typ), low input noise voltage (3nV/√Hz), and low 1/f noise corner frequency (5Hz). The amplifier also features high open loop gain (1500V/mV) for excellent CMRR (120dB) and THD+N performance (0.0002% @ 3.5VRMS, 1kHz into 2kΩ). A complementary bipolar output stage enables high capacitive load drive without external compensation. If the output lags far enough behind the input, the anti-parallel input diodes can conduct. For example, if an input pulse ramps from 0V to +10V in 1µs, then the output of the ISL76627 will reach only +3.6V (slew rate = 3.6V/µs), while the input is at 10V. The input differential voltage of 6.4V will force input ESD diodes to conduct, dumping the input current directly into the output stage and the load. The resulting current flow can cause permanent damage to the ESD diodes. The ESD diodes are rated to 20mA, and in the previous example, setting RIN to 1k resistor (see Figure 28) would limit the current to < 6.4mA, and provide additional protection up to ±20V at the input. Operating Voltage Range In applications where one or both amplifier input terminals are at risk of exposure to high voltage, current limiting resistors may be needed at each input terminal (see Figure 29 RIN+, RIN-) to limit current through the power supply ESD diodes to 20mA. The device is designed to operate over the 4.5V (±2.25V) to 40V (±20V) range and are fully characterized at 10V (±5V) and 30V (±15V). Parameter variation with operating voltage is shown in the “Typical Performance Curves” beginning on page 6. V+ Input ESD Diode Protection The input terminals (IN+ and IN-) have internal ESD protection diodes to the positive and negative supply rails, and an additional anti-parallel diode pair across the inputs (see Figures 28 and 29). V+ RIN VOUT + RL V- FIGURE 28. INPUT ESD DIODE CURRENT LIMITING- UNITY GAIN For unity gain applications (see Figure 28) where the output is connected directly to the non-inverting input, a current limiting resistor (RIN) will be needed under the following conditions to protect the anti-parallel differential input protection diodes. 10 VIN+ RIN- - RIN+ + VOUT RL V- VIN VIN- FIGURE 29. INPUT ESD DIODE CURRENT LIMITING - DIFFERENTIAL INPUT Output Current Limiting The output current is internally limited to approximately ±45mA at +25°C and can withstand a short circuit to either rail as long as the power dissipation limits are not exceeded. Continuous operation under these conditions may degrade long term reliability. FN7725.0 July 12, 2011 ISL76627 Output Phase Reversal ISL76627 SPICE Model Output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. The ISL76627 is immune to output phase reversal, even when the input voltage is 1V beyond the supplies. Figure 30 shows the SPICE model schematic and Figure 31 shows the net list for the ISL76627 SPICE model. The model is a simplified version of the actual device and simulates important AC and DC parameters. AC parameters incorporated into the model are: 1/f and flatband noise, Slew Rate, CMRR, Gain and Phase. The DC parameters are VOS, IOS, total supply current and output voltage swing. The model does not model input bias current. The model uses typical parameters given in the “Electrical Specifications” table beginning on page 3. The AVOL is adjusted for 128dB with the dominate pole at 5Hz. The CMRR is set higher than the “Electrical Specifications” table to better match design simulations (150dB,f = 50Hz). The input stage models the actual device to present an accurate AC representation. The model is configured for ambient temperature of +25°C. Power Dissipation It is possible to exceed the +150°C maximum junction temperatures under certain load and power supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related using Equation 1: (EQ. 1) T JMAX = T MAX + θ JA xPD MAX where: • PDMAX is the maximum power dissipation of the amplifier in the package, and can be calculated using Equation 2: V OUTMAX PD MAX = V S × I qMAX + ( V S - V OUTMAX ) × -----------------------R L (EQ. 2) where: • TMAX = Maximum ambient temperature • θJA = Thermal resistance of the package • VS = Total supply voltage • IqMAX = Maximum quiescent supply current of the amplifier • VOUTMAX = Maximum output voltage swing of the application • RL = Load resistance Figures 32 through 47 show the characterization vs simulation results for the Noise Voltage, Closed Loop Gain vs Frequency, Closed Loop Gain vs Rf/Rg, Closed Loop Gain vs RL, Closed Loop Gain vs CL, Large Signal 10V Step Response, Open Loop Gain Phase and Simulated CMRR vs Frequency. LICENSE STATEMENT The information in this SPICE model is protected under the United States copyright laws. Intersil Corporation hereby grants users of this macro-model hereto referred to as “Licensee”, a nonexclusive, nontransferable licence to use this model as long as the Licensee abides by the terms of this agreement. Before using this macro-model, the Licensee should read this license. If the Licensee does not accept these terms, permission to use the model is not granted. The Licensee may not sell, loan, rent, or license the macro-model, in whole, in part, or in modified form, to anyone outside the Licensee’s company. The Licensee may modify the macro-model to suit his/her specific applications, and the Licensee may make copies of this macro-model for use within their company only. This macro-model is provided “AS IS, WHERE IS, AND WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUY NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.” In no event will Intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. Intersil reserves the right to make changes to the product and the macro-model without prior notice. 11 FN7725.0 July 12, 2011 ISL76627 . V++ V++ R3 R4 4.45k 4 CASCODE 5 Q4 C4 2.5pF Vin- VIN- + - C6 2pF 0.1V 25 Q5 2 SUPERB D1 3 SUPERB DX EOS Vmid 9 + - IEE 200E-6 5E11 + - En Vc + - + - Q3 1E-9 R2 C5 2.5pF Mirror VCM 377.4 8 7 1 IOS R17 In+ VIN+ 5 6 R1 5E11 24 DN CASCODE 4 Q1 Q2 V5 D12 IEE1 96E-6 4.45k + VOS - 10E-6 V-VCM VOLTAGE NOISE INPUT STAGE V++ V++ 10 + - 4 5 D2 DX + V1 - 1.86V G3 13 + - R5 1 D4 DX + V3 - 1.86V 11 G5 R7 C2 55.55pF 572.9E6 Vg + 12 - R8 G4 V2 1.86V D3 DX + V-VCM R6 1 G2 14 - V4 1.86V 55.55pF R11 1 Vg R12 1 G6 18 VCM D5 DX L2 3.18E-3 V-- 2ND GAIN STAGE 1ST GAIN STAGE 17 Vc R10 1 C3 572.9E6 + + - Vmid R9 1 Vmid Vc L1 3.18E-3 + - + - G1 COMMON MODE GAIN STAGE MID SUPPLY REF V++ E2 22 ISY 2.2mA Vg D6 DX 23 20 G7 + V5 1.12V V- V6 21 + DX - D7 1.12V G8 + + E3 V- V-- D10 DY + G9 + - R15 90 - + - D9 DX + + - D8 DX V+ D11 DY VOUT VOUT R16 90 + - V+ G10 OUTPUT STAGE SUPPLY ISOLATION STAGE FIGURE 30. SPICE SCHEMATIC 12 FN7725.0 July 12, 2011 ISL76627 * source ISL76627_SPICEmodel * Revision C, August 8th 2009 LaFontaine * Model for Noise, supply currents, 150dB f=50Hz CMRR, *128dB f=5Hz AOL *Copyright 2009 by Intersil Corporation *Refer to data sheet “LICENSE STATEMENT” Use of *this model indicates your acceptance with the *terms and provisions in the License Statement. * Connections: +input * | -input * | | +Vsupply * | | | -Vsupply * | | | | output * | | | | | .subckt ISL28127subckt Vin+ Vin-V+ V- VOUT * source ISL28127_SPICEMODEL_0_0 * *Voltage Noise E_En IN+ VIN+ 25 0 1 R_R17 25 0 377.4 TC=0,0 D_D12 24 25 DN V_V7 24 0 0.1 * *Input Stage I_IOS IN+ VIN- DC 1e-9 C_C6 IN+ VIN- 2E-12 R_R1 VCM VIN- 5e11 TC=0,0 R_R2 IN+ VCM 5e11 TC=0,0 Q_Q1 2 VIN- 1 SuperB Q_Q2 3 8 1 SuperB Q_Q3 V-- 1 7 Mirror Q_Q4 4 6 2 Cascode Q_Q5 5 6 3 Cascode R_R3 4 V++ 4.45e3 TC=0,0 R_R4 5 V++ 4.45e3 TC=0,0 C_C4 VIN- 0 2.5e-12 C_C5 8 0 2.5e-12 D_D1 6 7 DX I_IEE 1 V-- DC 200e-6 I_IEE1 V++ 6 DC 96e-6 V_VOS 9 IN+ 10e-6 E_EOS 8 9 VC VMID 1 * *1st Gain Stage G_G1 V++ 11 4 5 0.0487707 G_G2 V-- 11 4 5 0.0487707 R_R5 11 V++ 1 TC=0,0 R_R6 V-- 11 1 TC=0,0 D_D2 10 V++ DX D_D3 V-- 12 DX V_V1 10 11 1.86 V_V2 11 12 1.86 * *2nd Gain Stage G_G3 V++ VG 11 VMID 4.60767E-3 G_G4 V-- VG 11 VMID 4.60767E-3 R_R7 VG V++ 572.958E6 TC=0,0 R_R8 V-- VG 572.958E6 TC=0,0 C_C2 VG V++ 55.55e-12 TC=0,0 C_C3 V-- VG 55.55e-12 TC=0,0 D_D4 13 V++ DX D_D5 V-- 14 DX V_V3 13 VG 1.86 V_V4 VG 14 1.86 * *Mid supply Ref R_R9 VMID V++ 1 TC=0,0 R_R10 V-- VMID 1 TC=0,0 I_ISY V+ V- DC 2.2E-3 E_E2 V++ 0 V+ 0 1 E_E3 V-- 0 V- 0 1 * *Common Mode Gain Stage with Zero G_G5 V++ VC VCM VMID 31.6228e-9 G_G6 V-- VC VCM VMID 31.6228e-9 R_R11 VC 17 1 TC=0,0 R_R12 18 VC 1 TC=0,0 L_L1 17 V++ 3.183e-3 L_L2 18 V-- 3.183e-3 * *Output Stage with Correction Current Sources G_G7 VOUT V++ V++ VG 1.11e-2 G_G8 V-- VOUT VG V-- 1.11e-2 G_G9 22 V-- VOUT VG 1.11e-2 G_G10 23 V-- VG VOUT 1.11e-2 D_D6 VG 20 DX D_D7 21 VG DX D_D8 V++ 22 DX D_D9 V++ 23 DX D_D10 V-- 22 DY D_D11 V-- 23 DY V_V5 20 VOUT 1.12 V_V6 VOUT 21 1.12 R_R15 VOUT V++ 9E1 TC=0,0 R_R16 V-- VOUT 9E1 TC=0,0 * .model SuperB npn + is=184E-15 bf=30e3 va=15 ik=70E-3 rb=50 + re=0.065 rc=35 cje=1.5E-12 cjc=2E-12 + kf=0 af=0 .model Cascode npn + is=502E-18 bf=150 va=300 ik=17E-3 rb=140 + re=0.011 rc=900 cje=0.2E-12 cjc=0.16E-12f + kf=0 af=0 .model Mirror pnp + is=4E-15 bf=150 va=50 ik=138E-3 rb=185 + re=0.101 rc=180 cje=1.34E-12 cjc=0.44E-12 + kf=0 af=0 .model DN D(KF=6.69e-9 AF=1) .MODEL DX D(IS=1E-12 Rs=0.1) .MODEL DY D(IS=1E-15 BV=50 Rs=1) .ends ISL28127subckt FIGURE 31. SPICE NET LIST 13 FN7725.0 July 12, 2011 ISL76627 Characterization vs Simulation Results 100 INPUT NOISE VOLTAGE (nV/√Hz) INPUT NOISE VOLTAGE (nV/√Hz) 100 VS = ±19V AV = 1 10 1 0.1 1 10 100 1k 10k 10 V(INOISE) 1 0.1 100k 1 10 AV = 1000 Rg = 100, Rf = 100k Rg = 10k, Rf = 100k 10 Rg = OPEN, Rf = 0 1k 15 10k 100k 1M FREQUENCY (Hz) 10M 30 20 Rg = 10k, Rf = 100k 9 Rf = Rg = 1k 7 5 Rf = Rg = 100 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 36. CHARACTERIZED CLOSED LOOP GAIN vs Rf/Rg 14 AV = 1 Rg = OPEN, Rf = 0 1k 10k 15 11 10k AV = 10 100k 1M FREQUENCY (Hz) 10M 100M FIGURE 35. SIMULATED CLOSED LOOP GAIN vs FREQUENCY Rf = Rg = 10k 3 VS = ±15V RL = 10k 1 CL = 3.5pF -1 A = +2 V -3 VOUT = 100mVP-P Rg = 100, Rf = 100k Rg = 1k, Rf = 100k -10 100 100M Rf = Rg = 100k 13 1k 40 0 FIGURE 34. CHARACTERIZED CLOSED LOOP GAIN vs FREQUENCY NORMALIZED GAIN (dB) 100k AV = 100 10 AV = 1 -10 100 -5 GAIN (dB) VS = ±15V CL = 3.5pF RL = INF VOUT = 100mVP-P AV = 10 AV = 1000 50 Rf = Rg = 100k 13 NORMALIZED GAIN (dB) GAIN (dB) AV = 100 30 0 60 Rg = 1k, Rf = 100k 50 20 10k 70 70 40 1k FIGURE 33. SIMULATED INPUT NOISE VOLTAGE FIGURE 32. CHARACTERIZED INPUT NOISE VOLTAGE 60 100 FREQUENCY (Hz) FREQUENCY (Hz) 11 Rf = Rg = 10k 9 7 Rf = Rg = 1k 5 3 VS = ±15V RL = 10k CL = 3.5pF -1 A = +2 V -3 VOUT = 100mVP-P Rf = Rg = 100 1 -5 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 37. SIMULATED CLOSED LOOP GAIN vs R f/Rg FN7725.0 July 12, 2011 ISL76627 Characterization vs Simulation Results (Continued) 2 2 1 RL = 1k NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) RL = 10k 0 -1 RL = 499 -2 RL = 100 VS = ±15V -3 RL = 49.9 CL = 3.5pF AV = +1 VOUT = 100mVP-P -4 -5 1k 10k 100k 1M FREQUENCY (Hz) 10M 1 RL = 100 VS = ±15V -3 CL = 3.5pF AV = +1 VOUT = 100mVP-P -4 RL = 49.9 10k 100k 1M FREQUENCY (Hz) 10M 100M FIGURE 39. SIMULATED CLOSED LOOP GAIN vs RL 7 VS = ±15V RL = 10k AV = +1 VOUT = 100mVP-P 5 4 CL = 1000pF CL = 220pF 3 CL = 100pF 2 CL = 25.5pF 1 0 -1 CL = 3.5pF -2 1k 10k 100k 1M FREQUENCY (Hz) 5 4 CL = 1000pF 3 2 CL = 220pF 1 0 CL = 25.5pF -1 CL = 100pF -2 10M CL = 3.5pF -3 100M FIGURE 40. CHARACTERIZED CLOSED LOOP GAIN vs CL 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M FIGURE 41. SIMULATED CLOSED LOOP GAIN vs CL 6 6 5 5 4 4 2 1 0 LARGE SIGNAL (V) VS = ±15V CL = 3.5pF AV = 1 Rf = 0, Rg = INF VOUT = 10VP-P 3 1 -2 -3 RL = 2k RL = 10k -4 VS = ±15V CL = 3.5pF AV = 1 Rf = 0, Rg = INF VOUT = 10VP-P 3 2 1 0 1 -2 -3 RL = 10k -4 -5 -5 -6 VS = ±15V RL = 10k AV = +1 VOUT = 100mVP-P 6 NORMALIZED GAIN (dB) 6 NORMALIZED GAIN (dB) RL = 499 -2 -5 1k 100M 7 LARGE SIGNAL (V) RL = 1k -1 FIGURE 38. CHARACTERIZED CLOSED LOOP GAIN vs R L -3 RL = 10k 0 0 5 10 15 TIME (µs) 20 25 FIGURE 42. CHARACTERIZED LARGE SIGNAL 10V STEP RESPONSE 15 30 -6 0 5 10 15 TIME (µs) 20 25 30 FIGURE 43. SIMULATED LARGE SIGNAL 10V STEP RESPONSE FN7725.0 July 12, 2011 ISL76627 200 180 160 140 120 100 80 60 40 20 0 -20 R = 10k L -40 CL = 10pF -60 SIMULATION -80 -100 0.1m 1m 10m100m 1 OPEN LOOP GAIN (dB)/PHASE (°) OPEN LOOP GAIN (dB)/PHASE (°) Characterization vs Simulation Results (Continued) PHASE GAIN 10 100 1k 10k 100k 1M 10M100M FREQUENCY (Hz) PHASE 100 50 GAIN 0 RL = 10k -50 CL = 10pF MODEL VOS SET TO ZERO FOR THIS TEST -100 0.1Hz 10Hz 1.0k 100k 10M FREQUENCY (Hz) 150 VS = ±5V VS = ±2.25V 100 CMRR (dB) CMRR (dB) 150 FIGURE 45. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY FIGURE 44. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY 130 120 110 100 90 80 70 60 50 40 30 20 10 0 -10 10 200 VS = ±15V RL = INF CL = 5.25pF AV = +1 VCM = 1VP-P 100 50 0 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 46. CHARACTERIZED CMRR vs FREQUENCY 16 10M GENERATED USING FULL MODEL. CMRR DELTA INPUT BASE VOLTAGE/VCM INPUT VOLTAGE -50 10m 1.0Hz 100Hz 10k 1.0M 100M 10G 1.0T FREQUENCY (Hz) FIGURE 47. SIMULATED CMRR vs FREQUENCY FN7725.0 July 12, 2011 ISL76627 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION 7/12/11 FN7725.0 CHANGE Initial Release. Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL76627 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17 FN7725.0 July 12, 2011 ISL76627 Package Outline Drawing M8.15 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 3, 3/11 DETAIL "A" 1.27 (0.050) 0.40 (0.016) INDEX 6.20 (0.244) 5.80 (0.228) AREA 0.50 (0.20) x 45° 0.25 (0.01) 4.00 (0.157) 3.80 (0.150) 1 2 8° 0° 3 0.25 (0.010) 0.19 (0.008) SIDE VIEW “B” TOP VIEW 2.20 (0.087) SEATING PLANE 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 1 8 2 7 0.60 (0.023) 1.27 (0.050) 3 6 4 5 -C- 1.27 (0.050) 0.51(0.020) 0.33(0.013) SIDE VIEW “A 0.25(0.010) 0.10(0.004) 5.20(0.205) TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS-012-AA ISSUE C. 18 FN7725.0 July 12, 2011