GMF05LC-HSF www.vishay.com Vishay Semiconductors 5-Line ESD Protection Diode Array in LLP75-6L FEATURES • Ultra compact LLP75-6L package 6 5 • Low package profile < 0.6 mm 4 • 5-line ESD-protection • Low leakage current IR < 0.1 μA • Low load capacitance of typ. 43 pF at VR = 0 V 1 2 3 • ESD-immunity acc. IEC 61000-4-2 ± 30 kV contact discharge ± 30 kV air discharge 19957 19956 1 • Working voltage range VRWM = 5 V MARKING (example only) • e4 - precious metal (e.g. Ag, Au, NiPd, NiPdAu) (no Sn) • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 XX YY 21001 Dot = pin 1 marking XX = date code YY = type code (see table below) ORDERING INFORMATION DEVICE NAME ORDERING CODE TAPED UNITS PER REEL (8 mm TAPE ON 7" REEL) MINIMUM ORDER QUANTITY GMF05LC-HSF GMF05LC-HSF-GS08 3000 15 000 PACKAGE DATA DEVICE NAME PACKAGE NAME TYPE CODE WEIGHT MOLDING COMPOUND FLAMMABILITY RATING MOISTURE SENSITIVITY LEVEL SOLDERING CONDITIONS GMF05LC-HSF LLP75-6L 1B 4.2 mg UL 94 V-0 MSL level 1 (according J-STD-020) 260 °C/10 s at terminals ABSOLUTE MAXIMUM RATINGS GMF05LC-HSF PARAMETER TEST CONDITIONS SYMBOL VALUE UNIT Peak pulse current BiAs-mode: each input (pin 1; 3 to pin 6) to ground (pin 2); acc. IEC 61000-4-5; tp = 8/20 μs; single shot IPPM 5 A Peak pulse power BiAs-mode: each input (pin 1; 3 to pin 6) to ground (pin 2); acc. IEC 61000-4-5; tp = 8/20 μs; single shot PPP 70 W BiAs-mode: each input (pin 1; 3 to pin 6) to ground (pin 2); acc. IEC 61000-4-2; 10 pulses ± 30 kV ESD immunity ± 30 kV TJ -55 to +125 °C TSTG -55 to +150 °C Operating temperature Storage temperature Rev. 1.4, 16-Jul-15 Junction temperature Contact discharge Air discharge VESD Document Number: 81200 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 GMF05LC-HSF www.vishay.com Vishay Semiconductors BiAs-MODE (5-line bidirectional asymmetrical protection mode) With the GMF05LC-HSF up to 5 signal- or data-lines (L1 to L5) can be protected against voltage transients. With pin 2 connected to ground and pin 1; pin 3 up to pin 6 connected to a signal- or data-line which has to be protected. As long as the voltage level on the data- or signal-line is between 0 V (ground level) and the specified maximum reverse working voltage (VRWM) the protection diode between data-line and ground offer a high isolation to the ground line. The protection device behaves like an open switch. As soon as any positive transient voltage signal exceeds the break through voltage level of the protection diode, the diode becomes conductive and shorts the transient current to ground. Now the protection device behaves like a closed switch. The clamping voltage (VC) is defined by the breakthrough voltage (VBR) level plus the voltage drop at the series impedance (resistance and inductance) of the protection device. Any negative transient signal will be clamped accordingly. The negative transient current is flowing in the forward direction of the protection diode. The low forward voltage (VF) clamps the negative transient close to the ground level. Due to the different clamping levels in forward and reverse direction the GMF05LC-HSF clamping behaviour is bidirectional and asymmetrical (BiAs). L1 Ground L2 1 5 2 4 3 3 L5 L4 L3 BiAs 20739 ELECTRICAL CHARACTERISTICS GMF05LC-HSF PARAMETER Protection paths Reverse stand-off voltage Reverse current Reverse breakdown voltage TEST CONDITIONS/REMARKS SYMBOL MIN. TYP. MAX. UNIT Number of lines which can be protected Nchannel - - 5 lines at IR = 1 μA VRWM - - 5 V at VR = VRWM = 5 V IR - 0.01 0.1 μA at IR = 1 mA VBR 6 - 8 V - 8 9.5 V - 11.5 12.5 V at IPP = 1 A acc. IEC 61000-4-5 Reverse clamping voltage VC at IPP = IPPM = 5 A acc. IEC 61000-4-5 at IF = 1 A acc. IEC 61000-4-5 Forward clamping voltage VF at IPP = IPPM = 5 A acc. IEC 61000-4-5 at VR = 0 V; f = 1 MHz Capacitance CD at VR = 2.5 V; f = 1 MHz - 1.5 2 V - 3.1 4 V - 43 50 pF - 25 - pF Note • Ratings at 25 °C ambient temperature, unless otherwise specified. BiAs mode: each input (pin 1, 2, 3, to 6) to ground (pin 2). If a higher surge current or peak pulse current (IPP) is needed, some protection diodes in the GMF05LC-HSF can also be used in parallel in order to “multiply” the performance. If two diodes are switched in parallel you get • double surge power = double peak pulse current (2 x IPPM) • half of the line inductance = reduced clamping voltage • half of the line resistance = reduced clamping voltage • double line capacitance (2 x CD) • double reverse leakage current (2 x IR) L1 1 6 2 5 3 4 L2 L3 Ground 20740 Rev. 1.4, 16-Jul-15 Document Number: 81200 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 GMF05LC-HSF www.vishay.com Vishay Semiconductors TYPICAL CHARACTERISTICS Tamb = 25 °C, unless otherwise specified 100 120 % BiAs-mode Rise time = 0.7 ns to 1 ns 10 80 % 1 IF (mA) Discharge Current IESD 100 % 60 % 53 % 0.1 40 % 27 % 0.01 20 % 0.001 0.5 0% -10 0 10 20 30 40 50 60 70 80 90 100 Time (ns) 20557 0.6 0.7 Fig. 1 - ESD Discharge Current Wave Form acc. IEC 61000-4-2 (330 /150 pF) 0.8 0.9 1 VF (V) 20282 Fig. 4 - Typical Forward Current IF vs. Forward Voltage VF 10 8 µs to 100 % 100 % 9 BiSy-mode 8 80 % 7 6 VR (V) IPPM 60 % 20 µs to 50 % 40 % BiAs-mode 5 4 3 20 % 2 1 0% 0 10 20 30 0 40 0.01 Time (µs) 20548 0.1 1 Fig. 2 - 8/20 μs Peak Pulse Current Wave Form acc. IEC 61000-4-5 10 100 1000 10 000 IR (µA) 20283 Fig. 5 - Typical Reverse Voltage VR vs. Reverse Current IR 16 50 f = 1 MHz 45 BiSy-mode 14 40 12 10 30 VC (V) CD (pF) 35 BiAs-mode 25 20 6 15 BiSy-mode 10 2 Measured acc. IEC 61000-4-5 (8/20µs - wave form) 0 20284 0 1 2 3 4 5 6 VR (V) Fig. 3 - Typical Capacitance CD vs. Reverse Voltage VR Rev. 1.4, 16-Jul-15 VC 4 5 20281 BiAs-mode 8 0 0 1 2 3 4 5 6 IPP (A) Fig. 6 - Typical Peak Clamping Voltage VC vs. Peak Pulse Current IPP Document Number: 81200 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 GMF05LC-HSF www.vishay.com Vishay Semiconductors 60 80 60 Acc. IEC 61000-4-2 + 8 kV contact discharge 40 20 VC-ESD (V) VC-ESD (V) 40 20 0 0 - 20 - 20 - 40 - 40 - 60 - 60 - 10 0 21105 Acc. IEC 61000-4-2 - 8 kV contact discharge - 80 - 10 0 10 20 30 40 50 60 70 80 90 t (ns) 21106 Fig. 7 - Typical Clamping Performance at + 8 kV Contact Discharge (acc. IEC 61000-4-2) 300 10 20 30 40 50 60 70 80 90 t (ns) Fig. 8 - Typical Clamping Performance at - 8 kV Contact Discharge (acc. IEC 61000-4-2) Acc. IEC 61000-4-2 contact discharge 200 Positive discharge VC-ESD (V) 100 VC-ESD 0 - 100 Negative discharge - 200 - 300 0 21107 5 10 15 20 25 30 VESD (kV) Fig. 9 - Typical Peak Clamping Voltage at ESD Contact Discharge (acc. IEC 61000-4-2) Rev. 1.4, 16-Jul-15 Document Number: 81200 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 GMF05LC-HSF www.vishay.com Vishay Semiconductors 0.45 (0.018) 0.55 (0.022) 0.2 (0.008) 0.3 (0.012) 0.2 (0.008) 0.3 (0.012) 1 (0.039) 0.2 (0.008) 0.3 (0.012) Heat sink 0.95 (0.037) 1.05 (0.041) PACKAGE DIMENSIONS in millimeters (inches): LLP75-6L 0.5 (0.020) 0.6 (0.024) 0.54 (0.021) 0.60 (0.023) 0.05 (0.002) 0 (0.000) 0.15 (0.006) 0.25 (0.010) 1.65 (0.065) 1.55 (0.061) 1.55 (0.061) 1.65 (0.065) Pin 1 marking Foot print recommendation: 0.5 (0.020) 0.5 (0.020) 0.3 (0.012) 0.3 (0.012) Document no.:S8-V-3906.02-010 (4) Created - Date: 04. MAY 2005 Rev. 4 - Date: 21. March 2006 0.15 (0.006) 1 (0.039) 0.5 (0.020) 1 (0.039) 0.25 (0.010) 0.15 (0.006) Solder resist mask Solder pad 0.5 (0.020) 20454 Rev. 1.4, 16-Jul-15 Document Number: 81200 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 GMF05LC-HSF www.vishay.com Vishay Semiconductors LLP75-6x S9 F5 Pad layout - view from top / seen at bottom side S8-V-3906.02-004 (4) 10.01.2005 Rev. 1.4, 16-Jul-15 Pin 1 - location Document Number: 81200 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000