VBUS053CZ-HAF www.vishay.com Vishay Semiconductors USB-OTG BUS-Port ESD-Protection for VBUS = 28 V FEATURES • Ultra compact LLP75-7L package • Low package height < 0.6 mm 6 5 4 • 3-line USB ESD-protection with max. working range = 5.5 V • VBUS-protection with 28 V working range 7 1 2 3 • Low leakage current • Low load capacitance CD = 0.7 pF 21102 • ESD-protection to IEC 61000-4-2 ± 15 kV contact discharge ± 15 kV air discharge 20517 1 • Surge current acc. IEC 61000-4-5 IPP > 3 A MARKING (example only) • e4 - precious metal (e.g. Ag, Au, NiPd, NiPdAu) (no Sn) XX YY • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 21001 Dot = pin 1 marking XX = date code YY = type code (see table below) ORDERING INFORMATION ORDERING CODE TAPED UNITS PER REEL (8 mm TAPE on 7" REEL) MINIMUM ORDER QUANTITY VBUS053CZ-HAF-G-08 3000 15 000 DEVICE NAME VBUS053CZ-HAF PACKAGE DATA DEVICE NAME PACKAGE NAME TYPE CODE WEIGHT MOLDING COMPOUND FLAMMABILITY RATING MOISTURE SENSITIVITY LEVEL SOLDERING CONDITIONS VBUS053CZ-HAF LLP75-7L UA 4.2 mg UL 94 V-0 MSL level 1 (according J-STD-020) 260 °C/10 s at terminals ABSOLUTE MAXIMUM RATINGS VBUS053CZ-HAF PARAMETER TEST CONDITIONS SYMBOL VALUE UNIT acc. IEC 61000-4-5; tP = 8/20 μs; single shot IPPM 3 A acc. IEC 61000-4-5; tP = 8/20 μs; single shot PPP Data line D+, D-, ID: Pin 1, 2 and 3 to ground (pin 7) Peak pulse current Peak pulse power ESD immunity Contact discharge acc. IEC 61000-4-2; 10 pulses Air discharge acc. IEC 61000-4-2; 10 pulses VESD 54 W ± 15 kV ± 15 kV VBUS: Pin 6 to ground (pin 7) Peak pulse current acc. IEC 61000-4-5; tP = 8/20 μs; single shot IPPM 3 A Peak pulse power acc. IEC 61000-4-5; tP = 8/20 μs; single shot PPP 156 W ESD immunity Operating temperature Storage temperature Rev. 1.5, 15-Jul-15 Contact discharge acc. IEC 61000-4-2; 10 pulses Air discharge acc. IEC 61000-4-2; 10 pulses Junction temperature ± 30 kV ± 30 kV TJ -40 to +125 °C TSTG -55 to +150 °C VESD Document Number: 85200 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS053CZ-HAF www.vishay.com Vishay Semiconductors ELECTRICAL CHARACTERISTICS VBUS053CZ-HAF All inputs (pin 1, 2, and 3) to ground (pin 7) PARAMETER Protection paths Reverse working voltage Reverse voltage Reverse current Forward voltage Reverse breakdown voltage Reverse clamping voltage Forward clamping voltage Line capacitance Line to line capacitance Line symmetry TEST CONDITIONS/REMARKS Number of line which can be protected Reverse stand-off voltage at IR = 0.1 μA at VR = 3.3 V at VR = 3.3 V; T = 65 °C at VR = VRWM = 5.5 V at IF = 15 mA at IR = 1 mA at IPP = 1 A; acc. IEC 61000-4-5 at IPP = 3 A; acc. IEC 61000-4-5 at IF = 3 A; acc. IEC 61000-4-5 Test pin at VR = 0 V; any other I/O pin at VR = 3.3 V; f = 1 MHz Among pins 1, 2 and 3 at VR = 0 V; f = 1 MHz Difference of the line capacitance SYMBOL Nchannel VRWM VR IR IR IR VF VBR VC VC VF MIN. 5.5 0.7 6.5 - TYP. 10 15 3.4 MAX. 3 5.5 0.02 0.085 0.1 1.2 10 12 18 4.1 UNIT lines V V μA μA μA V V V V V CD - 0.7 1 pF CD - 0.35 0.5 pF dCD - - 0.1 pF MIN. 28 0.6 32 - TYP. 0.75 37 42 31 MAX. 1 28 100 0.9 40 45 52 2.2 40 UNIT lines V V nA V V V V V pF Note • Ratings at 25 °C ambient temperature, unless otherwise specified ELECTRICAL CHARACTERISTICS VBUS (pin 6) to ground (pin 7) PARAMETER Protection paths Reverse working voltage Reverse voltage Reverse current Forward voltage Reverse breakdown voltage Reverse clamping voltage Forward clamping voltage Line capacitance TEST CONDITIONS/REMARKS Number of line which can be protected Reverse stand-off voltage at IR = 0.1 μA at VR = VRWM = 28 V at IF = 10 mA at IR = 1 mA at IPP = 1 A; acc. IEC 61000-4-5; T = 25 °C at IPP = 3 A; acc. IEC 61000-4-5; T = 25 °C at IF = 3 A; acc. IEC 61000-4-5 at VR = 0 V; f = 1 MHz SYMBOL Nchannel VRWM VR IR VF VBR VC VC VF CD Note • Ratings at 25 °C ambient temperature, unless otherwise specified APPLICATION NOTE The VBUS053CZ-HAF is intended as an ESD-protection and transient voltage suppressor for one USB-OTG port. The LLP75-7L package contains two separate dies which are mounted on a common ground plane (pin 7). The high-speed data lines D-, D+ and ID, are connected to any of the pins no. 1 to 3. As long as the signal voltage on the data lines is between the ground- and the 5 V working range, the low capacitance PN-diodes offer a very high isolation to ground and to the other data lines. But as soon as any transient signal like an ESD-signal, exceeds this working range of 5 V in either the positive or negative direction, one of the PN-diodes gets intothe forward mode and clamps the transient either to ground or to the avalanche break through level. An extra avalanche diode (separate die) clamps the supply line voltage (VBUS at pin 6) above the 28 V working range to ground (pin 7). Due to the “two die construction” the VBUS line has a very high isolation to the data lines. In case of a destructive transient signal, i.e. coming from a charger, the data lines will not be influenced. (pinning top view) VBUS 6 5 4 nc. nc. 6 5 4 2 3 7 GND 7 1 D- 2 D+ 3 ID 1 21103 Remark: The input pins no. 1, 2 and 3 are symmetrical. Each of the data signals D-, D+ and ID can be connected to pin 1, 2 or 3. Rev. 1.5, 15-Jul-15 Document Number: 85200 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS053CZ-HAF www.vishay.com Vishay Semiconductors TYPICAL CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) 120 % 0.8 f = 1 MHz, one I/O pin at 3.3 V Rise time = 0.7 ns to 1 ns 0.7 Discharge Current IESD 100 % 0.6 80 % CD (pF) 0.5 60 % 53 % 0.4 Pin 1, 2 or 3 to pin 7 0.3 40 % 0.2 27 % 20 % 0.1 0 0% -10 0 10 20 30 40 50 60 70 80 90 100 0 1 2 22080 Time (ns) 20557 Fig. 1 - ESD Discharge Current Wave Form acc. IEC 61000-4-2 (330 /150 pF) 3 4 VR (V) Fig. 4 - Typical Capacitance CD vs. Reverse Voltage VR 100 8 µs to 100 % 100 % 10 80 % Pin 6 to pin 7 1 IF (mA) IPPM 60 % 20 µs to 50 % Pin 1, 2 or 3 to pin 7 40 % 0.1 20 % 0.01 0% 0 10 20 30 0.001 0.5 40 Time (µs) 20548 Fig. 2 - 8/20 μs Peak Pulse Current Wave Form acc. IEC 61000-4-5 35 30 0.9 1.0 1.1 Pin 6 to pin 7 30 VR (V) 25 CD (pF) 0.8 VF (V) 40 Pin 6 to pin 7 f = 1 MHz 20 15 25 20 15 10 Pin 1, 2 or 3 to pin 7 10 5 5 0 0.01 0 0 5 10 15 20 25 VR (V) Fig. 3 - Typical Capacitance CD vs. Reverse Voltage VR Rev. 1.5, 15-Jul-15 0.7 Fig. 5 - Typical Forward Current IF vs. Forward Voltage VF 35 22408 0.6 22409 22410 0.1 1 10 100 1000 10 000 IR (µA) Fig. 6 - Typical Reverse Voltage VR vs.Reverse Current IR Document Number: 85200 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS053CZ-HAF www.vishay.com Vishay Semiconductors 18 50 Measured acc. IEC 61000-4-5 (8/20 µs - wave form) 40 16 14 30 Pin 1, 2 or 3 to pin 7 20 VC-ESD (V) VC (V) 12 10 VF 8 6 Pin 7 to pin 1, 2 or 3 Pin 6 to pin 7 0 - 10 - 20 - 40 2 - 50 0 0 1 2 3 - 60 - 10 0 4 IPP (A) 22083 22413 Fig. 7 - Typical Peak Clamping Voltage VC vs. Peak Pulse Current IPP 10 20 30 40 50 60 70 80 90 t (ns) Fig. 10 - Typical Clamping Performance at - 8 kV Contact Discharge (acc. IEC 61000-4-2) 50 140 Measured acc. IEC 61000-4-5 (8/20 µs - wave form) 45 40 120 80 VC-ESD (V) 30 25 VC 20 acc. IEC 61000-4-2 + 8 kV contact discharge 100 Pin 6 to pin 7 35 VC (V) 10 - 30 4 60 40 Pin 1, 2 or 3 to pin 7 20 15 0 10 5 - 20 Pin 7 to pin 6 0 1 2 3 4 IPP (A) 22411 Fig. 8 - Typical Peak Clamping Voltage VC vs. Peak Pulse Current IPP 100 80 - 40 - 10 0 5 22414 10 20 30 40 50 60 70 80 90 t (ns) Fig. 11 - Typical Clamping Performance at + 8 kV Contact Discharge (acc. IEC 61000-4-2) 40 acc. IEC 61000-4-2 + 8 kV contact discharge 20 acc. IEC 61000-4-2 - 8 kV contact discharge 0 60 Pin 6 to pin 7 40 20 VC-ESD (V) 0 VC-ESD (V) acc. IEC 61000-4-2 - 8 kV contact discharge - 20 - 40 Pin 1, 2 or 3 to pin 7 - 60 - 80 - 100 0 - 20 - 10 0 22412 - 120 10 20 30 40 50 60 70 80 90 t (ns) Fig. 9 - Typical Clamping Performance at + 8 kV Contact Discharge (acc. IEC 61000-4-2) Rev. 1.5, 15-Jul-15 - 140 - 10 0 22415 10 20 30 40 50 60 70 80 90 t (ns) Fig. 12 - Typical Clamping Performance at - 8 kV Contact Discharge (acc. IEC 61000-4-2) Document Number: 85200 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS053CZ-HAF www.vishay.com Vishay Semiconductors 60 80 acc. IEC 61000-4-2 contact discharge 50 40 30 Pin 1, 2 or 3 to pin 7 40 VC-ESD (V) VC-ESD (V) 20 10 VC-ESD 0 acc. IEC 61000-4-2 contact discharge 60 Pin 6 to pin 7 20 VC-ESD 0 - 10 t = 30 ns t = 30 ns - 20 - 20 - 30 - 40 - 40 0 5 10 15 20 0 VESD (kV) 22416 5 10 Fig. 13 - Typical Clamping Voltage at after 30 ns of ESD Contact Discharge (acc. IEC 61000-4-2) 15 20 25 30 VESD (kV) 22417 Fig. 14 - Typical Clamping Voltage at after 30 ns of ESD Contact Discharge (acc. IEC 61000-4-2) 0.45 (0.018) 0.55 (0.022) 0.2 (0.008) 0.3 (0.012) 0.2 (0.008) 0.3 (0.012) 1 (0.039) 0.2 (0.008) 0.3 (0.012) Heat sink 0.95 (0.037) 1.05 (0.041) PACKAGE DIMENSIONS in millimeters (inches): LLP75-7L 0.5 (0.020) 0.6 (0.024) 0.6 (0.024) 0.54 (0.021) 1.65 (0.065) 1.55 (0.061) 0.05 (0.002) 0 (0.000) 0.15 (0.006) 0.25 (0.010) 1.65 (0.065) Pin 1 marking 1.55 (0.061) Foot print recommendation: 0.5 (0.020) 0.5 (0.020) 0.3 (0.012) 0.3 (0.012) Document no.:S8-V-3906.02-014 (4) Created - Date: 04. April 2006 0.15 (0.006) 1 (0.039) 1 (0.039) 0.5 (0.020) 0.25 (0.010) 0.15 (0.006) Solder resist mask Solder pad 0.5 (0.020) 20500 Rev. 1.5, 15-Jul-15 Document Number: 85200 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS053CZ-HAF www.vishay.com Vishay Semiconductors LLP75-7x S9 F5 Pad layout - view from top / seen at bottom side S8-V-3906.02-008a (4) 10.12.2009 Rev. 1.5, 15-Jul-15 Pin 1 - location Document Number: 85200 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. 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