AND9454/D Good Practice for the NCP1602 CSZCD Pin Design and PCB Layout NCP1602 combines the current sense (CS) and the core demagnetization detection (ZCD, zero crossing detection) signals into a single pin named CSZCD. In some noisy environment, a non-optimum choice of sensing resistors combined with a dense PCB layout can lead to a unstable operation of 1602. This application note describes good practices for designing the circuitry around the NCP1602 CSZCD pin, including choice of component values and PCB layout. www.onsemi.com APPLICATION NOTE Safety: If one resistor gets shorted, the drain voltage which is high (e.g., 400 V) is not directly applied to CSZCD pin and no damage will be observed. Drain Connection for CSZCD Pin (Sensitivity to PCB Parasitics) Reliability: If RCS1,a , RCS1,b and RCS1,c have the same resistance value, the power MOSFET drain voltage is divided by the resistors and each RCS1,i resistor has roughly one third of drain voltage across it, well under the max voltage rating of each resistor. When trying to reduce the no-switching standby consumption current by increasing (above 1 MW) the resistance (RCS1 + RCS2 ) of the CSZCD bridge connected between the drain and the source of the power MOSFET (see Figure 1), the sensitivity of the CSZCD pin to PCB parasitic capacitors is increased. In some case, it can lead to non-functionality caused for example by a constant false triggering of OCP (Over Current Protection) or OVP (Over Voltage Protection). This is due to the fact that the CSZCD voltage is distorted and the internal circuitry cannot work as intended. While recommendations for avoiding such CSZCD pin sensitivity are given in [1], this application note will focus only on optimizing the CSZCD pin operations. VDRAIN RCS1,c RCS1,b VDRAIN RCS1,a RCS0 DRV RCS2 RCS1 RCS0 DRV CSZCD VSOURCE CSZCD RSENSE RCS2 VSOURCE Figure 2. CSZCD Pin Circuitry Showing How RCS1 is Made RSENSE What are not shown in Figure 2 are the PCB parasitic capacitors Cpi and the CSZCD pin to GND parasitic capacitance CCSZCDpar which are shown in Figure 3. The parasitic capacitors Cp0 and Cp7 do not cause problems because Cp0 together with the resistance RSENSE create a very high frequency pole (well above the MHz range) and the same for VDRAIN output impedance and Cp7 . Figure 1. The CSZCD Connection without an Auxiliary Winding For safety and reliability reasons, the RCS1 resistor is generally made with three resistors in series (RCS1,a , RCS1,b and RCS1,c ) shown in Figure 2. © Semiconductor Components Industries, LLC, 2016 June, 2016 − Rev. 0 1 Publication Order Number: AND9454/D AND9454/D R CS2 w 20 kW On the contrary, when RCS1,a , RCS1,b and RCS1,c values are getting close to 1 MW, very small parasitic capacitance values like for example 159 fF (femto farad) can creates a pole at 1 MHz which is right in the range of the ringing frequency of power MOSFET drain voltage. As we want a distortion-free drain voltage image at the CSZCD pin, we are in trouble. There is an internal zero inside the controller for cancelling the effect of the pole made by RCS resistors and the CSZCD pin to grounds parasitic capacitor (mostly due to the TSOP6 package) CCSZCDpar. In case Cpi have a low effect (Cpi values low and/or RCSi values low), RCS values are determined by the following Equations 1, 2 and 3. R CS2 ) R CS1,a ) R CS1,b ) R CS1,c R CS2 ȱ ȧR Ȳ CS0 ) 1 (eq. 1) + 138 " 10% ȳ ȧ@ C ȴ 1 1 ) R CS2 R CS1,a)R CS1,b)R CS1,c CSZCDpar (eq. 2) (eq. 3) + 500 ns VDRAIN Cp7 Cp4 RCS1,c Cp3 RCS1,b Cp2 RCS1,a Cp1 DRV Cp6 Cp5 RCS0 CSZCD RCS2 CCSZCDpar VSOURCE Cp0 RSENSE Figure 3. CSZCD Pin External Circuitry Showing Some of the PCB Parasitic Capacitors Unfortunately, it is not possible to cancel the effects of MHz-range poles and zeroes created by the combination of PCB parasitic capacitances Cpi (there are even more Cpi than those shown in Figure 3, for example those coupling each node of the RCS resistor ladder and DRV signal, VIN signal, …) by a schematic trick, and the only way to avoid problems is to keep Cpi values as low as possible and/or avoid RCS1,a , RCS1,b and RCS1,c to have a value greater than 333-kW (RCS1,a + RCS1,b + RCS1,c lower than 1-MW limit). While application note [1] already contains information, it is good to remind the following. (RCS1 + RCS2 ) Lower than 1 MW Three RCS1 200-V SMD1206 resistors can be placed in series RCS1 = RCS1,a + RCS1,b + RCS1,c . (RCS1 + RCS2 ) Greater than 1 MW and Lower than 5.12 MW Bench experiments have shown that three SMD 200-V resistors of same value in series (RCS1 = RCS1,a + RCS1,b + RCS1,c ) lead to false fault tripping (e.g., OVP2 false triggering). It is advised to have one 500-V SMD high-value resistor RCS1,c on the drain side (e.g., 5.1 MW for The EVB) with two low value (e.g., 240 kW) 200-V SMD resistors in series (RCS1,a + RCS1,b ). This is to avoid having inter-resistor capacitance to GND and observe difficulties to discharge them before a tON cycle. Do Not Do This Using RCS1,a = RCS1,b = RCS1,c with RCS1 = RCS1,a + RCS1,b + RCS1,c if RCS1 is greater than 1 MW. www.onsemi.com 2 AND9454/D Showing Bad CSZCD Waveforms As said before, very low parasitic capacitances between the nodes of the CSZCD divider bridge and GND creates a distorted CSZCD signal as shown in Figure 4 from both simulation and measurements. At the beginning of on-time, a voltage bump is added with can trigger OVS or OCP protections and during dead-time the parasitic capacitors are masking the image of drain voltage ringing which is well seen when the parasitic capacitances are low (see blue simulated curve on Figure 4) Type of RCS Resistors Bench experiments have proven SMD1206 & 0805 superiority, parasitic capacitance wise, over trough-hole resistors for RCS1 , RCS2 and RCS0 resistors. PCB Layout Considerations RCS0 must be placed as close as possible to CS/ZCD pin voltage and RCS1 and RCS2 as close as possible to RCS0 . PCB traces connecting the RCSi resistors must be kept as short as possible, the width of the trace being as small as possible (minimum parasitic capacitance). It is wise to keep a safety distance of 1 cm between the high value resistors of the CSZCD bridge and DRV, VIN, VDRAIN copper traces to avoid coupling. Measured V CSZCD C5,7,8,9 V CSZCD (V) V RSENSE V R1 (V) C5,7,8,9 DRV CSZCD 1 pF 0.5 pF 0.25 pF 0.1 pF 0.01 pF 12 ms tON Simulated Figure 4. Effect of Parasitic Capacitances on CSZCD Signal www.onsemi.com 3 AND9454/D References [1] Application Note AND9218/D “5 Key Steps to Designing a Compact, High-Efficiency PFC Stage Using the NCP1602” which can be downloaded at: http://www.onsemi.com/pub_link/Collateral/ AND9218−D.PDF ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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