ISL7457SRH ® Data Sheet March 16, 2009 Radiation Hardened, SEE Hardened, Non-Inverting, Quad CMOS Driver FN6874.0 Features • Electrically Screened to SMD 5962-08230 The ISL7457SRH is a radiation hardened, SEE hardened, high speed, non-inverting, quad CMOS driver. It is capable of running at clock rates up to 40MHz and features 2A typical peak drive capability and a nominal on-resistance of just 3.5Ω. The ISL7457SRH is ideal for driving highly capacitive loads, such as storage and vertical clocks in CCD applications. It is also well suited to level-shifting and clock-driving applications. Each output of the ISL7457SRH can be switched to either the high (VH) or low (VL) supply pins, depending on the related input pin. The inputs are compatible with both 3.3V and 5V CMOS logic. The output enable (OE) pin can be used to put the outputs into a high-impedance state. This is especially useful in CCD applications, where the driver should be disabled during power down. • QML Qualified per MIL-PRF-38535 Requirements • Full Mil-temp Range Operation . . . . TA = -55°C to +125°C • Radiation Hardness - TID [50-300 rad(Si)/s] . . . . . . . . . . . . . . . 10krad(Si) min • SEE Hardness - LET (SEL and SEB Immunity) . . . . 40MeV/mg/cm2 min - LET [SET = ΔVOUT < 15V, Δt < 500ns] 40MeV/mg/cm2 min • 4 Channels • Clocking Speeds up to 40MHz • 11ns/12ns Typical tR/tF with 1nF Load (15V bias) • 1ns Typical Rise and Fall Time Match (15V bias) • 1.5ns Typical Prop Delay Match (15V bias) The ISL7457SRH also features very fast rise and fall times which are typically matched to within 1ns. The propagation delay is also matched between rising and falling edges to typically within 1.5ns. The ISL7457SRH is available in a 16 lead ceramic flatpack package and specified for operation over the full -55°C to +125°C ambient temperature range. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. • Low Quiescent Current - < 1mA Typical • Fast Output Enable Function - 12ns Typical (15V bias) • Wide Output Voltage Range - 0V ≤ VL ≤ 8V - 2.5V ≤ VH ≤ 16.5V • 2A Typical Peak Drive Current (15V Bias) • 3.5Ω Typical On-Resistance (15V bias) • Input Level Shifters Detailed Electrical Specifications for these devices are contained in SMD 5962-08230. A “hot-link” is provided on our website for downloading. • 3.3V/5V CMOS Compatible Inputs Pinouts • CCD Drivers, Clock/line Drivers, Level-Shifters Applications ISL7457SRH 16 LD FLATPACK TOP VIEW INA 1 16 VS+ OE 2 15 OUTA INB 3 14 OUTB VL 4 13 NC GND 5 12 VH NC 6 11 OUTC INC 7 10 OUTD IND 8 9 1 VS- CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.. ISL7457SRH Ordering Information ORDERING NUMBER PART NUMBER TEMP. RANGE (°C) PACKAGE PKG. DWG. # 5962D0823001QXC ISL7457SRHQF -55 to +125 16 Ld Flatpack K16.A 5962D0823001VXC ISL7457SRHVF -55 to +125 16 Ld Flatpack K16.A 5962D0823001V9A ISL7457SRHVX -55 to +125 Die ISL7457SRHF/PROTO ISL7457SRHF/PROTO -55 to +125 16 Ld Flatpack ISL7457SRHX/SAMPLE ISL7457SRHX/SAMPLE -55 to +125 Die 2 K16.A FN6874.0 March 16, 2009 ISL7457SRH Electrical Specifications PARAMETER Typical values reflect VS+ = VH = 5V, VS- = VL= 0V, OE = VS+, TA = +25°C unless otherwise specified. DESCRIPTION CONDITION MIN TYP MAX UNIT INPUT VIH Logic “1” Input Voltage IIH Logic “1” Input Current VIL Logic “0” Input Voltage IIL Logic “0” Input Current CIN RIN 1.3 V 0.1 µA 1.23 V 0.1 µA Input Capacitance 5.7 pF Input Resistance 50 MΩ INx = VS+ INx = 0V OUTPUT ROH ON Resistance VH to OUTx INx = VS+, IOUTx = -100mA 8 Ω ROL ON Resistance VL to OUTx INx = 0V, IOUTx = +100mA 6 Ω ILEAK+ Positive Output Leakage Current INx = VS+, OE = 0V, OUTx = VS+ 0.1 µA ILEAK- Negative Output Leakage Current INx = VS+, OE = 0V, OUTx = VS- 0.1 µA POWER SUPPLY IS+ VS+ Supply Current INx = 0V and VS+ 0.2 mA IS- VS- Supply Current INx = 0V and VS+ -0.2 mA IH VH Supply Current INx = 0V and VS+ 0.1 µA IL VL Supply Current INx = 0V and VS+ 0.1 µA SWITCHING CHARACTERISTICS tR Rise Time INx = 0V to 4.5V step, CL = 1nF 23 ns tF Fall Time INx = 4.5V to 0V step, CL = 1nF 20 ns tRFΔ tR, tF Mismatch CL = 1nF 3 ns tD+ Turn-On Delay Time INx = 0V to 4.5V step, CL = 1nF 20 ns tD- Turn-Off Delay Time INx = 4.5V to 0V step, CL = 1nF 22 ns tDD tD+, tD- Mismatch CL = 1nF 2 ns tENABLE Enable Delay Time INx = VS+, OE = 0V to 4.5V step, RL = 1kΩ 21 ns tDISABLE Disable Delay Time INx = VS+, OE = 4.5V to 0V step, RL = 1kΩ 46 ns 3 FN6874.0 March 16, 2009 ISL7457SRH Electrical Specifications PARAMETER Typical values reflect VS+ = VH = 15V, VS- = VL= 0V, OE = VS+, TA = +25°C unless otherwise specified. DESCRIPTION CONDITION MIN TYP MAX UNIT INPUT VIH Logic “1” Input Voltage IIH Logic “1” Input Current VIL Logic “0” Input Voltage IIL Logic “0” Input Current CIN RIN 1.63 V 0.1 µA 1.4 V 0.1 µA Input Capacitance 5.7 pF Input Resistance 50 MΩ INx = VS+ INx = 0V OUTPUT ROH ON Resistance VH to OUTx INx = VS+, IOUTx = -100mA 3.5 Ω ROL ON Resistance VL to OUTx INx = 0V, IOUTx = +100mA 3 Ω ILEAK+ Positive Output Leakage Current INx = VS+, OE = 0V, OUTx = VS+ 0.1 µA ILEAK- Negative Output Leakage Current INx = VS+, OE = 0V, OUTx = VS- 0.1 µA POWER SUPPLY IS+ VS+ Supply Current INx = 0V and VS+ 0.8 mA IS- VS- Supply Current INx = 0V and VS+ -0.8 mA IH VH Supply Current INx = 0V and VS+ 0.1 µA IL VL Supply Current INx = 0V and VS+ 0.1 µA SWITCHING CHARACTERISTICS tR Rise Time INx = 0V to 5V step, CL = 1nF 11 ns tF Fall Time INx = 5V to 0V step, CL = 1nF 12 ns tRFΔ tR, tF Mismatch CL = 1nF 1 ns tD+ Turn-On Delay Time INx = 0V to 5V step, CL = 1nF 11.5 ns tD- Turn-Off Delay Time INx = 5V to 0V step, CL = 1nF 13 ns tDD tD+, tD- Mismatch CL = 1nF 1.5 ns tENABLE Enable Delay Time INx = VS+, OE = 0V to 5V step, RL = 1kΩ 12 ns tDISABLE Disable Delay Time INx = VS+, OE = 5V to 0V step, RL = 1kΩ 27 ns 4 FN6874.0 March 16, 2009 ISL7457SRH Typical Performance Curves (Pre-rad) 1.8 2.0 TA = +25°C HIGH LIMIT = 2.4V 1.6 HYSTERESIS 1.4 1.2 SUPPLY CURRENT (mA) INPUT VOLTAGE (V) TA = +25°C ALL INPUTS = 0V 1.6 1.2 0.8 0.4 ALL INPUTS = VS+ LOW LIMIT = 0.8V 0 1.0 5.0 7.0 10 12 5 15 7 FIGURE 1. SWITCH THRESHOLD vs SUPPLY VOLTAGE 15 FIGURE 2. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE 9 25 RISE/FALL TIME (ns) IOUT = 100mA TA = +25°C 8 “ON” RESISTANCE (Ω) 12 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) 7 6 VH TO OUT 5 VL TO OUT 4 tR 20 tF 15 10 CL = 1nF TA = +25°C 3 2 5 5 7 10 12 15 5 7 SUPPLY VOLTAGE (V) 10 12 15 SUPPLY VOLTAGE (V) FIGURE 3. “ON” RESISTANCE vs SUPPLY VOLTAGE FIGURE 4. RISE/FALL TIME vs SUPPLY VOLTAGE 16 25 PROPAGATION DELAY TIME (ns) CL = 1nF VS+ = 15V RISE/FALL TIME (ns) 10 14 12 tF 10 tR 8 6. -50 CL = 1nF TA = +25°C 20 tD- 15 tD+ 10 5.0 -25 0 25 50 75 100 125 TEMPERATURE (°C) FIGURE 5. RISE/FALL TIME vs TEMPERATURE 5 5 7 10 12 15 SUPPLY VOLTAGE (V) FIGURE 6. PROPAGATION DELAY TIME vs SUPPLY VOLTAGE FN6874.0 March 16, 2009 ISL7457SRH Typical Performance Curves (Pre-rad) (Continued) 16 140 CL = 1nF VS+ = 15V VS+ = 15V 120 TA = +25°C 14 RISE/FALL TIME (ns) PROPAGATION DELAY TIME (ns) 18 tD- 12 tD+ 10 8 6 -50 100 80 60 tF 40 tR 20 -25 0 50 25 75 100 0 100 125 TEMPERATURE (°C) 2.2k 4.7k 10k LOAD CAPACITANCE (pF) FIGURE 7. PROPAGATION DELAY TIME vs TEMPERATURE FIGURE 8. RISE/FALL TIME vs LOAD CAPACITANCE 50 12 VS+ = VH = 10V VS- = VL = 0V 10 f = 100kHz TA = +25°C 8 OPERATING FREQUENCY (MHz) SUPPLY CURRENT (mA) 1k 470 6 4 2 0 100 1k 10k LOAD CAPACITANCE (pF) FIGURE 9. SUPPLY CURRENT PER CHANNEL vs LOAD CAPACITANCE 6 VS+ = 15V 40 . 30 20 TJ = +125°C . . . . 10 0 0 200 . .. . TJ = +150°C 400 600 800 1000 LOAD CAPACITANCE (pF) FIGURE 10. OPERATING FREQUENCY vs LOAD CAPACITANCE DERATING CURVES FN6874.0 March 16, 2009 ISL7457SRH Timing Diagram TABLE 1. OPERATING VOLTAGE RANGE PIN MIN MAX VS+ to VS- 4.5V 16.5V VS- to GND 0V 0V VH VS- + 2.5V VS+ VL VS- VS+ VH to VL 0V 16.5V VL to VS- 0V 8V 5V INPUT 2.5V 0 OUTPUT 90% 10% t D+ tDtR tF Standard Test Configuration VS+ 0.1µF 4.7µF VS+ 10kΩ 1 INA 16 OUTA 1nF OE INB 2 15 3 14 OUTB 1nF VL 4.7µF 4 13 0.1µF 0.1µF 5 12 6 11 VH 4.7µF OUTC 1nF INC 7 10 IND 8 9 OUTD 1nF 7 FN6874.0 March 16, 2009 ISL7457SRH Pin Descriptions 16 LD FLATPACK NAME 1 INA FUNCTION EQUIVALENT CIRCUIT Input Channel A VS+ VS+ INx VS- VS- CIRCUIT 1 2 OE Output enable (Reference Circuit 1) 3 INB Input Channel B (Reference Circuit 1) 4 VL Low voltage input pin 5 GND 6, 13 NC No connection 7 INC Input Channel C (Reference Circuit 1) 8 IND Input Channel D (Reference Circuit 1) 9 VS- Negative supply voltage 10 OUTD Input logic ground Output Channel D VH VS+ OUTx VSVSVL CIRCUIT 2 11 OUTC Output Channel C (Reference Circuit 2) 12 VH 14 OUTB Output Channel B (Reference Circuit 2) 15 OUTA Output Channel A (Reference Circuit 2) 16 VS+ High voltage input pin Positive supply voltage Block Diagram OE VH VS+ INx GND LEVEL SHIFTER 3-STATE CONTROL OUTx VSVL 8 FN6874.0 March 16, 2009 ISL7457SRH Application Information Product Description The ISL7457SRH is a high performance, high speed quad CMOS driver. Each channel of the ISL7457SRH consists of a single P-channel high side driver and a single N-Channel low side driver. These 3.5Ω devices will pull the output (OUTx) to either the high or low voltage, on VH and VL respectively, depending on the input logic signal (INx). It should be noted that there is only one set of high and low voltage pins. A common output enable (OE) pin is available on the ISL7457SRH. When this pin is pulled low, it will put all outputs in a high impedance state. Supply Voltage Range and Input Compatibility The ISL7457SRH is designed to operate on nominal 5V to 15V supplies with ±10% tolerance. Table 1 on page 7 shows the specifications for the relationship between the VS+, VS-, VH, VL, and GND pins. The ISL7457SRH does not contain a true analog switch and therefore VL should always be less than VH. All input pins are compatible with both 3.3V and 5V CMOS signals. PCB Layout Guidelines Power Dissipation Calculation When switching at high speeds, or driving heavy loads, the ISL7457SRH drive capability is limited by the rise in die temperature brought about by internal power dissipation. For reliable operation die temperature must be kept below TJMAX (+150°C). Power dissipation may be calculated as shown in Equation 1: 4 PD = ( VS × IS ) + 2 2 × f) ∑ ( CINT × VS × f ) + ( CL × VOUT (EQ. 1) 1 where: PD is the power dissipated in the device. VS is the total power supply to the ISL7457SRH (from VS+ to VS-). IS is the quiescent supply current. CINT is the internal load capacitance (80pF max). f is the operating frequency. CL is the load capacitance. VOUT is the swing on the output (VH - VL). 1. A ground plane must be used, preferably located on layer #2 of the PCB. Junction Temperature Calculation 2. Connect the GND and VS- pins directly to the ground plane. Once the power dissipation for the application is determined, the maximum junction temperature can be calculated as shown in Equation 2: 2. The VS+, VH and VL pins should be bypassed directly to the ground plane using a low-ESR, 4.7µF solid tantalum capacitor in parallel with a 0.1µF ceramic capacitor. Locate all bypass capacitors as close as possible to the respective pins of the IC. 3. Keep all input and output connections to the IC as short as possible. 4. For high frequency operation above 1MHz, consider use of controlled impedance traces terminated into 50Ω on all inputs and outputs. T JMAX = T SMAX + ( Θ JC + Θ CS ) × P D (EQ. 2) where: TJMAX is the maximum operating junction temperature (150°C). TSMAX is the maximum operating sink temperature of the PCB. θJC is the thermal resistance, junction-to-case, of the package. θCS is the thermal resistance, case-to-sink, of the PCB. PD is the power dissipation calculated in Equation 1. PCB Thermal Management To minimize the case-to-sink thermal resistance, it is recommended that multiple vias be placed on the top layer of the PCB directly underneath the IC. The vias should be connected to the ground plane, which functions as a heatsink. A gap filler material (i.e. a Sil-Pad or thermally conductive epoxy) may be used to insure good thermal contact between the bottom of the IC and the vias. 9 FN6874.0 March 16, 2009 ISL7457SRH Die Characteristics Substrate: Type: Silicon Isolation: Junction DIE DIMENSIONS: 2390 µm x 2445 µm (94.1 mils x 96.3 mils) Thickness:13.0 mils ±0.5 mil Backside Finish: Silicon INTERFACE MATERIALS ASSEMBLY RELATED INFORMATION Glassivation Substrate Potential: Type: PSG and Silicon Nitride Thickness: 0.5 µm ± 0.05 µm to 0.7 µm +/- 0.05 µm Vs- Top Metallization ADDITIONAL INFORMATION Type: AlCuSi (1%/0.5%) Thickness: 1.0 µm +/-0.1 µm Worst Case Current Density: < 2 x 105 A/cm2 (See Figure 10) Transistor Count: 1142 Metallization Mask Layout ISL7457SRH INA VS+ OE OUTA INB OUTB VL VH GND OUTC DELAY OUTD INC IND 10 VS- FN6874.0 March 16, 2009 ISL7457SRH Layout Characteristics Step and Repeat: 2390 µm x 2445 µm The DELAY pad is not bonded. TABLE 1. LAYOUT X-Y COORDINATES X (µm) Y (µm) DX (µm) DY (µm) PROBES PER PAD IND 675 190 140 140 1 VS- 995 190 140 140 1 OUTD 2118 490 122 133 1 OUTC 2118 795 122 133 1 VH 2118 1039 122 345 2 2118 1211 OUTB 2118 1554 122 133 1 OUTA 2118 1861 122 133 1 VS+ 1015 2140 140 140 1 INA 608 2140 140 140 1 OE 213 1993 140 140 1 INB 213 1673 140 140 1 VL 213 1331 140 345 2 213 1159 GND 213 864 140 140 1 DELAY 213 585 140 140 0 INC 213 213 140 140 1 PAD NAME All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN6874.0 March 16, 2009 ISL7457SRH Ceramic Metal Seal Flatpack Packages (Flatpack) K16.A MIL-STD-1835 CDFP4-F16 (F-5A, CONFIGURATION B) A e 16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE A INCHES PIN NO. 1 ID AREA SYMBOL -A- D -B- S1 b MIN MILLIMETERS MAX MIN MAX NOTES A 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - D - 0.440 - 11.18 3 E1 0.004 M H A-B S Q D S 0.036 M H A-B S D S C E -D- A -C- -HL E2 E3 SEATING AND BASE PLANE c1 L E3 (c) b1 M 0.245 0.285 6.22 7.24 - - 0.315 - 8.00 3 E2 0.130 - 3.30 - - E3 0.030 - 0.76 - 7 2 e LEAD FINISH BASE METAL E E1 M (b) SECTION A-A 0.050 BSC 1.27 BSC - k 0.008 0.015 0.20 0.38 L 0.250 0.370 6.35 9.40 - Q 0.026 0.045 0.66 1.14 8 S1 0.005 - 0.13 - 6 M - 0.0015 - 0.04 - N 16 16 Rev. 1 2-20-95 NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH 12 FN6874.0 March 16, 2009