® Pb October 25, 2005 NOT Ro a nd e e r -F om HS C HI1176 nt plia N FO R D E END I1179 OMM See H C E R EW D NS ESIG 8-Bit, 20 MSPS, Flash A/D Converter Features Description • Resolution ±0.5 LSB (DNL) . . . . . . . . . . . . . . . . . . . 8-Bit The HI1176 is an 8-bit, CMOS analog-to-digital converter for video use that features a sync clamp function. The adoption of a 2-step parallel method realizes low power consumption and a maximum conversion speed of 20 MSPS. For higher sampling rates, refer to the pin-for-pin compatible HI1179 data sheet, document number 3666. •[ /Title Maximum Sampling Frequency . . . . . . . . . . . 20 MSPS (HI1176) (8-Bit, 20 MSPS, A/D Converter) •/Subject Low Power Consumption at Flash 20 MSPS (Typ) (Reference /Author () Current Excluded) . . . . . . . . . . . . . . . 60mW (Harris •/Keywords Built-In Sync ClampSemiconductor, Function Video, Image Scanner, PC Video capture, Set top box, Clamp, Internal Ref• Built-In Monostable Multivibrator for Clamp Pulse Applications erence) Generation • Video Digitizing •/Creator Built-In () Sync Pulse Polarity Selection Function • Image Scanners /DOCINFO pdfmark • Clamp Pulse Direct Input Possible • Low Cost High Speed Data Acquisition Systems •[ /PageMode Built-In Clamp ON/OFF Function /UseOutlines • Multimedia •/DOCVIEW Built-In Reference Voltage Self Bias Circuit pdfmark Ordering Information • Input CMOS Compatible PART NUMBER • Three-State TTL Compatible Output TEMP. RANGE (oC) PACKAGE PKG. NO. 32 Ld MQFP Q32.7x7-S • Single +5V Power Supply • Low Input Capacitance (Typ) . . . . . . . . . . . . . . . . 11pF • Reference Impedance (Typ) . . . . . . . . . . . . . . . . . 300Ω HI1176JCQ -40 to 85 HI1176-EV 25 Evaluation Board • Direct Replacement for the Sony CXD1176 Pinout VRBS VREF CCP DVSS CLE OE DVSS NC HI1176 (MQFP) TOP VIEW 3 22 AVSS D3 4 21 VIN D4 5 20 AVDD D5 6 19 AVDD D6 7 18 VRT (MSB) D7 8 17 9 10 11 12 13 14 15 16 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1998, 2005. All Rights Reserved 1 All other trademarks mentioned are the property of their respective owners. VRB VRTS AVDD PW AVSS D2 SYNC 23 SEL 2 CLK D1 DVDD 32 31 30 29 28 27 26 25 24 NC 1 DVDD (LSB) D0 FN3582.6 HI1176 Functional Block Diagram 28 OE 30 25 VRBS DVSS REFERENCE SUPPLY DVSS 31 D0 (LSB) 24 VRB 1 D1 2 D2 3 D3 4 D4 5 D5 6 D6 7 D7 (MSB) 8 23 AVSS LOWER ENCODER (4-BIT) LOWER DATA LATCHES LOWER SAMPLING COMPARATOR (4-BIT) 22 AVSS 21 VIN LOWER ENCODER (4-BIT) LOWER SAMPLING COMPARATOR (4-BIT) UPPER ENCODER (4-BIT) UPPER SAMPLING COMPARATOR (4-BIT) 20 AVDD 19 AVDD 18 VRT UPPER DATA LATCHES 17 VRTS 16 AVDD DVDD 10 DVDD 11 CLOCK GENERATOR CLK 12 NC - 9 + NC 32 15 PW 14 SYNC M•M 29 27 13 SEL 26 CLE CCP VREF Typical Application Schematic WHEN CLAMP IS NOT USED (SELF BIAS USED) +5V (DIGITAL) HCO4 0.1µF CLOCK IN +5V (ANALOG) VIDEO IN 0.01µF 75Ω 0.1µF 10pF 0.01µF 16 15 14 13 12 11 10 9 8 17 D7 18 7 D6 19 6 D5 20 5 D4 21 4 D3 22 3 D2 23 2 D1 1 24 25 26 27 28 29 30 31 32 D0 GND (ANALOG) GND (DIGITAL) +5V (DIGITAL) 2 HI1176 Absolute Maximum Ratings Thermal Information Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Reference Voltage, VRT , VRB . . . . . . . . . VDD + 0.5V to VSS - 0.5V Analog Input Voltage, VIN . . . . . . . . . . . . VDD + 0.5V to VSS - 0.5V Digital Input Voltage, CLK . . . . . . . . . . . . VDD + 0.5V to VSS - 0.5V Digital Output Voltage, VOH , VOL . . . . . . VDD + 0.5V to VSS - 0.5V Thermal Resistance (Typical, Note 1) θJA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC (Lead Tips Only) Operating Conditions (Note 1) Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC Supply Voltage AVDD , AVSS , DVDD , DVSS . . . . . . . . . . . . . . . +4.75V to +5.25V |DGND-AGND| . . . . . . . . . . . . . . . . . . . . . . . . . . . .0mV to 100mV Reference Input Voltage VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V and Above VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8V and Below Analog Input Voltage, VIN . . . . . . . . VRB to VRT (1.8VP-P to AVDD) Clock Pulse Width tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min) tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications fC = 20 MSPS, VDD = +5V, VRB = 0.5V, VRT = 2.5V, TA = 25oC (Note 1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EOT -60 -40 -20 mV EOB +20 +40 +60 mV SYSTEM PERFORMANCE Offset Voltage Integral Non-Linearity, INL fC = 20 MSPS, VIN = 0.5V to 2.5V - ±0.5 ±1.3 LSB Differential Non-Linearity, DNL fC = 20 MSPS, VIN = 0.5V to 2.5V - ±0.3 ±0.5 LSB Signal to Noise Ratio, SINAD RMS Signal ---------------------------------------------------------------------------------------------------------------Signal-To-Noise + Distortion Ratio, SINAD fS = 20MHz, fIN = 1MHz - 46 - dB fS = 20MHz, fIN = 3.58MHz - 46 - dB Maximum Conversion Speed, fC VIN = 0.5V to 2.5V, fIN = 1kHz Ramp 20 35 - MSPS - - 0.5 MSPS - 1.0 - % Differential Phase Error, DP - 0.5 - Degree Aperture Jitter, tAJ - 30 - ps Sampling Delay, tDS - 4 - ns - 18 - MHz - 11 - pF DYNAMIC CHARACTERISTICS Minimum Conversion Speed Differential Gain Error, DG NTSC 40 IRE Mod Ramp, fC = 14.3 MSPS ANALOG INPUTS Analog Input Bandwidth (-1dB), BW Analog Input Capacitance, CIN VIN = 1.5V + 0.07VRMS 3 HI1176 Electrical Specifications fC = 20 MSPS, VDD = +5V, VRB = 0.5V, VRT = 2.5V, TA = 25oC (Note 1) (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Reference Pin Current, IREF 4.5 6.6 8.7 mA Reference Resistance (VRT to VRB), RREF 230 300 450 Ω 0.48 0.52 0.56 V 1.96 2.08 2.22 V VIH 4.0 - - V VIL - - 1.0 V VIH = VDD - - 5 µA VIL = 0V - - 5 µA VOH = VDD -0.5V -1.1 - - mA VOL = 0.4V 3.7 - - mA VOH = VDD - - 16 µA VOL = 0V - - 16 µA - 18 30 ns fC = 20 MSPS, NTSC Ramp Wave Input - 12 18 mA VIN = DC, PWS = 3µs VREF = 0.5V 0 +20 +40 mV VREF = 2.5V -50 -30 -10 mV 1.75 2.75 3.75 µs - 25 - ns REFERENCE INPUT INTERNAL VOLTAGE REFERENCES Self Bias VRB Short VRB and VRBS , Short VRT and VRTS VRT - VRB DIGITAL INPUTS Digital Input Voltage Digital Input Current IIH VDD = Max IIL DIGITAL OUTPUTS Digital Output Current IOH OE = VSS , VDD = Min IOL Digital Output Current IOZH OE = VDD , VDD = Max IOZL TIMING CHARACTERISTICS Output Data Delay, tDL POWER SUPPLY CHARACTERISTIC Supply Current, IDD CLAMP CHARACTERISTICS Clamp Offset Voltage, EOC Clamp Pulse Width (Sync Pin Input), tCPW C = 100pF, R = 130kΩ on Pin 15 Clamp Pulse Delay, tCPD NOTE: 1. Electrical specifications guaranteed only under the stated operating conditions. 4 HI1176 Timing Diagrams tPW1 tPW0 CLOCK ANALOG INPUT DATA OUTPUT : POINT FOR ANALOG SIGNAL SAMPLING N N+1 N-3 N+3 N-2 N-1 N-2 N+4 N N+1 tD = 18ns FIGURE 1. VI (1) VI (2) VI (3) VI (4) ANALOG INPUT EXTERNAL CLOCK UPPER COMPARATOR BLOCK S (1) S (1) DIGITAL OUTPUT S (3) C (3) MD (2) RV (1) H (1) H (0) C (0) C (1) LD (-2) MD (3) RV (3) S (3) H (3) H (2) C (2) LD (0) OUT (-1) FIGURE 2. 5 C (4) C (3) LD (1) S (2) OUT (-2) S (4) RV (2) LD (-1) LOWER DATA A LOWER DATA B C (2) MD (1) RV (0) LOWER REFERENCE VOLTAGE LOWER COMPARATOR BLOCK B S (2) MD (0) UPPER DATA LOWER COMPARATOR BLOCK A C (1) S (4) H (4) LD (2) OUT (0) OUT (1) HI1176 Typical Performance Curves 20 100 20 IDD (mA) IDD (mA) 15 15 10 50 10 5 4.5 4.0 5.0 5 5.5 0 5 10 POWER SUPPLY VOLTAGE (V) FIGURE 3. SUPPLY CURRENT vs SUPPLY VOLTAGE DIFFERENTIAL NON-LINEARITY (LSB) 1.4 15 20 25 1.0 0.6 0.2 0 2 4 6 8 10 INPUT FREQUENCY (MHz) FIGURE 5. DIFFERENTIAL NON-LINEARITY vs INPUT FREQUENCY Pin Descriptions PIN NUMBER SYMBOL 1-8 D0 to D7 EQUIVALENT CIRCUIT DESCRIPTION D0 (LSB) to D7 (MSB) Output. D1 10, 11 35 FIGURE 4. SUPPLY CURRENT AND POWER vs SAMPLING RATE TA = 25oC, VRT = 2.5V, VRB = 0.5V VDD = 5.0V, fS = 20 MSPS 0 30 SAMPLING RATE (MSPS) DVDD Digital +5V. 6 POWER DISSIPATION (mW) VPP = 5.0V, VRT = 2.5V, VRB = 0.5V TA = 25oC, VIN = 2VP-P HI1176 Pin Descriptions (Continued) PIN NUMBER SYMBOL 12 CLK EQUIVALENT CIRCUIT DESCRIPTION Clock Input. DVDD 12 DVSS 13 SEL When SEL is low, the falling edge of Pin 14 (sync) triggers the monostable. When SEL is high, the rising edge of Pin 14 (sync) triggers the monostable. DVDD 13 DVSS 14 SYNC Trigger pulse input to the monostable multivibrator. Trigger polarity can be controlled by Pin 13 (SEL). DVDD 14 DVSS 15 PW When a clamp pulse is generated by the monostable, the pulse width is determined by the external R and C. When the clamp pulse is directly input, it is input to Pin 15 (PW). DVDD 15 DVSS 16, 19, 20 AVDD 17 VRTS Analog +5V. When shorted with VRT , generates approx. +2.6V. AVDD 17 18 VRT 24 VRB Reference Voltage (Top). AVDD Reference Voltage (Bottom). 18 24 AVSS 7 HI1176 Pin Descriptions (Continued) PIN NUMBER SYMBOL 21 VIN EQUIVALENT CIRCUIT DESCRIPTION Analog Input. AVDD 21 AVSS 22, 23 AVSS 25 VRBS Analog Ground. AVSS When shorted with VRB , generates approx. +0.5V. 25 26 VREF Clamp Reference Voltage Input. AVDD 26 AVSS 27 CCP Integrates the voltage for clamp control. AVDD 27 AVSS 28, 31 DVSS 29 CLE Digital GND. When CLE is low, clamp function is activated. When CLE is high, clamp function is OFF and only the usual A/D converter function is active. By connecting CLE pin to DVDD via a several hundred Ω resistance, the clamp pulse can be tested. DVDD 29 DVSS 30 OE CLAMP PULSE When OE is low, data is valid. When OE is high, D0 to D7 pins are high impedance. DVDD 30 DVSS 8 HI1176 TABLE 1. A/D OUTPUT CODE DIGITAL OUTPUT CODE INPUT SIGNAL VOLTAGE STEP MSB VRT 255 1 • • • • • • • • VRB LSB 1 1 1 1 1 1 1 • • • • • • 128 1 0 0 0 0 0 0 0 127 0 1 1 1 1 1 1 1 0 0 0 • • • • • • 0 0 0 0 0 0 Detailed Description Reference Input The HI1176 is a 2-step A/D converter featuring a 4-bit upper comparator group and two lower comparator groups of 4 bits each. The reference voltage can obtained from the onboard bias generator or be supplied externally. This IC uses an offset canceling type comparator that operates synchronously with an external clock. The operating modes of the part are input sampling/autozero (S), hold (H), and compare (C). The range of the A/D is set by the voltage between VRT and VRB . The internal bias generator will set VRTS to 2.5V and VRBS to 0.5V. These can be used as the part reference by shorting VRT and VRTS and VRB to VRBS . The analog input range of the A/D will now be from 0.5V to 2.5V. If a VRB below +0.5V is used the linearity of the part will be degraded. The operation of the part is illustrated in Figure 2. A reference voltage that is between VRT -VRB is constantly applied to the upper 4-bit comparator group. VI(1) is sampled with the falling edge of the first clock by the upper comparator block. The lower block A also samples VI(1) on the same edge. The upper comparator block finalizes comparison data MD(1) with the rising edge of the first clock. Simultaneously the reference supply generates a reference voltage RV(1) that corresponds to the upper results and applies it to the lower comparator block A. The lower comparator block finalizes comparison data LD(1) with the rising edge of the second clock. MD(1) and LD(1) are combined and output as OUT(1) with the rising edge of the third clock. There is a 2.5 cycle clock delay from the analog input sampling point to the corresponding digital output data. Notice how the lower comparator blocks A and B alternate generating the lower data in order to increase the overall A/D sampling rate. Bypass VRT and VRB to analog ground with a 0.1µF capacitor. Clamp Operation The HI1176 provides a clamp option that allows the user to clamp a portion of the analog input to a voltage set by the VREF pin. The clamp function is enabled by bringing CLE low. An internal monostable multivibrator is provided that can be used to generate the clamp pulses. The monostable pulse width is determined by the external R and C connected to the PW pin. The trigger to the monostable is applied on the SYNC pin. The edge that triggers the monostable is determined by the SEL pin. When SEL is low the falling edge will trigger the monostable and when SEL is high the rising edge will trigger the monostable. Figure 6 shows the HI1176 configured for this mode of operation. The clamp pulse is latched by the ADC sampling clock. This is not necessary to the operation of the clamp function but if this is not done then a slight beat might be generated as vertical sag according to the relation between the sampling frequency and the clamp frequency. Power, Grounding, and Decoupling To reduce noise effects, separate the analog and digital grounds. Bypass both the digital and analog VDD pins to their respective grounds with a ceramic 0.1µF capacitor close to the pin. The HI1176 can also be configured to operate with an external clamp pulse. In this case a negative going pulse is input to the PW pin. VIN will now be clamped during the low period of the clamp pulse to the voltage on the VREF pin. Figure 7 shows the HI1176 configured for this mode of operation. Analog Input The input capacitance is small when compared with other flash type A/D converters. However, it is necessary to drive the input with an amplifier with sufficient bandwidth and drive capability. In order to prevent parasitic oscillation, it may be necessary to insert a resistor between the output of the amplifier and the A/D input. Figure 1 illustrates the operation of HI1176 when the clamp function is not used. 9 HI1176 Typical Application Circuits +5V (DIGITAL) HCO4 0.1µF CLOCK IN CK SYNC IN LATCH Q +5V (ANALOG) VIDEO IN 10µF 0.01µF 75Ω + 0.1µF 10pF 0.01µF 16 15 14 13 12 11 10 9 8 17 D7 18 7 D6 19 6 D5 20 5 D4 21 4 D3 22 3 D2 23 2 D1 1 24 25 26 27 28 29 30 31 32 D0 +5V (ANALOG) VREF 20K 0.01µF GND (ANALOG) GND (DIGITAL) FIGURE 6. PEDESTAL CLAMP IS EXECUTED BY SYNC PULSE (SELF BIAS USED) 10 HI1176 Typical Application Circuits (Continued) +5V (DIGITAL) HCO4 0.1µF CLOCK IN CK CLAMP PULSE IN LATCH Q +5V (ANALOG) VIDEO IN 10µF 0.01µF 75Ω + 0.1µF 10pF 0.01µF 16 15 14 13 12 11 10 9 8 17 D7 18 7 D6 19 6 D5 20 5 D4 21 4 D3 22 3 D2 23 2 D1 24 1 25 26 27 28 29 30 31 32 D0 +5V (ANALOG) VREF 20K 0.01µF GND (ANALOG) GND (DIGITAL) FIGURE 7. CLAMP PULSE IS DIRECTLY INPUT (SELF BIAS USED) Test Circuits +V S2 - S1 : ON IF A < B S2 : ON IF A > B S1 + -V A<B A>B COMPARATOR VIN DUT HI1176 8 “0” A8 B8 A1 A0 B1 B0 8 BUFFER “1” DVM 8 CLK (20MHz) 000 • • • 00 TO 111 • • • 10 CONTROLLER FIGURE 8. INTEGRAL AND DIFFERENTIAL NON-LINEARITY ERROR AND OFFSET VOLTAGE TEST CIRCUIT 11 HI1176 Test Circuits 2.6V ERROR RATE fC -1kHz SG HPF 0.6V 1 100 IRE 0 -40 SG (CW) VIN AMP 2 NTSC SIGNAL SOURCE 40 IRE MODULATION COUNTER HI20201 DUT HI1176 8 TTL 1 8 10-BIT D/A ECL 620 2 VECTOR SCOPE CLK 2.6V BURST DG DP -5.2V 620 0.6V SYNC -5.2V TTL fC ECL FIGURE 9. MAXIMUM OPERATIONAL SPEED AND DIFFERENTIAL GAIN AND PHASE ERROR TEST CIRCUIT 2.6V VDD VRT 2.6V IOL VIN 0.6V VDD VRT VIN VRB 0.6V CLK IOH VRB CLK VOL OE GND VOH OE + GND - + - FIGURE 10. DIGITAL OUTPUT CURRENT TEST CIRCUIT All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12