HI1866 S IGN ES WD Semiconductor E NOT RN D FO 6 E D EN I308 OMM See H C E R 6-Bit, 140 MSPS, Flash A/D Converter October 1998 Features Description • Ultra-High Speed Operation with Maximum Conversion Rate. . . . . . . . . . . . . . . . . . . . . . . 140 MSPS HI1866 is a 6-bit, high-speed, flash A/D converter capable of digitizing analog signals at the maximum rate of 140 MSPS. The digital input level is compatible with the ECL 100K/10KH/10K. [ /Title (HI1866) • Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . 7pF /Subject (6-Bit, 140 MSPS, Flash A/D Converter) • Wide Analog Input Bandwidth . . . . . . . . . . . . . 210MHz /Author () • Low Power Consumption . . . . . . . . . . . . . . . . . .325mW Ordering Information /Keywords (Harris Semiconductor, RGB, Video, Flat •Panel, Low Error Rate LCD) PART TEMP. NUMBER RANGE (oC) PACKAGE •/Creator Excellent Temperature Characteristics () •/DOCINFO 1:2 Demultiplexed Output (TTL Level) pdfmark HI1866JCQ -20 to 75 48 Ld MQFP PKG. NO. Q48.12x12-S • Direct Replacement for Sony CXA1866 [ /PageMode /UseOutlines Applications /DOCVIEW pdfmark • LCD Panels • Magnetic Recording (PRML) • Communications (QPSK, QAM) Pinout DVCC2 DGND2 DGND1 DVCC1 DGND3 DVEE DVCC2 DGND1 P1D3 P1D2 P1D1 30 29 P1D0 (LSB) 6 7 8 9 10 28 27 DGND3 P1D4 DGND3 DVCC2 INV CCLK NCCLK NC AVEE 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 NC NDCLK 33 32 31 VRT VRTS DCLK 4 5 NC DVCC2 NC P1D5 (MSB) VIN AGND DGND3 2 3 35 34 AGND P2D3 P2D4 P2D5 (MSB) 48 47 46 45 44 43 42 41 40 39 38 37 36 VRBS VRB P2D0 (LSB) P2D1 P2D2 1 AVEE DGND3 DGND2 DVEE DVCC2 DVCC1 HI1866 (MQFP) TOP VIEW CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1997 4-1 File Number 4108.2 HI1866 Functional Block Diagram VRBS VIN VRTS 15 19 22 VRTS 16 REFERENCE RESISTANCE CHAIN 21 VRT COMPARATOR 6-BIT LATCH 41 DVEE 6 INV 27 23 AVEE CCLK 26 CD CLATCH A NCCLK 25 20 AGND 46 DGND1 45 DGND2 42 DGND3 CLATCH B 6 47 DVCC1 6 48 DVCC2 DCLK 11 TTLOUT CD P2D2 P2D1 P2D0 (LSB) PD15 MSB) 4-2 P1D1 35 34 33 32 31 30 P1D0 (LSB) 2 P1D2 3 P1D3 4 P1D4 5 P2D3 6 P2D4 CD: CLOCK DRIVER 7 P2D5 (MSB) NDCLK 12 HI1866 Pin Descriptions PIN NO. SYMBOL I/O TYPICAL VOLTAGE LEVEL 21 VRT I 0V EQUIVALENT CIRCUIT DESCRIPTION Top reference voltage input (= 0). This is the top reference voltage supplied to the internal resistance chain. The external input can be set in accordance with the peak value on the plus side of the input analog signal amplitude. VRT VRTS COMPARATOR 1 22 VRTS O 0V 16 VRB I -2V VRT sense output. This is the voltage sense pin for VRT . COMPARATOR 2 COMPARATOR 31 COMPARATOR 32 15 19 VRBS O VIN I -2V COMPARATOR 63 VRBS Bottom reference voltage input (= -2V). This is the bottom reference voltage supplied to the internal resistance chain. The external input can be set in accordance with the peak value on the minus side of the input analog signal amplitude. VRB sense output. This is the voltage sense pin for VRB . VRB VRTS to VRBS Analog input. The input range is 2VP-P . AGND VIN AVEE 26 CCLK I ECL CCLK clock input. This is the conversion clock, and is an ECL level input. 25 NCCLK I ECL CCLK inversion clock input. This is an ECL level input. When left open, this input goes to the ECL threshold potential (-1.3V). Only CCLK input can be used for operation with the NCCLK input left open, but complementary input is recommended to attain fast and stable operation. DGND1 R R R 500 11 DCLK I ECL NCCLK (NDCLK) 12 NDCLK I R CCLK (DCLK) DCLK clock input. This is the 1:2 DMPX latch clock; input a clock of 1/2 frequency of CCLK. Data is output from DMPX port 1 and port 2 synchronously with the rising edge of this signal. This is an ECL level input. 500 ECL R R DVEE 4-3 1.3V DCLK inversion clock input. This is an ECL level input. When left open, this input goes to the ECL threshold potential (-1.3V). Only DCLK input can be used for operation with the NDCLK input left open, but complementary input is recommended to attain fast and stable operation. HI1866 Pin Descriptions (Continued) PIN NO. SYMBOL I/O TYPICAL VOLTAGE LEVEL 27 INV I ECL EQUIVALENT CIRCUIT DESCRIPTION DGND1 R 1.3V R 500 Digital output polarity inversion input. This is an ECL level input. This input inverts the polarity of the digital outputs P1D0 to P1D5, and P2D0 to P2D5. (Refer to the Output Code Table.) When left open, this signal is maintained at the low level. R INV R 1.3V DVEE 30 P1D0 31 P1D1 O TTL 32 P1D2 33 P1D3 34 P1D4 35 P1D5 2 P2D0 3 P2D1 4 P2D2 5 P2D3 6 P2D4 7 P2D5 38, 47 DVCC1 - +5.0V +5V power supply for TTL level internal circuit. 9, 28, 37, 43, 48 DVCC2 - +5.0V +5V power supply for TTL level output buffers (P1D0 to P2D5). 39, 46 DGND1 - 0V Ground for DVEE digital circuit. 40, 45 DGND2 - 0V Ground for DVCC1 digital circuit. 1, 8, 29, 36, 42 DGND3 - 0V Ground for DVCC2 digital circuit. 17, 20 AGND - 0V Ground for AVEE analog circuit. Used as the ground for the comparator input buffers, latches, etc. Separated from DGND. 41, 44 DVEE - -5.2V -5.2V power supply for digital circuit. Connected internally with AVEE . (Resistance is 4Ω to 6Ω.) 14, 23 AVEE - -5.2V -5.2V power supply for analog circuit. Connected internally with DVEE . (Resistance is 4Ω to 6Ω.) DVCC1 DVCC2 P1D0 TO D5 P2D0 TO D5 100K DGND2 These pins are for the 6 bits of digital output data for DMPX port 1. P2D5 is the MSB, and P2D0 is the LSB. These are TTL levels outputs. These pins are for the 6 bits of digital output data for DMPX port 2. P2D5 is the MSB, and P2D0 is the LSB. These are TTL level outputs. DGND3 4-4 HI1866 Absolute Maximum Ratings Thermal Information Supply Voltage (AVEE , DVEE) . . . . . . . . . . . . . . . . . . . . -7V to 0.5V (DVCC) (Note 2). . . . . . . . . . . . . . . . . . . .0.5V to 7.0V Reference Voltage (VRT , VRB) . . . . . . . . . . . . . . . . . . . -2.7V to 0.5V (VRT - VRB). . . . . . . . . . . . . . . . . . . . . . . . . 2.5V Analog Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . -2.7V to 0.5V Digital Input Voltage (DIN) (Note 3) . . . . . . . . . . . . . . . -4.0V to 0.5V ( CCLK–NCCLK , DCLK–NDCLK ) . . . . 2.5V Digital Output Current (ID0 to ID6) . . . . . . . . . . . . . -30mA to +30mA Storage Temperature (TSTG) . . . . . . . . . . . . . . . . . . -65oC to 150oC Ambient Operating Temperature (TA) . . . . . . . . . . . . . -20oC to 75oC Allowable Power Dissipation (PD). . . . . . . . . . . . . . . . . . . . . 750mW Thermal Resistance (Typical, Note 1) θJA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range (TSTG) . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (Lead Tips Only) Recommended Operating Conditions Supply Voltage MIN TYP AVEE, DVEE . . . . . . . . . . . . . . . . . . . . . . . -5.5V -5.2V AVEE - DVEE . . . . . . . . . . . . . . . . . . . . . . .-0.05V 0V AGND - DGND (Note 4) . . . . . . . . . . . . . - 0.05V 0V DVCC (Note 5). . . . . . . . . . . . . . . . . . . . . . 4.75V 5.0V Temperature Range (TA) . . . . . . . . . . . . . . . -20oC - MAX -4.75V 0.05V 0.05V 5.25V 75oC Reference Input Voltage VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Input Voltage (VIN) . . . . . . . . . . . . . Digital Input Voltage, DIN (H) . . . . . . . . . . . DIN (L) CCLK, NCCLK Frequency (fCCLK)(MHz) . . DCLK, NDCLK Frequency (fDCLK)(MHz) . . CCLK, NCCLK Duty (DCCLK)(%) . . . . . . . . DCLK, NDCLK Duty (DDCLK)(%) . . . . . . . . CCLK-DCLK Time Difference (tDCD)(ns). . . . MIN TYP MAX -0.1V 0V 0.1V -2.2V -2.0V -0.8V VRB To VRT -1.1V -1.5V 140 70 40 50 60 40 50 60 -tPWL + 2 0 tPWH + 1 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on an evaluation PC board in free air. 2. DVCC = DVCC1 , DVCC2 . 3. DIN = CCLK, NCCLK, DCLK, NDCLK, INV. 4. DGND = DGND1, DGND2, DGND3. 5. Refer to Timing Chart 1 for tPWL , tPWH . Electrical Specifications PARAMETER Resolution, n TA = 25oC, AVEE = DVEE = -5.2V, DVCC = 5V, VRT = 0V, VRB = -2V SYMBOL TEST CONDITIONS n MIN TYP MAX UNITS - 6 - bits DC CHARACTERISTICS Integral Linearity Error EIL fC = 140MHz - - ±0.2 LSB Differential Linearity Error EDL fC = 140MHz - - ±0.2 LSB - Guaranteed - - - 7 - pF No Missing Code ANALOG INPUT Analog Input Capacitance CIN VIN = -1V_0.7VRMS , DC Analog Input Resistance RIN -2V ≤ VIN ≤ 0V 200 - - KΩ Input Bias Current IIN -2V ≤ VIN ≤ 0V - - 110 µΑ REFERENCE INPUT Reference Resistance RREF - 225 - Ω Reference Resistance Current IREF - 9 - mA Offset Voltage VRT EOT 0 - 25 mV VRB EOB - - 25 mV VIH -1.13 - - V DIGITAL INPUT Logic High Level 4-5 HI1866 Electrical Specifications TA = 25oC, AVEE = DVEE = -5.2V, DVCC = 5V, VRT = 0V, VRB = -2V (Continued) PARAMETER SYMBOL Logic Low Level VIL Logic High Current IIH Logic Low Current IIL TEST CONDITIONS MIN TYP MAX UNITS - - -1.50 V VIH = -0.8V 0 - 50 µA VIL = -1.6V -50 - 50 µA - 3.5 - pF 140 - - MSPS Input Capacitance SWITCHING CHARACTERISTICS Error Rate 1E-9 TPS (Note 1) Maximum Conversion Frequency fC Aperture Jitter tAJ - 5.0 - ps Sampling Delay tDS - 1.0 - ns DIGITAL OUTPUT Logic High Level VOH IOUT = -2mA 2.7 - - V Logic Low Level VOL IOUT = 1mA - - 0.5 V Output Delay tDO ZL = 25pF 2.0 - 8.0 ns Output Rising Time tr ZL = 25pF, 0.5V to 2.4V - 1.2 - ns Output Falling Time tf ZL = 25pF, 0.5V to 2.4V - 1.2 - ns 210 - - MHz DYNAMIC CHARACTERISTICS Analog Amplitude Input Bandwidth FINB VIN = 2VP-P, Peak-to-Peak Value = 3dB Down Input Frequency S/N Ratio SNR1 SNR2 SNR3 fC = 140MHz, fIN = 1MHz fC = 140MHz, fIN = 35MHz fC = 140MHz, fIN = 70MHz - 36 34 32 - dB dB dB fC = 140MHz, Error > 4 LSB - -10-9 - TPS (Note 1) -60 20 -40 32 - mA mA - 325 - mW Error Rate POWER SUPPLY Supply Current ICC IEE Power Consumption PD DVCC = +5V AVEE = DVEE = -5.2V NOTE: 1. TPS: Times Per Sample Output Code Table DINV: 1 INV:0 VIN STEP 0V 0 000000 111111 1 000001 111110 • • • • • • 31 011111 100000 32 100000 011111 • • • • • • 62 111110 000001 63 111111 000000 -1V -2V NOTE: VRT = 0V, VRB = -2V. 4-6 D5 D0 D5 D0 HI1866 Timing Diagrams tDS VIN N N+1 N+2 N+3 N-1 N+4 tr DCCLK tf tPWH tPWL -1.1V -1.3V CCLK -1.5V -1.3V NCCLK tf tDCD DDCLK tr -1.1V DCLK -1.3V -1.5V -1.3V NDCLK tDO tDO P1D0-5 2.0V 1.0V P2D0-5 N-4 N-2 N N-1 N+1 2.0V 1.0V N-3 FIGURE 1. TIMING CHART 1 4-7 HI1866 Timing Diagrams (Continued) 6 6 VIN COMPARATOR 6-BIT LATCH CLATCHA 6 CLATCHB 6 CCLK P1D0 TO D5 TTLOUT DCLK 6 6 TTLOUT N-1 N N+1 N+3 N+2 N+4 P2D0 TO D5 N+5 VIN CCLK COMPARATOR (MASTER) N - 1● COMPARATOR (SLAVE) N N-1 N+1 N ● 6-BIT LATCH N-2 N-1 CLATCHA N-3 N-2 N-1 CLATCHB N-4 N-3 N-2 N+1 N ● N+2 ● N+3 N+2 N+4 N+3 N+5 N+4 N+5 N+1 N+2 N+3 N+4 N N+1 N+2 N+3 N-1 N N+1 N+2 DCLK TTLOUT (P2D0 TO D5) N-3 N-1 N+1 TTLOUT (P1D0 TO D5) N-4 N-2 N FIGURE 2. TIMING CHART 2 4-8 HI1866 Test Circuits SIGNAL SOURCE fCLK 4 -1kHz VIN 6 6 DUT HI1866 CCLK A LATCH B DCLK + COMPARATOR A>B LATCH 2VP-P SIN WAVE DATA 4 SIGNAL SOURCE fCLK 1/ 2 AMP FIGURE 3. MAXIMUM CONVERSION RATE TEST CIRCUIT +V S1 S1: NON WHEN A< B S2: ON WHEN A > B - + S2 -V (P1D0 TO D5) 6 VIN DUT HI1866 A<BA>B 6 SW COMPARATOR B6 A6 6 TO TO (P2D0 TO D5) B1 A1 B0 A0 “0” “1” BUFFER CCLK DCLK 6 DVM 000000 TO 111110 CONTROLLER FIGURE 4. INTEGRAL/DIFFERENTIAL LINEARITY ERROR TEST CIRCUIT 4-9 PULSE COUNTER HI1866 (Continued) CCLK NCCLK INV DVCC2 DGND3 P1D0 P1D1 P1D2 P1D3 P1D4 P1D5 DGND3 36 35 34 33 32 31 30 29 28 27 26 25 37 DVCC2 24 AVEE 23 38 DVCC1 VRTS 22 39 DGND1 VRT 21 40 DGND2 41 DVEE AGND 20 IIN VIN 19 A 42 DGND3 HI1866 43 DVCC2 -1.0V 18 44 DVEE AGND 17 45 DGND2 VRB 16 46 DGND1 -2.0V VRBS 15 47 DVCC1 AVEE 14 P2D2 P2D3 P2D4 P2D5 DGND3 DVCC2 2 3 4 5 6 7 8 9 10 11 12 NDCLK P2D1 1 DCLK P2D0 48 DVCC2 DGND3 Test Circuits ICC 13 IEE A A +5.0V -5.2V FIGURE 5. CURRENT CONSUMPTION/ANALOG INPUT BIAS TEST CIRCUIT 6 VIN SIGNAL SOURCE 1 ∅: VARIABLE LOGIC ANALYZER HI1866 6 CCLK SW DCLK FREQUENCY LOCK SIGNAL SOURCE 2 ECL BUFFER FIGURE 6. SAMPLING DELAY/APERTURE JITTER TEST CIRCUIT 4-10 1024 SAMPLES HI1866 Typical Performance Curves 25.0 -35 22.5 ICC -40 20.0 IEE -45 17.5 -50 -25 0 VEE = -5.2, VCC = 5V, IOUT = -2mA 15.0 75 50 25 3.6 DIGITAL OUTPUT LEVEL (V) VEE = -5.2V, VCC = +5V CURRENT CONSUMPTION (mA) CURRENT CONSUMPTION (mA) -30 3.5 3.4 3.3 3.2 3.1 -25 AMBIENT TEMPERATURE (oC) 0 25 50 75 AMBIENT TEMPERATURE (oC) FIGURE 7. CURRENT CONSUMPTION vs AMBIENT TEMPERATURE FIGURE 8. VOH vs AMBIENT TEMPERATURE 38 0.40 VEE = -5.2V, VCC = 5V, IOUT = 1mA 34 0.36 SNR (dB) DIGITAL OUTPUT LEVEL (V) 36 0.38 0.34 32 30 28 26 0.32 24 CCLK = 140MHz, DCLK = 70MHz 0.30 -25 22 0 25 50 75 1 AMBIENT TEMPERATURE (oC) FIGURE 9. VOL vs AMBIENT TEMPERATURE 2ND, 3RD HARMONIC DISTORTION (dB) -20 CCLK = 140MHz, DCLK = 70MHz EFFECTIVE BIT NUMBER (BITS) 100 FIGURE 10. SNR vs INPUT FREQUENCY 6.5 6.0 5.5 5.0 4.5 4.0 3.5 10 INPUT FREQUENCY (MHz) 1 10 -30 -40 3ND HARMONIC DISTORTION (dB) -50 -60 2ND HARMONIC DISTORTION (dB) -70 100 1 10 100 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) FIGURE 11. EFFECTIVE BIT NUMBER vs INPUT FREQUENCY CCLK = 140MHz, DCLK = 70MHz FIGURE 12. 2ND, 3RD HARMONIC DISTORTION vs INPUT FREQUENCY 4-11 HI1866 Notes on Operation The HI1186 is a high speed A/D converter with ECL level logic input and demultiplexed TT level output. Take notice of the following to ensure optimum performance from this IC. Power Supply and Grounding Grounding has a profound influence on converter performance. The higher the frequency is, the more important the way of grounding becomes. The ground pattern should be as large as possible. It is recommended to make the power supply and ground patterns wider at an inner layer using the multi-layer board. To prevent interference between the AGND and DGND patterns and between the AVEE and DVEE lines, make sure the respective patterns are separated. To prevent a DC offset in the power supply pattern, connect the AVEE and DVEE lines at one point each via a ferrite-bead filter. Shorting analog and digital ground patterns in one place immediately under the A/D converter improves A/D converter performance. Ground the power supply pins (AVEE , DVEE , DVCC) as close to each pin as possible with a 0.1µF or larger ceramic chip capacitor. (Connect the AVEE pin to the AGND pattern, DVEE to DGND, and DVCC to DGND.) Analog Input Make the connection between the VIN pin and the analog input source as short as possible. There is a slight offset voltage at reference voltage pins VRT and VRB . If it presents no problem in the application, the voltage can be applied directly. However, if the reference voltage is to be set precisely, apply it via a feedback circuit created, using the VRTS and VRBS pins. Make adequate bypass for high frequency noise at VRT and VRB . The VRT pin is normally connected to AGND on the board. Bypass the VRB pin to the AGND pattern with a 0.1µF or larger ceramic chip capacitor as short as possible. The 10µF tantalum capacitor connected to VRB in the Application Circuit is to stop oscillation in the reference voltage generation circuit. Digital Input Noise at the INV pin may cause misoperation of which the cause is extremely hard to identify. If it is okay for the set voltage level to be low only, leave the pin open. If a high level voltage has to be input, bypass the INV pin to DGND with an about 0.1µF ceramic chip capacitor as short as possible. It is recommended that high level input voltage is about -0.5V to 1.0V, and low level input voltage is about -1.6V to -2.5V. When inputting a high level voltage, avoid connecting directly to DGND. The HI1186 has input pins for two clocks: CCLK and DCLK. For CCLK, which is used for the internal comparator, input an ECL level clock with up to the maximum conversion frequency. For DCLK, which is used for the multiplex output, input an ECL level clock with a rate half that of CCLK. Take notice of the timing between CCLK and DCLK. It is recommended that differential signals be input to the clock input pins CCLK, NCCLK, DCLK and NDCLK. The A/D converter can be driven only by the clock input pins CCLK and DCLK, but there is a risk of unstable characteristics at maximum speeds. If the NCCLK and NDCLK pins are not used, bypass these pins to DGND with an about 0.1µF capacitor. In this time, about -1.3V voltage is generated at the NCCLK and NDCLK pins. However, this is too weak to be used as threshold voltage VBB ; it can not directly drive even one ECL input load. The clock duty cycle is designed for use at 50%. Any diversion from this percentage will have a slight effect on the maximum performance of the A/D converter, but there is no great need for adjustment. Digital Output P1D0 (LSB) to P1D5 (MSB), and P2D0 (LSB) to P2D5 (MSB) are demultiplex digital outputs (2 systems), and are output using the DCLK timing. The polarity of the output data can be inverted using the INV signal. 4-12 HI1866 Typical Application Circuit DGND DVCC1 DVCC2 DGND1 DGND2 DVEE DVCC2 DGND3 DVEE DGND2 DVCC1 DGND1 DVCC2 48 47 46 45 44 43 42 41 40 39 38 37 DGND3 36 1 DGND3 P1D5 35 P1D5 (TTL) P1D4 34 P1D4 (TTL) 4 P2D2 P1D3 33 P1D3 (TTL) (TTL) P2D3 5 P2D3 P1D2 32 P1D2 (TTL) (TTL) P2D4 6 P2D4 P1D1 31 P1D1 (TTL) P1D0 30 P1D0 (TTL) (TTL) P2D0 2 P2D0 (TTL) P2D1 3 P2D1 (TTL) P2D2 HI1866 (TTL) P2D5 7 P2D5 8 DGND3 DGND3 29 9 DVCC2 DVCC2 28 10 INV (ECL LEVEL) INV 27 11 DCLK CCLK 26 12 NCLK AVEE VRTS VRT AGND VIN AGND VRB VRBS AVEE NCCLK 25 13 14 15 16 17 18 19 20 21 22 23 24 -5.2V AGND 10µF TANTALUM CAPACITOR +5.0V ONE POINT SHORTING - + VRB VRTS -5.2V 1/ CLK 2 CAPACITORS, IF NOT SPECIFIED, ARE 0.1µF CERAMIC CHIP CAPACITORS. ANALOG INPUT ECL BUFFER CLK (ECL LEVEL) 4-13