CT ODU ODUCT R P PR TE 5 O LE I117 U TE O B S U B STI T M B E R H E S RT NU Data SIBLSheet S PA O P R SI L I N TE ® HI5675 March 2003 FN4711.1 8-Bit, 20MSPS, Flash A/D Converter Features The HI5675 is an 8-bit, analog-to-digital converter built in an advanced CMOS process. The low power, low differential gain and phase, high sampling rate, and single 5V supply make the HI5675 ideal for video and imaging applications. • Resolution . . . . . . . . . . . . . . . . . . . . 8-Bit ±0.3 LSB (DNL) The adoption of a 2-step flash architecture achieves low power consumption (60mW) at a maximum conversion speed of 20MSPS with only a 2.5 clock cycle data latency. The HI5675 also features digital output enable/disable and a built in voltage reference. The HI5675 can be configured to use the internal reference or an external reference if higher precision is required. Part Number Information PART NUMBER HI5675JCB TEMP. RANGE (oC) -40 to 85 • Maximum Sampling Frequency . . . . . . . . . . . . . . 20MSPS • Low Power Consumption . . . . . . . . . . . . . . . . . . . . .60mW (Reference Current Excluded) • Built-In Sample and Hold Circuit • Built-In Reference Voltage Self Bias Circuit • Three-State TTL Compatible Output • Single +5V Power Supply • Low Input Capacitance. . . . . . . . . . . . . . . . . . . 11pF (Typ) • Reference Impedance . . . . . . . . . . . . . . . . . . . 300Ω (Typ) • Low Cost PACKAGE 24 Ld SOIC PKG. NO. • Direct Replacement for TLC5510 and ADC1175 M24.2-S Applications • Video Digitizing Pinout • PC Video Capture HI5675 (SOIC) TOP VIEW • Image Scanners OE 1 24 DVSS • TV Set Top Boxes DVSS 2 23 VRB • Multimedia D0 (LSB) 3 22 VRBS • Personal Communication Systems (PCS) D1 4 21 AVSS D2 5 20 AVSS D3 6 19 VIN D4 7 18 AVDD D5 8 17 VRT D6 9 16 VRTS D7 (MSB) 10 15 AVDD DVDD 11 14 AVDD CLK 12 13 DVDD 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HI5675 Functional Block Diagram OE 1 DVSS 2 D0 (LSB) 3 D1 4 D2 5 D3 6 D4 7 D5 8 D6 24 DVSS REFERENCE VOLTAGE 23 VRB 22 LOWER ENCODER (4-BIT) LOWER DATA LATCHES 21 AVSS 20 AVSS LOWER ENCODER (4-BIT) LOWER COMPARATORS WITH S/H (4-BIT) UPPER ENCODER (4-BIT) UPPER COMPARATORS WITH S/H (4-BIT) 19 VIN 18 AVDD 17 VRT UPPER DATA LATCHES 9 LOWER COMPARATORS WITH S/H (4-BIT) D7 (MSB) 10 16 VRTS 2.6V (Typ) 15 AVDD DVDD 11 CLK 12 VRBS 0.6V (Typ) 14 AVDD 13 DVDD CLOCK GENERATOR Typical Application Schematic HC04 CA158A +5V +5V R4 + - C9 + 4.7µF R13 R11 R3 ICL8069 CLK CLOCK IN C10 0.1µF 13 12 14 11 15 10 D7 (MSB) 16 9 D6 17 8 D5 7 D4 19 6 D3 20 5 D2 21 4 D1 22 3 D0 (LSB) 23 2 24 1 R5 R12 + - CA158A C12 0.1µF C8 18 HA2544 VIN † + HI5675 R1 R2 C11 0.1µF C7 4.7µF + +5V † : Ceramic Chip Capacitor 0.1µF : Analog GND : Digital GND NOTE: It is necessary that AVDD and DVDD pins be driven from the same supply. The gain of analog input signal can be changed by adjusting the ratio of R2 to R1. 2 HI5675 Pin Descriptions PIN NUMBER SYMBOL 1 OE 2, 24 DVSS 3-10 D0 to D7 11, 13 DVDD 12 CLK Clock Input. 16 VRTS Shorted with VRT generates, +2.6V. 17 VRT Reference Voltage (Top). 23 VRB Reference Voltage (Bottom). 14, 15, 18 AVDD 19 VIN Analog Input. 20, 21 AVSS Analog GND. 22 VRBS Shorted with VRB generates +0.6V. DESCRIPTION When OE = Low, Data is valid. When OE = High, D0 to D7 pins high impedance. 3 Digital GND. D0 (LSB) to D7 (MSB) Output. Digital +5V. (Connect to AVDD to avoid Latchup). Analog +5V. Digital +5V. (Connect to DVDD to avoid Latchup). HI5675 Absolute Maximum Ratings Thermal Information Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V Reference Voltage, VRT, VRB . . . . . . . . . . . . . . . . . . . . VDD to VSS Analog Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS Digital Input Voltage, CLK . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS Digital Output Voltage, VOH, VOL . . . . . . . . . . . . . . . . . VDD to VSS Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range, TSTG . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions (Note 1) Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC Supply Voltage AVDD , AVSS , DVDD , DVSS . . . . . . . . . . . . . . . . +4.75V to +5.25V | DGND-AGND |. . . . . . . . . . . . . . . . . . . . . . . . . . . . 0mV to 100mV Reference Input Voltage VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V and Above VRT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8V and Below Analog Input Range, VIN . . . . . . . VRB to VRT (1.8VP-P to 2.8VP-P) Clock Pulse Width tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min) tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min) Die Characteristics Die Size: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.23 x 2.24mm CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. fC = 20MSPS, AVDD = DVDD = 5V, VRB = 0.5V, VRT = 2.5V, TA = 25oC (Note 1) Electrical Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EOT -60 -35 -10 mV EOB 0 +15 +45 mV SYSTEM PERFORMANCE Offset Voltage Integral Non-Linearity, INL fC = 20MSPS, VIN = 0.6V to 2.6V - ±0.5 ±1.3 LSB Differential Non-Linearity, DNL fC = 20MSPS, VIN = 0.6V to 2.6V - ±0.3 ±0.5 LSB Effective Number of Bits, ENOB fIN = 1MHz - 7.6 - Bits Spurious Free Dynamic Range fIN = 1MHz - 51 - dB Signal to Noise Ratio, SINAD fC = 20MHz, fIN = 1MHz - 46 - dB fC = 20MHz, fIN = 3.58MHz - 46 - dB 20 - - MSPS - - 0.5 MSPS - 1.0 - % Differential Phase Error, DP - 0.5 - Degree Aperture Jitter, tAJ - 30 - ps Sampling Delay, tDS - 4 - ns Data Latency, tLAT - - 2.5 Cycles - 18 - MHz - 11 - pF DYNAMIC CHARACTERISTICS RMS Signal = -----------------------------------------------------------------RMS Noise + Distortion Maximum Conversion Speed, fC VIN = 0.6V to 2.6V, fIN = 1kHz Ramp Minimum Conversion Speed Differential Gain Error, DG NTSC 40 IRE Mod Ramp, fC = 14.3MSPS ANALOG INPUTS Analog Input Bandwidth (-1dB), BW Analog Input Capacitance, CIN VIN = 1.5V + 0.07VRMS 4 HI5675 fC = 20MSPS, AVDD = DVDD = 5V, VRB = 0.5V, VRT = 2.5V, TA = 25oC (Note 1) (Continued) Electrical Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Reference Pin Current, IREF 4.5 6.6 8.7 mA Reference Resistance (VRT to VRB), RREF 230 300 450 Ω 0.60 0.64 0.68 V 1.96 2.09 2.21 V 2.25 2.39 2.53 V VIH 4.0 - - V VIL - - 1.0 V VIH = VDD - - 5 µA VIL = 0V - - 5 µA VOH = VDD -0.5V -1.1 - - mA VOL = 0.4V 3.7 - - mA VOH = VDD - 0.01 16 µA VOL = 0V - 0.01 16 µA - 18 30 ns - 12 17 mA REFERENCE INPUT INTERNAL VOLTAGE REFERENCE Self Bias Mode 1 VRB Short VRB and VRBS , Short VRT and VRTS VRT - VRB Self Bias Mode 2, VRT VRB = AGND, Short VRT and VRTS DIGITAL INPUTS Digital Input Voltage Digital Input Current IIH VDD = Max IIL DIGITAL OUTPUTS Digital Output Current IOH OE = VSS , VDD = Min IOL Digital Output Current IOZH OE = VDD , VDD = Max IOZL TIMING CHARACTERISTICS Output Data Delay, tDL POWER SUPPLY CHARACTERISTIC Supply Current, IDD fC = 20MSPS, NTSC Ramp Wave Input NOTE: 2. Electrical specifications guaranteed only under the stated operating conditions. Timing Diagrams tPW1 tPW0 CLOCK ANALOG INPUT N DATA OUTPUT N+1 N-3 : POINT FOR ANALOG SIGNAL SAMPLING N-2 tD = 18ns FIGURE 1. 5 N-2 N-1 N+3 N N+4 N+1 HI5675 Timing Diagrams (Continued) VI (1) VI (2) VI (3) VI (4) ANALOG INPUT EXTERNAL CLOCK UPPER COMPARATOR BLOCK S (1) S (1) DIGITAL OUTPUT C (3) MD (2) C (0) RV (3) H (3) C (3) LD (1) S (2) LD (-2) OUT (-2) C (4) MD (3) S (3) LD (-1) H (0) S (4) RV (2) C (1) H (2) C (2) LD (0) OUT (-1) FIGURE 2. 6 S (3) RV (1) H (1) LOWER DATA A LOWER DATA B C (2) MD (1) RV (0) LOWER REFERENCE VOLTAGE LOWER COMPARATOR BLOCK B S (2) MD (0) UPPER DATA LOWER COMPARATOR BLOCK A C (1) S (4) H (4) LD (2) OUT (0) OUT (1) HI5675 TABLE 1. A/D OUTPUT CODE TABLE DIGITAL OUTPUT CODE INPUT SIGNAL VOLTAGE STEP MSB D6 D5 D4 D3 D2 D1 LSB VRT 255 1 1 1 1 1 1 1 1 • • • • • • • • VRB • • • • • • 128 1 0 0 0 0 0 0 0 127 0 1 1 1 1 1 1 1 0 0 0 • • • • • • 0 0 0 0 0 0 Detailed Description The HI5675 is a 2-step A/D converter featuring a 4-bit upper comparator group and two lower comparator groups of 4 bits each. The reference voltage can be obtained from the onboard bias generator or be supplied externally. This IC uses an offset canceling type comparator that operates synchronously with an external clock. The operating modes of the part are input sampling (S), hold (H), and compare (C). Analog Input The operation of the part is illustrated in Figure 2. A reference voltage that is between VRT -VRB is constantly applied to the upper 4-bit comparator group. VI(1) is sampled with the falling edge of the first clock by the upper comparator block. The lower block A also samples VI(1) on the same edge. The upper comparator block finalizes comparison data MD(1) with the rising edge of the first clock. Simultaneously the reference supply generates a reference voltage RV(1) that corresponds to the upper results and applies it to the lower comparator block A. The lower comparator block finalizes comparison data LD(1) with the rising edge of the second clock. MD(1) and LD(1) are combined and output as OUT(1) with the rising edge of the third clock. There is a 2.5 cycle clock delay from the analog input sampling point to the corresponding digital output data. Notice how the lower comparator blocks A and B alternate generating the lower data in order to increase the overall A/D sampling rate. Reference Input Power, Grounding, and Decoupling To reduce noise effects, separate the analog and digital grounds. In order to avoid latchup at power up, it is necessary that AVDD and DVDD be driven from the same supply. Bypass both the digital and analog VDD pins to their respective grounds with a ceramic 0.1µF capacitor close to the pin. 7 The input capacitance is small when compared with other flash type A/D converters. However, it is necessary to drive the input with an amplifier with sufficient bandwidth and drive capability. In order to prevent parasitic oscillation, it may be necessary to insert a low value (i.e., 0.24Ω) resistor between the output of the amplifier and the A/D input. The range of the A/D is set by the voltage between VRT and VRB . The internal bias generator will set VRTS to 2.6V and VRBS to 0.6V. These can be used as the part reference by shorting VRT and VRTS and VRB to VRBS . The analog input range of the A/D will now be from 0.6V to 2.6V and is referred to as Self Bias Mode 1. Self Bias Mode 2 is where VRB is connected to AGND and VRT is shorted to VRTS . The analog input range will now be from 0V to 2.4V. HI5675 Test Circuits +V S1: ON IF A < B S2: ON IF A > B S2 S1 + A<B VIN 8 DUT HI5675 A>B COMPARATOR -V A8 TO A1 A0 “0” 8 B8 TO B1 B0 BUFFER “1” DVM CLK (20MHz) 000 • • • 00 TO 111 • • • 10 8 CONTROLLER FIGURE 3. INTEGRAL AND DIFFERENTIAL NON-LINEARITY ERROR AND OFFSET VOLTAGE TEST CIRCUIT 2.6V ERROR RATE fC -1kHz SG HPF 1 100 IRE 0 -40 SG (CW) VIN AMP 2 NTSC SIGNAL SOURCE 40 IRE MODULATION COUNTER HI20201 0.6V DUT HI5675 8 TTL 1 8 10-BIT D/A ECL 620 2 VECTOR SCOPE CLK 2.6V BURST DG DP -5.2V 620 0.6V SYNC TTL fC -5.2V ECL FIGURE 4. MAXIMUM OPERATIONAL SPEED AND DIFFERENTIAL GAIN AND PHASE ERROR TEST CIRCUIT VDD VRT 2.6V 2.6V IOL VIN VIN VRB 0.6V VDD VRT 0.6V VRB HI5675 HI5675 CLK OE + VOL GND - CLK OE + VOH GND FIGURE 5. DIGITAL OUTPUT CURRENT TEST CIRCUIT 8 IOH - HI5675 Static Performance Definitions Offset, full scale, and gain all use a measured value of the internal voltage reference to determine the ideal plus and minus full scale values. The results are all displayed in LSBs. Total Harmonic Distortion This is the ratio of the RMS sum of the first 5 harmonic components to the RMS value of the measured input signal. 2nd and 3rd Harmonic Distortion Offset Error (EOB) The first code transition should occur at a level 1/2 LSB above the bottom reference voltage. Offset is defined as the deviation of the actual code transition from this point. Note that this is adjustable to zero. Full Scale Error (EOT) The last code transition should occur for a analog input that is 11/2 LSBs below full scale. Full scale error is defined as the deviation of the actual code transition from this point. Differential Linearity Error (DNL) DNL is the worst case deviation of a code width from the ideal value of 1 LSB. The converter is guaranteed to have no missing codes. Integral Linearity Error (INL) INL is the worst case deviation of a code center from a best fit straight line calculated from the measured data. Dynamic Performance Definitions Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the HI5675. A low distortion sine wave is applied to the input, it is sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with a 1024 point FFT and analyzed to evaluate the dynamic performance of the A/D. The sine wave input to the part is -0.5dB down from fullscale for all these tests. The distortion numbers are quoted in dBc (decibels with respect to carrier) and DO NOT include any correction factors for normalizing to fullscale. Signal-to-Noise Ratio (SNR) SNR is the measured RMS signal to RMS noise at a specified input and sampling frequency. The noise is the RMS sum of all of the spectral components except the fundamental and the first five harmonics. Signal-to-Noise + Distortion Ratio (SINAD) SINAD is the measured RMS signal to RMS sum of all other spectral components below the Nyquist frequency excluding DC. Effective Number Of Bits (ENOB) The effective number of bits (ENOB) is derived from the SINAD data. ENOB is calculated from: ENOB = (SINAD - 1.76 + VCORR) / 6.02, where: VCORR = 0.5dB. 9 This is the ratio of the RMS value of the 2nd and 3rd harmonic component respectively to the RMS value of the measured input signal. Spurious Free Dynamic Range (SFDR) SFDR is the ratio of the fundamental RMS amplitude to the RMS amplitude of the next largest spur or spectral component. If the harmonics are buried in the noise floor it is the largest peak. Full Power Input Bandwidth Full power bandwidth is the frequency at which the amplitude of the digitally reconstructed output has decreased 3dB below the amplitude of the input sine wave. The input sine wave has a peak-to-peak amplitude equal to the reference voltage. The bandwidth given is measured at the specified sampling frequency. Timing Definitions Sampling Delay (tSD) Sampling delay is the time delay between the external sample command (the falling edge of the clock) and the time at which the signal is actually sampled. This delay is due to internal clock path propagation delays. Aperture Jitter (tAJ) This is the RMS variation in the sampling delay due to variation of internal clock path delays. Data Latency (tLAT) After the analog sample is taken, the data on the bus is available after 2.5 cycles of the clock. This is due to the architecture of the converter where the data has to ripple through the stages. This delay is specified as the data latency. After the data latency time, the data representing each succeeding sample is output at the following clock pulse. The digital data lags the analog input by 2.5 cycles. Output Data Delay (tD) Output Data Delay is the delay time from when the data is valid (rising clock edge) to when it shows up at the output bus. This is due to internal delays at the digital output. Small Outline Plastic Packages (SOIC) M24.2-S N INDEX AREA 1 2 24 LEAD SMALL OUTLINE PLASTIC PACKAGE (200 MIL) H INCHES E 3 MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.067 0.088 1.70 2.25 - A1 0.002 0.011 0.05 0.30 - B 0.014 0.021 0.35 0.55 - C 0.006 0.011 D 0.587 0.606 14.9 15.4 1 E 0.205 0.220 5.2 5.6 2 L SEATING PLANE D A e µα e A1 B C 0.15(0.006) 0.24 M 0.050 BSC 0.15 0.30 1.27 BSC - - H 0.296 0.326 7.5 8.3 - L 0.012 0.027 0.30 0.70 3 10o 0o N α 24 0o 24 4 10o Rev. 1 4/95 NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. 2. Dimension “E” does not include interlead flash or protrusions. 3. “L” is the length of terminal for soldering to a substrate. 4. “N” is the number of terminal positions. 5. Terminal numbers are shown for reference only. 6. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10