Semiconductor HI20206 S IGN ES WD NE August 1997 NOT R D FO 8 E D EN I117 OMM See H C E R Triple 8-Bit, 35 MSPS, RGB, 3-Channel D/A Converter Features Description • Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . Triple 8-Bit The HI20206 is a triple 8-bit, high-speed, bipolar D/A converter designed for video band use. It has three separate, 8-bit pixel inputs, one each for red, green, and blue video data. A single 5.0V power supply and pixel clock input is all that is required to make the device operational. A bias voltage generator is internal. For lower CMOS power consumption, refer to the HI1178. • Maximum Conversion Speed . . . . . . . . . . . . . . . 35MHz • RGB 3-Channel Input/Output • Differential Linearity Error . . . . . . . . . . . . . . . ±1/2 LSB • Digital Input Voltage . . . . . . . . . . . . . . . . . . . .TTL Level • Output Voltage Full-Scale . . . . . . . . . . . . . . 1VP-P (Typ) • Low Power Consumption . . . . . . . . . . . . . 360mW (Typ) Ordering Information • +5V Single Power Supply • Direct Replacement for Sony CX20206 PART NUMBER Applications HI20206JCP • Digital TV TEMP. RANGE (oC) -20 to 75 PACKAGE 42 Ld PDIP PKG. NO. E42.6B-S • Graphics Display • High Resolution Color Graphics • Video Reconstruction • Instrumentation • Image Processing • I/Q Modulation Pinout HI20206 (PDIP) TOP VIEW R5 1 42 R4 R6 2 41 R3 R7 3 40 R2 R8 4 39 R1 G1 5 38 NC G2 6 37 DGND G3 7 36 NC G4 8 35 ROUT G5 9 34 NC G6 10 33 GOUT G7 11 32 NC G8 12 31 BOUT B1 13 30 NC B2 14 29 AVCC B3 15 28 NC B4 16 27 VSET B5 17 26 VREF B6 18 25 AGND B7 19 24 NC B8 20 23 NC CLK 21 22 DVCC CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1997 10-1 File Number 4111.1 HI20206 Functional Block Diagram DGND 37 39 R2 40 R3 41 R4 42 R5 1 R6 2 R7 3 R8 4 G1 5 G2 6 G3 7 G4 8 G5 9 G6 10 G7 11 G8 12 B1 13 B2 14 B3 15 B4 16 B5 17 B6 18 B7 19 B8 20 33 ROUT 2 DECODER INPUT BUFFER (R) 3 3 6 2 6 DECODER INPUT BUFFER (G) CLOCK SYNCHRONIZING CIRCUIT R1 3 6 CURRENT SWITCH (R) R R R 2R R 2R R 2R R 2R R 2R R 33 GOUT 3 6 CURRENT SWITCH (G) R R R 2R R 2R R 2R R 2R R 2R R 3 31 BOUT DECODER 2 3 INPUT BUFFER (B) 6 6 CURRENT SWITCH (B) R R R 2R R 2R R 2R R 2R R 2R R 29 AVCC CLOCK BUFFER - + INTERNAL REFERENCE VOLTAGE SOURCE 21 22 23 26 27 CLK DVCC AGND VRET VREF 10-2 HI20206 Pin Descriptions PIN NO. SYMBOL 1 To 20 39 To 42 R1 To R8 G1 To G8 B1 To B8 EQUIVALENT CIRCUIT DESCRIPTION Digital Input pin. From pins 39 to 42 and from 1 to 4 are for RED. R1 is MSB and R8 is LSB. From pins 5 to 12 are for GREEN. G1 is MSB and G8 is LSB. From pins 13 to 20 are for BLUE. B1 is MSB and B8 is LSB. DVCC 22 39 - 42 1 ~ 20 37 DGND 21 CLK Clock Input pin. DVCC 22 21 37 DGND 22 DVCC Digital VCC . 23 24 NC No Connect. 25 AGND Analog GND. 26 VSET Bias Input pin. Normally, apply 0.8V. AVCC 29 54K 26 25 AGND 27 VREF Internal Reference Voltage Output pin 1.2V (Typ). A pulldown resistance is necessary externally. AVCC 29 27 20P 25 AGND 10-3 HI20206 Pin Descriptions (Continued) PIN NO. SYMBOL EQUIVALENT CIRCUIT DESCRIPTION 28 NC No Connect. 29 AVCC Analog VCC . 30 NC 31 BOUT Vacant pin but connect to AVCC (Note 1). Analog Output pin for BLUE. AVCC 29 RO 31 25 AGND 32 NC 33 GOUT Vacant pin but connect to AVCC (Note 1). Analog Output pin for GREEN. AVCC 29 RO 33 25 AGND 34 NC 35 ROUT Vacant pin but connect to AVCC (Note 1). Analog Output pin for RED. AVCC 29 RO 35 25 AGND 36 NC Vacant pin but connect to AVCC (Note 1). 37 DGND Digital GND. 38 NC No Connect. NOTE: 1. Pins 30, 32, 34 and 36 are vacant, but in order to reduce interference between the individual RGB outputs, connect them to AVCC . 10-4 HI20206 Absolute Maximum Ratings Thermal Information Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 7V Input Voltage (Digital) (VI , VCLK) . . . . . . . . . . . . . . . . . -0.3V to VCC Output Voltage (Analog) (VSET) . . . . . . . . . . . . . . VCC -2.1V to VCC Output Current Analog (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3mA to 10mA VREF Pin (IREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA to 0mA Supply Voltage Range (Typ) . . . . . . . . . . . . . . . . . . . . . . . 5V to 10V Thermal Resistance (Typical, Note 2) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Storage Temperature Range (TSTG) . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Recommended Operating Conditions Supply Voltage AVCC , DVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V AVCC-DVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to 0.2V AGND-DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V Digital Input Voltage H Level (VIH , VCLKH) . . . . . . . . . . . . . . . . . . . . . . . .2.0V to DVCC L Level (VIL , VCLKL) . . . . . . . . . . . . . . . . . . . . . . . . DGND to 0.8V VSET Input Voltage (VSET). . . . . . . . . . . . . . . . . . . . . . .0.7V to 0.9V VREF Pin Current (IREF). . . . . . . . . . . . . . . . . . . . . . -3mA to -0.4mA Clock Pulse Width tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15ns tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10ns Temperature Range (TOPR) . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = 25oC, AVCC = DVCC = 5V, AGND = DGND = 0V PARAMETER SYMBOL Resolution RSL Monotonic MNT Differential Linearity Error DLE Integral Linearity Error ILE Maximum Conversion Speed fMAX Full Scale Output Voltage (Note 3) VOFS RGB Output Voltage Full Scale Ratio (Note 4) FSR TEST CONDITIONS MIN TYP MAX UNITS - 8 - Bit - Guarantee - - VSET - AGND = 0.8V, RL > 10kΩ -0.5 - 0.5 LSB -0.4 - 0.4 % of Full Scale VSET - AGND = 0.8V, RL > 10kΩ, CL < 20pF 35 - - MHz 0.85 1.0 1.15 VP-P 0 4 8 % mV VOFFSET -40 -6 0 Output Resistance RO 270 340 420 Ω Dissipation Current ID 54 72 90 mA VI = DVCC - 1.2 20 µA - 0.6 10 µA VI = DGND -10 0 10 µA -10 0 10 µA Output Zero Offset Voltage Digital Data Input Current H Level L Level Upper 2 Bits IIH(U) Lower 6 Bits IIH(L) Upper 2 Bits IIL(U) Lower 6 Bits IIL(U) VSET - AGND = 0.8V, RL > 10kΩ, IREF = -400µA H Level ICLKH VCLK = DVCC - 3 30 µA L Level ICLKL VCLK = DGND -10 0 10 µA VSET Input Current ISET VSET - AGND = 0.8V -5 -0.3 0 µA Internal Reference Voltage VREF IREF = -400µA 1.08 1.20 1.32 V 12 - - ns Clock Input Current Set-Up Time tS Hold Time tH Crosstalk Among R, G and B CT D/A OUT: 1VP-P , RL>10kΩ, CL<20pF, fDATA = 7MHz, fCLK = 14MHz, See Figure 5 10-5 3 - - ns - -40 -33 dB HI20206 Electrical Specifications TA = 25oC, AVCC = DVCC = 5V, AGND = DGND = 0V (Continued) PARAMETER TEST CONDITIONS SYMBOL Glitch Energy GE Rise Time (Note 6) tr Fall Time (Note 6) tf Settling Time MIN TYP MAX UNITS - 160 - pV/s VSET - AGND = 0.8V, RL>10kΩ, fCLK = 1MHz, Digital Ramp Output, See Figure 6 (Note 5) VSET - AGND = 0.8V See Figure 4 tSET - 5.5 - ns - 5.0 - ns - 16 - ns NOTES: 3. AVCC - VO . 4. Maximum value among VO FS ( R ) VO FS ( G ) VO FS ( B ) 100 × ------------------------ – 1 , 100 × ------------------------ – 1 , or 100 × ------------------------ – 1 . VO FS ( G ) VO FS ( B ) VO FS ( R ) 5. Observe the glitch which is generated when the digital input varies as follows: 0 0 1 1 1 1 1 1 — 0 1 0 0 0 0 0 0 01 1 1 1 1 1 1 1 — 1 0 0 0 0 0 0 0 10 1 1 1 1 1 1 1 — 1 1 0 0 0 0 0 0 6. The time required for the D/A OUT to arrive at 90% of its final value from 10%. INPUT CORRESPONDING TABLE INPUT CODE MSB OUTPUT VOLTAGE LSB 11111111 VCC + VOFFSET • • • 10000000 VCC + VOFFSET -0.5V • • • • • • 00000000 VCC + VOFFSET -1.0V NOTE: In case the output voltage full scale is 1V (1 LSB = 3.92mV). Test Circuits 37 D1 ~ D8 DVCC D1 D2 39 - 42 1~4 8 (R) ROUT 35 D1 ~ D8 5 ~ 12 8 (G) GOUT 33 31 D1 ~ D8 13 ~ 20 D8 8 (B) 29 27 26 DGND BOUT V AVCC VREF VSET 3K + - V 25 33µF CLK TTL LEVEL 21 22 CLK HI20206 FIGURE 1. DIFFERENTIAL LINEARITY AND INTEGRAL LINEARITY TEST CIRCUITS 10-6 HI20206 Test Circuits (Continued) (MSB) OUT D1 D2 39 - 42 1~4 8 (R) 5 ~ 12 8 (G) (LSB) D8 ROUT 35 D1 ~ D8 8-BIT COUNTER (TTL OUTPUT) DIGITAL RAMP WAVEFORM GENERATION 37 D1 ~ D8 GOUT 33 BOUT 31 D1 ~ D8 OSCILLOSCOPE 13 ~ 20 RIN = 1MΩ CIN = 10pF BW = 20MHZ 29 8 (B) IN 26 VSET 12.5K + V 25 32µF 21 22 CLK HI20206 MCLK f = 35MHz TTL LEVEL RECTANGULAR WAVE AGND DGND AVCC DVCC CLK 2ns ~ 10ns D1 ~ D8 TIMING BETWEEN CLK AND DATA FIGURE 2. MAXIMUM CONVERSION RATE TEST CIRCUIT 37 D1 ~ D8 DVCC 39 - 42 1~4 8 (R) ROUT 35 5 ~ 12 8 (G) GOUT 33 BOUT V 31 13 ~ 20 29 8 (B) 27 26 AVCC VREF VSET + - 3K V 25 CLK TTL LEVEL 21 22 33µF CLK HI20206 FIGURE 3. OUTPUT VOLTAGE FULL SCALE PRECISION, RGB OUTPUT VOLTAGE FULL SCALE RATIO, AND OUTPUT ZERO OFFSET VOLTAGE TEST CIRCUITS 10-7 HI20206 (Continued) HI20206 1m COAXAL CABLE 37 D1 ~ D8 OBSERVE DATA WAVEFORM WITH AN OSCILLOSCOPE RIN = 1MΩ BW = 200MHz 8 (R) ( COAXAL CABLE (1m) 50 ROUT COAXAL CABLE 35 330 51 5 ~ 12 8 (G) 50 GOUT 330 51 COAXAL CABLE 50 330 51 COAXAL CABLE 50 33 31 8 (B) ( RIN = 1MΩ BW = 200MHz BOUT 13 ~ 20 1.2K OBSERVE WITH AN OSCILLOSCOPE 29 47 26 VSET 12.5K + CLK 21 - 25 (TTL) 33µF 1/ 22 2 1.2K COAXIAL CABLE (1m) DIVIDER f = 35MHz TTL LEVEL OBSERVE CLK WITH AN OSCILLOSCOPE RIN = 1MΩ BW = 200MHz ( 50 47 ( ( 39 - 42 1~4 PULSE GENERATOR 8082A (YHP) f = 35MHz TTL LEVEL RECTANGULAR WAVE AGND DGND AVCC DVCC PULSE GENERATOR 8082A (YHP) D DELAY ADJUSTMENT FIGURE 4. SET-UP TIME, HOLD TIME, AND RISE AND FALL TIME TEST CIRCUITS D1 ~ D8 39 - 42 1~4 8 (R) 37 50Ω EXIT ROUT 35 5 ~ 12 8 (G) GOUT f = 7MHz TTL LEVEL RECTANGULAR WAVE 33 13 ~ 20 1/ 8 (B) FET PROBE BOUT 31 P6202 (TEKTRONIX) 30, 32 34, 36 2 DIVIDER 29 26 AVCC VSET 12.5K + - MCLK f = 14MHz TTL LEVEL RECTANGULAR WAVE 25 33µF 21 CLK 22 HI20206 Measuring Method, in case the measuring crosstalk of G → R: 1. Apply the data to G only, and measure the power of the frequency component of the data at ROUT . 2. Apply the data to R only, and measure the power of the frequency component of the data at ROUT . 3. Take the difference of the above two powers; the unit is in dB. FIGURE 5. CROSSTALK AMONG R, G, AND B TEST CIRCUIT 10-8 SPECTRUM ANALYZER ( Test Circuits HI20206 Test Circuits (Continued) OUT (MSB) D1 D2 39 - 42 1~4 8 (R) ROUT 35 D1 ~ D8 8-BIT COUNTER (TTL OUTPUT) GOUT 5 ~ 12 33 8 (G) (LSB) D8 OSCILLOSCOPE RIN = 1MΩ CIN = 20PF BW = 5MHZ 29 8 (B) 100pF BOUT 31 D1 ~ D8 13 ~ 20 IN DIGITAL RAMP WAVEFORM GENERATION 37 D1 ~ D8 27 26 VREF VSET 3K + V - 25 33µF 22 21 CLK HI20206 MCLK f = 35MHz TTL LEVEL RECTANGULAR WAVE AGND DGND AVCC DVCC CLK 5ns ~ 300ns D1 ~ D8 TIMING OF CLK AND DATA FIGURE 6. GLITCH ENERGY TEST CIRCUIT 37 DATA (R) (TTL LEVEL) 39 - 42 1~4 8 ROUT - GOUT - BOUT - 35 (G) R† + 5 ~ 12 8 33 8 31 ROUT LPF GOUT LPF BOUT R† + 13 ~ 20 (B) LPF R† + BW = 16MHz 30, 32 34, 36 29 27 VREF AGND VSET 26 3K + - 25 CLK (TTL LEVEL) 33µF CLK 22 21 HI20206 † R is matching resistance for LPF. FIGURE 7. APPLIED CIRCUIT EXAMPLE 10-9 DGND AVCC DVCC HI20206 Timing Diagram t1 tPW1 t3 t12 t2 tPW0 t34 t4 CLK VTH = 1.5V tX tY DATA VTH = 1.4V tH tH tS tS 100% VTH: THRESHOLD LEVEL 0% 90% 10% 10% 90% D/A OUT 0% 100% tr tf NOTE: At the time t = tX , the data of individual bits are switched and thereafter, when the CLK becomes L → H at t = t2 , the D/A OUT is varied synchronous with it. That is, the D/A OUT is synchronous with the rise of the CLK. [In this case, fetching of the data is carried out at the fall of the CLK (at the time when t = t12)]. NOTE: At the time t = tY , the data of individual bits are switched and thereafter when the CLK becomes L → H at t = t4 , the D/A OUT is varied synchronous with it. That is, the D/A OUT is synchronous with the rise of the CLK. [In this case, fetching of the data is carried out at the fall of the CLK (at the time when t = t4)]. FIGURE 8. TIMING CHART Notes On Use (1) Setting of pin 26 (VSET) See R vs IREF of Figure 14. The calculation expression is as follows: R = VREF /IREF . The full scale of the D/A output voltage changes by applying voltage to pin 26 (VSET). When load is connected to pin 27 (VREF), DC voltage of 1.2V is issued and the said voltage is dropped to 0.8V by resistance division. 2. Adjust the volume so that the RGB output voltage full scale becomes 1V. (At this point, it becomes R1: R2 = 1:2). When the 0.8V is applied to pin 26 (VSET), the D/A output of 1VP-P can be obtained. 5.0 27 26 RESISTANCE R (kΩ) (Example of use): VREF R1 VSET R R2 25 1.0 0.3 AGND FIGURE 9. 0.1 0.1 (Adjustment Method) 1. The resistance R is determined in accordance with the recommended operating condition of IREF , (current flowing through resistance R). 10-10 0.2 1 PIN CURRENT IREF (mA) FIGURE 10. RESISTANCE vs VREF PIN CURRENT 5 HI20206 • When mounting onto the printed board, allow as much space as possible to the ground surface and the VCC surface on the board and reduce the parasitic inductance and resistance. Phase Relationship Between Data and Clock In order to obtain the desired characteristics as a D/A converter, it is necessary to set the phase relationship correctly between the externally applied data and clock. • It is desirable that the AGND and DGND be separated in the pattern on the board. It is similar with AVCC and DVCC . As shown in the diagram below, for example, it is recommended that the wiring to the electric supply of AGND and DGND as also AVCC and DVCC be conducted separately, and then making AGND and DGND as also AVCC and DVCC in common right near the power supply respectively. Satisfy the standard of the set-up time (tS) and hold time (tH) indicated in the electrical characteristics. As to the meaning of tS and tH , see the timing chart. Moreover, the clock pulse width is desired to be as indicated in the recommended operating condition. (3) Regarding the Load of D/A Output Pin • Insert in parallel a 47µF tantalum capacitor and a 100pF ceramic capacitor between the VCC surface on the printed board and the nearmost ground surface. (A of diagram below). It is also desirable to insert the above between the VCC surface near the pin of the IC and the ground surface (see Figure 11). They are bypass capacitors to prevent bad effects from occurring to the characteristics when the power supply voltage fluctuates due to the clock, etc. Receive the D/A output of the next stage with high impedance. In other words perform so that it becomes as follows: RL > 10kΩ CL < 20pF. The temperature characteristics indicated in the characteristics diagram has been measured under this condition. It is recommended to reduce noise which overlaps the D/A output by inserting a capacitor of over 0.1µF between pin 25 (AGND) and pin 26 (VSET). However, when it is made RL ≤ 10kΩ the temperature characteristics may change considerably. In addition, when it is made to CL ≥ 20pF, the rise and fall of the D/A output become slow and will not operate at high speed. Noise Reduction Measures As the D/A output voltage is a minute voltage of approximately 4mV per one step, ingenuity is required in reducing the noise entering from the outside of the IC as much as possible. Therefore, use the items given below as reference. HI20206 B DGND AVCC A POWER SUPPLY AGND DVCC +5V (4) PRINTED BOARD FIGURE 11. 10-11 0V (2) HI20206 0 TA = 25oC AVCC = DVCC = 5oC RL > 10kΩ 2 OUTPUT ZERO OFFSET VOLTAGE (mV) OUTPUT VOLTAGE FULL SCALE (VP-P) Typical Performance Curves DEVIATION RANGE 1 0 1 -10 B TA = 25oC AVCC = DVCC = 5V -20 2 R 0 1.0 AGND (V) AGND (V) 2.0 FIGURE 13. OUTPUT ZERO OFFSET VOLTAGE vs VSET - AGND 0 OUTPUT ZERO OFFSET VOLTAGE (mV) OUTPUT VOLTAGE FULL SCALE (mVP-P) FIGURE 12. OUTPUT VOLTAGE FULL SCALE vs VSET - AGND G RL > 10kΩ 1000 VSET IS CREATED BY RESISTANCE DIVISION OF VREF (VSET = 2VREF /3) IREF = -400µA AVCC = DVCC = 5.0V RL > 10kΩ 950 -5 -10 -20 0 20 40 60 80 VSET IS CREATED BY RESISTANCE DIVISION OF VREF (VSET = 2VREF /3) REF = -400µA AVCC = DVCC = 5V RL > 10kΩ -20 0 20 40 60 80 AMBIENT TEMPERATURE (oC) AMBIENT TEMPERATURE (oC) FIGURE 14. OUTPUT VOLTAGE FULL SCALE vs AMBIENT TEMPERATURE FIGURE 15. OUTPUT ZERO OFFSET vs AMBIENT TEMPERATURE OUTPUT ZERO OFFSET VOLTAGE (mV) OUTPUT VOLTAGE FULL SCALE (VP-P) 0 TA = 25oC VSET - AGND = 0.8V RL > 10kΩ 1000 950 TA = 25oC VSET - AGND = 0.8V RL > 10kΩ -5 10 4 5 4 6 POWER SUPPLY VOLTAGE (V) FIGURE 16. OUTPUT VOLTAGE FULL SCALE vs POWER SUPPLY VOLTAGE 5 POWER SUPPLY VOLTAGE (V) FIGURE 17. OUTPUT ZERO OFFSET VOLTAGE vs POWER SUPPLY VOLTAGE 10-12 6 HI20206 (Continued) INTERNAL REFERENCE VOLTAGE (V) INTERNAL REFERENCE VOLTAGE (V) Typical Performance Curves 1.20 1.15 -20 IREF = -400µA AVCC = DVCC = 5V 0 20 40 60 80 1.20 1.15 TA = -25oC IREF = 400µA 4 5 POWER SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (oC) FIGURE 18. INTERNAL REFERENCE VOLTAGE vs AMBIENT TEMPERATURE FIGURE 19. INTERNAL REFERENCE VOLTAGE vs POWER SUPPLY VOLTAGE 0 CROSSTALK (dB) -20 -40 -60 -80 TA = 25oC OUTPUT VOLTAGE FULL SCALE 1VP-P fCLK = 2fDATA AVCC = DVCC = 5V RL > 10kΩ, CL <20pF PINS 30, 32, 34 AND 36 ARE CONNECTED TO AVCC -100 10 DATA RATE (MHz) 20 FIGURE 20. CROSSTALK AMONG R, G, AND B vs DATA RATE 10-13 6