HI1260 Semiconductor NS EW August 1997 NOT RN D FO 8 E D EN I117 OMM See H C E R IG DES Triple 8-Bit, 35 MSPS, RGB, 3-Channel D/A Converter Features Description • Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . Triple 8-Bit The HI1260 is a triple 8-bit, high-speed, bipolar D/A converter designed for video band use. It has three separate, 8-bit pixel inputs, one each for red, green, and blue video data. A single 5.0V power supply and pixel clock input is all that is required to make the device operational. A bias voltage generator is internal. For lower CMOS power consumption, refer to the HI1178. • Maximum Conversion Speed . . . . . . . . . . . . . . . 35MHz • RGB 3-Channel Input/Output • Differential Linearity Error . . . . . . . . . . . . . . . ±0.5 LSB • Digital Input Voltage . . . . . . . . . . . . . . . . . . . .TTL Level • Output Voltage Full Scale (Typ) . . . . . . . . . . . . . . 1VP-P • Low Power Consumption (Typ) . . . . . . . . . . . . .360mW Ordering Information • Direct Replacement for Sony CXA1260 PART NUMBER Applications TEMP. RANGE (oC) HI1260JCQ • Digital TV -20 to 75 PACKAGE 48 Ld MQFP PKG. NO. Q48.12 x 12-S • Graphics Display • High Resolution Color Graphics • Video Reconstruction • Instrumentation • Image Processing • I/Q Modulation Pinout DGND 5 32 6 7 31 ROUT NC GOUT 30 NC 8 29 9 28 BOUT NC 10 27 AVCC 11 12 26 NC VREF VSET AGND NC NC DGND DVCC NC 25 13 14 15 16 17 18 19 20 21 22 23 24 B5 B4 R2 33 CLK B3 R1 NC NC 4 B7 B8 B1 B2 R4 R3 NC 34 B6 G8 DGND 35 G2 G7 R7 NC 2 3 1 G5 G6 R6 R5 48 47 46 45 44 43 42 41 40 39 38 37 36 G1 G3 G4 R8 NC HI1260 (MQFP) TOP VIEW CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1997 10-1 File Number 4112.1 HI1260 Functional Block Diagram DGND 37 33 ROUT R1 39 DECODER R2 40 2 3 3 R3 41 R4 42 R5 44 INPUT BUFFER (R) CURRENT SWITCH (R) R R R 2R R 2R R 2R R 2R R 2R 6 6 R6 45 R7 46 R8 47 CLOCK SYNCHRONIZING CIRCUIT R G1 1 DECODER G2 2 2 3 G3 3 G4 4 G5 5 INPUT BUFFER (G) 6 G6 6 G7 7 3 CURRENT SWITCH (G) R R R 2R R 2R R 2R R 2R R 2R 6 G8 8 R B1 9 DECODER B2 10 2 3 B3 11 B4 12 B5 13 31 GOUT R R R 2R R 2R R 2R R 2R R 2R 29 BOUT 3 INPUT BUFFER (B) CURRENT SWITCH (B) 6 B6 14 6 B7 15 B8 16 R 27 AVCC CLOCK BUFFER -+ INTERNAL REFERENCE VOLTAGE SOURCE 18 20 23 24 25 CLOCK DVCC AGND VSET VREF 10-2 HI1260 Pin Descriptions NUMBER SYMBOL 1 to 16 39 to 42 44 to 47 R1 to R8 G1 to G8 B1 to B8 EQUIVALENT CIRCUIT DESCRIPTION Digital Input pin. From pins 39 to 42 and from 44 to 47 are for RED. R1 is MSB and R8 is LSB. From pins 1 to 8 are for GREEN. G1 is MSB and G8 is LSB. From pins 9 to 16 are for BLUE. B1 is MSB and B8 is LSB. DVCC 20 39 - 42 44 - 47 1 - 16 37 DGND 18 CLK Clock Input pin. DVCC 20 18 37 DGND 20 DVCC 17 21 to 22 NC 23 AGND 24 VSET Digital VCC . Vacant pin (no connection). Analog GND. Bias Input pin. Normally, apply 0.87V. See “Note on use.” AVCC 27 54K 24 23 25 VREF Internal Reference Voltage Out pin, 1.2V (Typ). A pull-down resistor is necessary externally. See “Notes on use.” AVCC 27 25 20p 23 AGND 10-3 HI1260 Pin Descriptions NUMBER SYMBOL 26 NC 27 AVCC 28 NC 29 BOUT (Continued) EQUIVALENT CIRCUIT DESCRIPTION Vacant pin (no connection). Analog VCC . Vacant pin but connect to AVCC (Note 1). Analog Output pin for BLUE. AVCC 27 RO 29 23 AGND 30 NC 31 GOUT Vacant pin but connect to AVCC (Note 1). Analog Output pin for GREEN. AVCC 27 RO 31 23 AGND 32 NC 33 ROUT Vacant pin but connect to AVCC (Note 1). Analog Output pin for RED. AVCC 27 RO 33 23 AGND 34 To 36 NC 19, 37, 43 DGND 48 NC Vacant pin but connect to AVCC (Note 1). Digital GND. Vacant pin (no connection). NOTE: 1. Pins 30, 32, 34 and 36 are vacant, but in order to reduce interference between the individual RGB outputs, connect them to AVCC . 10-4 HI1260 Absolute Maximum Ratings TA = 25oC Thermal Information Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 7V Input Voltage (Digital) VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC VCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC Input Voltage (VSET Pin), VSET . . . . . . . . . . . . . . . . . . -0.3V to VCC Output Voltage (Analog), VOUT . . . . . . . . . . . . . . VCC -2.1V to VCC Output Current (Analog), IOUT . . . . . . . . . . . . . . . . . . -3mA to 10mA (VREF Pin), IREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA to 0mA Allowable Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . 0.7W Thermal Resistance (Typical, Note 2) θJA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-55oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (Lead Tips Only) Recommended Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -20oC to 75oC Supply Voltage AVCC , DVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V AVCC - DVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to 0.2V AGND - DGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.0.5V Digital Input Voltage H Level, VIH , VCLKH . . . . . . . . . . . . . . . . . . . . . . . . .2.0V to DVCC L Level, VIL , VCLKL . . . . . . . . . . . . . . . . . . . . . . . . . DGND to 0.8V VSET Input Voltage, VSET . . . . . . . . . . . . . . . . . . . . . . . 0.7V to 1.0V VREF Pin Current, IREF . . . . . . . . . . . . . . . . . . . . . . . -3mA to 0.4mA Clock Pule Width tPW1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ns tPW0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = 25oC, AVCC = DVCC = 5.0V, AGND = DGND = 0.0V PARAMETER SYMBOL TEST CONDITIONS NOTES MIN TYP MAX UNITS Resolution RSL - 8 - Bit Monotony MNT - Guarantee - - Differential Linearity Error DLE - 0.5 LSB ILE VSET - AGND = 0.87V RL > 10kΩ FS = Full Scale -0.5 Integral Linearity Error -0.4 - 4 % of FS VSET - AGND = 0.87V RL > 10kΩ CL < 20pF 35 - - MSPS Note 3 0.85 1.0 1.15 VP-P Note 4 0 4 8 % -40 -6 0 mV 270 340 420 Ω 54 72 90 mA VI = DVCC - 1.2 20 µA - 0.6 10 µA VI = DGND -10 0 10 µA Maximum Conversion Speed fMAX Full Scale Output Voltage VOFS RGB Output Voltage Full Scale Ratio FSR Output Zero Offset Voltage VOFFSET Output Resistance RO Consumption Current ID Digital Data Input Current H Level Upper 2 Bits IIH(U) Lower 6 Bits IIH(L) L Level Upper 2 Bits IIL(U) VSET - AGND = 0.87V RL > 10kΩ IREF = -400µA Lower 6 Bits IIL(L) -10 0 10 µA H Level ICLKH VCLK = DVCC - 3 30 µA L Level ICLKL VCLK = DGND -10 0 10 µA VSET Input Current ISET VSET = AGND = 0.87V Internal Reference Voltage VREF IREF = -400µA Clock Input Current -5 -0.3 0 µA 1.08 1.20 1.32 V Set-Up Time tS 12 - - ns Hold Time tH 3 - - ns NOTES: 3. AVCC - V0 . VO FS ( G ) VO FS ( B ) VO FS ( R ) 4. Maximum value among 100 × ------------------------ – 1 ,100 × ------------------------ – 1 , or 100 × ------------------------ – 1 . VO FS ( G ) VO FS ( B ) VO FS ( R ) 10-5 HI1260 TABLE 1. INPUT CORRESPONDING TABLE INPUT CODE OUTPUT VOLTAGE MSB LSB 1 1 1 1 1 1 1 1 VCC + VOFFSET • • • 1 0 0 • • • 0 0 0 0 0 VCC + VOFFSET -0.5V • • • 0 Standard Circuit Design Data PARAMETER 0 0 • • • 0 0 0 0 0 VCC + VOFFSET -1.0V TA = 25oC, AVCC = DVCC = 5.0V, AGND = DGND = 0.0V SYMBOL TEST CONDITIONS NOTES MIN TYP MAX UNITS - -40 -35 dB Crosstalk Among R, G and B CT D/A OUT: 1VP-P RL > 10kΩ CL < 20pF fDATA = 7MHz fCLK = 14MHz See Figure 5 Glitch Energy GE VSET – AGND = 0.87V RL > 10kΩ fCLK = 1MHz Digital Ramp Output See Figure 6 Note 5 - 30 - pV/s Rise Time tr Note 6 - 5.5 - ns Fall Time tf VSET -AGND = 0.87V See Figure 4 Note 6 - 5.0 - ns - 1.6 - ns Settling Time tSET NOTE: 5. Observe the glitch which is generated when the digital input varies as follows: 0 0 1 1 1 1 1 1 – 0 1 0 0 0 0 0 1 1 1 1 1 1 1 – 1 0 0 0 0 0 1 0 1 1 1 1 1 1 – 1 1 0 0 0 0 0 0 0 0 0 0 6. The time required for the D/A OUT to arrive at 90% of its final value from 10%. Test Circuits and Waveforms 19, 37, 43 DVCC D1 D1 - D8 D2 8 (R) D1 - D8 D8 8 (G) D1 - D8 39 - 42 44 - 47 1-8 33 31 29 9 - 16 8 (B) 27 25 24 DGND ROUT GOUT BOUT VREF VSET + - 23 CLK TTL LEVEL 18 V AVCC 3K V 33µF 20 CLK HI1260 FIGURE 1. DIFFERENTIAL LINEARITY AND INTEGRAL LINEARITY TEST CIRCUIT 10-6 HI1260 Test Circuits and Waveforms (MSB) OUT D1 (Continued) D1 - D8 D2 8-BIT COUNTER (TTL OUTPUT) 19, 37, 43 DIGITAL RAMP WAVEFORM GENERATION 39 - 42 44 - 47 8 (R) D1 - D8 33 1-8 (LSB) D8 8 (G) D1 - D8 31 9 - 16 29 8 (B) ROUT GOUT BOUT OSCILLOSCOPE RIN = 1MΩ CIN - 10PF BW = 20MHz 27 IN 24 23 VSET + 12.5K V - 33µF 18 20 CLK HI1260 MCLK f = 35 MSPS TTL LEVEL RECTANGULAR WAVE CLK AGND DGND AVCC DVCC 2ns TO 10ns D1 TO D8 TIMING BETWEEN CLK AND DATA FIGURE 2. MAXIMUM CONVERSION RATE TEST CIRCUIT D1 - D8 DVCC 8 (R) 1-8 8 (G) 8 19, 37, 43 39 - 42 44 - 47 33 31 9- 16 29 (B) 27 25 24 ROUT GOUT BOUT V AVCC VREF VSET 33µF V 3K 23 18 CLK TTL LEVEL 20 CLK HI1260 FIGURE 3. OUTPUT VOLTAGE FULL SCALE PRECISION, RGB OUTPUT VOLTAGE FULL SCALE RATIO, AND OUTPUT ZERO OFFSET VOLTAGE TEST CIRCUITS 10-7 HI1260 Test Circuits and Waveforms (Continued) HI1260 OBSERVE DATA WAVEFORM WITH AN OSCILLOSCOPE RIN = 1MΩ BW = 200MHz ( D1 - D8 8 ) (1m) COAXIAL CABLE (R) ROUT 1-8 8 CO-AXIAL CABLE (1m) 33 (G) 330 9 - 16 8 50 19, 37, 43 39 - 42 44 - 47 51 COAXIAL CABLE 50 (B) GOUT 31 47 330 51 COAXIAL CABLE 50 OBSERVE CLK WAVEFORM WITH AN OSCILLOSCOPE RIN = 1MΩ BW = 200MHz ( ) BOUT 29 330 51 COAXIAL CABLE 50 27 VSET 24 12.5K + - 23 33µF (TTL) 18 1/ 2 20 1.2K DIVIDER COAXIAL CABLE (1m) f = 35MHz TTL LEVEL 47 50 OBSERVE CLK WAVEFORM WITH AN OSCILLOSCOPE RIN = 1MΩ BW = 200MHz ( PULSE GENERATOR 8082A (YHP) ) AGND DGND AVCC DVCC f = 35 MSPS TTL LEVEL RECTANGULAR WAVE PULSE GENERATOR 8082A (YHP) D DELAY ADJUSTMENT FIGURE 4. SETUP TIME, HOLD TIME, AND RISE AND FALL TIME TEST CIRCUITS D1 - D8 8 (R) f = 7MHz TTL LEVEL RECTANGULAR WAVE 1-8 8 (G) 8 1/ 19, 37, 43 39 - 42 44 - 47 50Ω EXIT 33 31 9 - 16 (B) 29 27 DIVIDER 24 23 CLK MCLK f = 14 MSPS TTL LEVEL RECTANGULAR WAVE FET PROVE GOUT BOUT P6202 (TEKTRONIX) 28, 30, 32 34 - 36 2 ROUT AVCC VSET + 12.5K - 33µF 18 20 HI1260 NOTES: The following notes cover the measurement methods in case the measuring crosstalk of G → R: 7. Apply the data to G only and measure the power of the frequency component of the data at ROUT . 8. Apply the data to R only and measure the power of the frequency component of the data at ROUT . 9. Take the difference of the above two powers. The unit is in dB. FIGURE 5. CROSSTALK AMONG R, G AND B TEST CIRCUIT 10-8 SPECTRUM ANALYZER HI1260 Test Circuits and Waveforms (Continued) (MSB) OUT D1 D1 -D8 D2 8-BIT COUNTER (TTL OUTPUT) 19, 37, 43 DIGITAL RAMP WAVEFORM GENERATION 39 - 42 44 - 47 8 (R) D1 -D8 33 1-8 8 (G) D1 -D8 (LSB) D8 31 9 - 16 29 8 (B) 100PF IN 27 25 24 23 ROUT GOUT BOUT VREF VSET 3K + V - 33µF 18 MCLK f = 1 MSPS TTL LEVEL RECTANGULAR WAVE 20 CLK HI1260 CLK AGND DGND AVCC DVCC 5ns TO 300ns D1 TO D8 TIMING OF CLK AND DATA FIGURE 6. GLITCH ENERGY TEST CIRCUIT Timing Diagram t1 t12 t2 t3 t34 t4 tPW1 tPW0 CLK VTH = 1.5V tX tY DATA VTH = 1.4V tH tH tS tS 100% 0% 10% 90% VTH: THRESHOLD LEVEL D/A OUT 90% 10% 0% 100% tf tr At the time t = tx , the data of individual bits are switched and thereafter, when the CLK becomes L → H at t = t2 , the D/A OUT is varied synchronous with it. That is, the D/A OUT is synchronous with the rise of the CLK. (In this case, fetching of the data is carried out at the fall of the CLK (at the time when t = T12).) At the time t = TY , the data of individual bits are switched and thereafter, when the CLK becomes L → H at t = t4 , the D/A OUT is synchronous with it. That is, the D/A OUT is synchronous with the rise of the CLK. (In this case, fetching of the data is carried out at the fall of CLK (at the time when t = t4 ).) FIGURE 7. 10-9 HI1260 TA = 25oC AVCC = DVCC = 5.0V RL > 10kΩ 2.0 0 OUTPUT ZERO OFFSET VOLTAGE (mV) OUTPUT VOLTAGE FULL SCALE (VP-P) Typical Performance Curves DEVIATION RANGE 1.0 0 1.0 B -10 G TA = 25oC AVCC = DVCC = 5.0V RL > 10kΩ -20 2.0 0 1.0 VSET - AGND (V) 2.0 VSET - AGND (V) FIGURE 8. OUTPUT VOLTAGE FULL SCALE vs VSET - AGND FIGURE 9. OUTPUT ZERO OFFSET VOLTAGE vs VSET - AGND 0 OUTPUT ZERO OFFSET VOLTAGE (mV) OUTPUT VOLTAGE FULL SCALE (mVP-P) R 1000 VSET IS CREATED BY RESISTANCE DIVISION OF VREF (VSET = 2VREF/3) IREF = -400µA AVCC = DVCC = 5.0V RL > 10kΩ 950 -20 0 20 40 60 VSET IS CREATED BY RESISTANCE DIVISION OF VREF (VSET = 2VREF/3) IREF = -400µA AVCC = DVCC = 5.0V RL > 10kΩ -5 -10 80 -20 AMBIENT TEMPERATURE (oC) 0 20 40 60 80 AMBIENT TEMPERATURE (oC) FIGURE 10. OUTPUT VOLTAGE FULL SCALE vs AMBIENT TEMPERATURE FIGURE 11. OUTPUT ZERO OFFSET VOLTAGE vs AMBIENT TEMPERATURE OUTPUT OFFSET VOLTAGE (mV) OUTPUT VOLTAGE FULL SCALE (VP-P) 0 1000 950 TA = 25oC VSET - AGND = 0.8V RL > 10kΩ -5 TA = 25oC VSET - AGND = 0.8V RL > 10kΩ -10 4 5 6 FIGURE 12. OUTPUT VOLTAGE FULL SCALE vs SUPPLY VOLTAGE 4 5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) FIGURE 13. OUTPUT ZERO OFFSET VOLTAGE vs SUPPLY VOLTAGE 10-10 6 HI1260 (Continued) INTERNAL REFERENCE VOLTAGE (V) INTERNAL REFERENCE VOLTAGE (V) Typical Performance Curves 1.20 1.15 IREF = -400µA AVCC = DVCC = 5.0V -20 0 20 40 60 80 1.20 1.15 TA = 25oC IREF = -400µA 4 AMBIENT TEMPERATURE (oC) 5 SUPPLY VOLTAGE (V) FIGURE 14. INTERNAL REFERENCE VOLTAGE vs AMBIENT TEMPERATURE FIGURE 15. INTERNAL REFERENCE VOLTAGE vs SUPPLY VOLTAGE 0 CROSSTALK (dB) -20 -40 -60 -80 TA = 25oC OUTPUT VOLTAGE FULL SCALE 1VP-P fCLK = 2fDATA AVCC = DVCC = 5.0V RL > 10kΩ, CL < 20PF PINS 30, 32, 34 AND 36 ARE CONNECTED TO AVCC -100 10 20 DATA FREQUENCY (MHz) FIGURE 16. CROSSTALK AMONG R, G AND B vs DATA FREQUENCY 10-11 6 HI1260 Typical Application Circuit 19, 37, 43 DATA (TTL LEVEL) 39 - 42 44 - 47 (R) 33 ROUT R - + LPF ROUT LPF GOUT LPF BOUT 8 (G) 1-8 31 8 (B) GOUT R - + 9 16 8 28, 30, 32 29 34, 35, 36 BOUT R - + BW = 16MHz 27 25 VREF VSET 24 23 CLK (TTL LEVEL) CLK 18 3K + - R IS MATCHING RESISTANCE FOR LPF 33µF AGND 20 DGND AVCC DVCC HI1260 FIGURE 17. Notes On Use • Setting of Pin 24 (VSET) The full scale of the D/A output voltage changes by applying voltage to pin 24 (VSET). When load is connected to pin 25 (VREF), DC voltage of 1.2V is issued and the said voltage is dropped to 0.87V by resistance division. Satisfy the standard of the setup time (tS) and hold time (tH) indicated in the electrical characteristics. As to the reaming of tS and tH , see the timing chart. Moreover, the clock pulse width is desired to be as indicated in the recommended operating condition. When the 0.87V is applied to pin 24 (VSET), the D/A output of 1VP-P can be obtained. 24 RESISTANCE (kΩ) 25 5.0 VREF R1 VSET R R2 23 AGND 1.0 0.3 FIGURE 18. EXAMPLE OF USE Adjustment Method 0.1 0.1 The resistance R is determined in accordance with the recommended operating condition of IREF (Current flowing through resistance R). See R vs IREF of Figure 19. The calculation expression is as follows: R = VREF/IREF . 0.2 1 5 PIN CURRENT IREF (mA) FIGURE 19. RESISTANCE vs VREF PIN CURRENT • Regarding the Load of D/A Output Pin Adjust the volume so that the RGB output voltage full scale becomes 1.0V. (At this point, it becomes R1:R2 = 2:5). • Phase Relationship Between Data and Clock In order to obtain the desired characteristics as a D/A converter, it is necessary to set the phase relationship correctly between the externally applied data and clock. 10-12 Receive the D/A output of the next stage with high impedance. In other words, perform so that it becomes as follows: RL > 10kΩ CL < 20pF The temperature characteristics indicated in the characteristics diagram has been measured under this condition. HI1260 However, when it is made to RL ≤ 10kΩ the temperature characteristics may change considerably. In addition, when it is made to CL ≤ 20pF, the rise and fall of the D/A output become slow and will not operate at high speed. recommended that the wiring to the electric supply of AGND and DGND as also AVCC and DVCC be conducted separately, and then making AGND and DGND as also AVCC and DVCC in common right near the power supply respectively. • Noise Reduction Measures Inset in parallel a 47µF tantalum capacitor and a 100pF ceramic capacitor between the VCC surface on the printed board and the nearmost ground surface (A of diagram below). It is also desirable to insert the above between the VCC surface near the pin of the IC and the ground surface (B of diagram below). They are bypass capacitors to prevent bad effects from occurring to the characteristics when the power supply voltage fluctuates due to the clock, etc. As the D/A output voltage is a minute voltage of approximately 4mV per one step, ingenuity is required in reducing the noise entering from the outside of the IC as much as possible. Therefore, use the items given below as reference. When mounting onto the printed board, allow as much space as possible to the ground surface and the VCC surface on the board and reduce the parasitic inductance and resistance. It is desirable that the AGND and DGND be separated in the pattern on the board. It is similar with AVCC and DVCC . As shown in the diagram below, for example, it is It is recommended to reduce noise which overlaps the D/A output by inserting a capacitor of over 0.1µF between pin 23 (AGND) and pin 24 (VSET). CXI260Q-Z B DGND AVCC A POWER SUPPLY PRINTED BOARD FIGURE 20. 10-13 0V AGND +5V DVCC