Data Sheet

74LV4052-Q100
Dual 4-channel analog multiplexer/demultiplexer
Rev. 3 — 22 October 2015
Product data sheet
1. General description
The 74LV4052-Q100 is a dual 4-channel analog multiplexer/demultiplexer with a common
select logic. Each multiplexer has four independent inputs/outputs (nY0 to nY3) and a
common input/output (nZ). The common channel select logics include two digital select
inputs (S0 and S1) and an active LOW enable input (E). With E LOW, one of the four
switches is selected (low impedance ON-state) by S0 and S1. With E HIGH, all switches
are in the high impedance OFF-state, independent of S0 and S1. VCC and GND are the
supply voltage pins for the digital control inputs (S0, S1 and E). The VCC to GND ranges
are 1.0 V to 6.0 V. The analog inputs/outputs (nY0, to nY3, and nZ) can swing between
VCC as a positive limit and VEE as a negative limit. VCC - VEE may not exceed 6.0 V. For
operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically
ground).
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 Optimized for low-voltage applications: 1.0 V to 6.0 V
 Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
 Low ON resistance:
 145  (typical) at VCC  VEE = 2.0 V
 90  (typical) at VCC  VEE = 3.0 V
 60  (typical) at VCC  VEE = 4.5 V
 Logic level translation:
 To enable 3 V logic to communicate with 3 V analog signals
 Typical ‘break before make’ built in
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
74LV4052-Q100
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
3. Ordering information
Table 1.
Ordering information
Type number
74LV4052D-Q100
Package
Temperature range
Name
Description
Version
40 C to +125 C
SO16
plastic small outline package; 16 leads; body
width 3.9 mm
SOT109-1
TSSOP16
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
74LV4052PW-Q100 40 C to +125 C
4. Functional diagram
9&&
6
(
/2*,&
/(9(/
&219(56,21
<
<
<
2)
'(&2'(5
<
Fig 1.
<
6
=
*1'
9((
<
<
<
=
DDD
Functional diagram
74LV4052_Q100
Product data sheet
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Rev. 3 — 22 October 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
2 of 24
74LV4052-Q100
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
=
<
6
<
6
<
<
<
<
<
<
(
*
î
0';
=
DDK
Fig 2.
DDK
Logic symbol
Fig 3.
IEC logic symbol
Q<Q
9&&
9((
9&&
9&&
9&&
9((
IURP
ORJLF
9((
Q=
PQE
Fig 4.
Schematic diagram (one switch)
74LV4052_Q100
Product data sheet
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Rev. 3 — 22 October 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 24
74LV4052-Q100
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
5. Pinning information
5.1 Pinning
/94
<
9&&
<
<
=
<
<
=
<
<
(
9((
*1'
/94
<
6
6
<
<
9&&
<
=
<
<
=
<
<
(
<
9((
6
*1'
DDD
Fig 5.
6
DDD
Pin configuration for SO16
Fig 6.
Pin configuration for TSSOP16
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
2Y0
1
independent input or output
2Y2
2
independent input or output
2Z
3
common input or output
2Y3
4
independent input or output
2Y1
5
independent input or output
E
6
enable input (active LOW)
VEE
7
negative supply voltage
GND
8
ground (0 V)
S1
9
select logic input
S0
10
select logic input
1Y3
11
independent input or output
1Y0
12
independent input or output
1Z
13
common input or output
1Y1
14
independent input or output
1Y2
15
independent input or output
VCC
16
positive supply voltage
74LV4052_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 22 October 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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74LV4052-Q100
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
6. Functional description
Table 3.
Function table[1]
Input
Channel on
E
S1
S0
L
L
L
nY0 and nZ
L
L
H
nY1 and nZ
L
H
L
nY2 and nZ
L
H
H
nY3 and nZ
H
X
X
none
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol
Parameter
VCC
supply voltage
Conditions
Min
Max
Unit
[1]
0.5
+7.0
V
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
[2]
-
20
mA
switch clamping current
VSW < 0.5 V or VSW > VCC + 0.5 V
[2]
-
20
mA
ISW
switch current
VSW > 0.5 V or VSW < VCC + 0.5 V;
source or sink current
[2]
-
25
mA
Tstg
storage temperature
65
+150
C
Tamb = 40 C to +125 C
[3]
IIK
ISK
total power dissipation
Ptot
[1]
DIP16 package
-
750
mW
SO16 package
-
500
mW
SSOP16 and TSSOP16 package
-
400
mW
To avoid drawing VCC current out of terminal nZ, when switch current flows into terminals nYn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VCC current flows out of terminals nYn. In this case, there is
no limit for the voltage drop across the switch, but the voltages at nYn and nZ may not exceed VCC or VEE.
[2]
The minimum input voltage rating may be exceeded if the input current rating is observed.
[3]
For SO16 package: above 70 C the value of Ptot derates linearly with 8 mW/K.
For TSSOP16 package: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
74LV4052_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 22 October 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
5 of 24
74LV4052-Q100
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
8. Recommended operating conditions
Table 5.
Recommended operating conditions[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC
supply voltage
see Figure 7
1
3.3
6
V
VI
input voltage
0
-
VCC
V
VSW
switch voltage
Tamb
ambient temperature
t/V
[1]
0
-
VCC
V
40
-
+125
C
input transition rise and fall rate VCC = 1.0 V to 2.0 V
-
-
500
ns/V
VCC = 2.0 V to 2.7 V
-
-
200
ns/V
VCC = 2.7 V to 6.0 V
-
-
100
ns/V
in free air
The static characteristics are guaranteed from VCC = 1.2 V to 6.0 V. However, LV devices are guaranteed to function down to
VCC = 1.0 V (with input levels GND or VCC).
001aak344
8.0
VCC - GND
(V)
6.0
operating area
4.0
2.0
0
0
Fig 7.
2.0
4.0
6.0
8.0
VCC - VEE (V)
Guaranteed operating area as a function of the supply voltages
74LV4052_Q100
Product data sheet
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Rev. 3 — 22 October 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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74LV4052-Q100
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
HIGH-level input voltage
VIH
LOW-level input voltage
VIL
input leakage current
II
IS(OFF)
IS(ON)
OFF-state leakage current
ON-state leakage current
supply current
ICC
ICC
additional supply current
CI
input capacitance
Csw
switch capacitance
[1]
40 C to +85 C
Conditions
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
VCC = 1.2 V
0.9
-
-
0.9
-
V
VCC = 2.0 V
1.4
-
-
1.4
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
2.0
-
V
VCC = 4.5 V
3.15
-
-
3.15
-
V
VCC = 6.0 V
4.20
-
-
4.20
-
V
VCC = 1.2 V
-
-
0.3
-
0.3
V
VCC = 2.0 V
-
-
0.6
-
0.6
V
VCC = 2.7 V to 3.6 V
-
-
0.8
-
0.8
V
VCC = 4.5 V
-
-
1.35
-
1.35
V
VCC = 6.0 V
-
-
1.80
-
1.80
V
VCC = 3.6 V
-
-
1.0
-
1.0
A
VCC = 6.0 V
-
-
2.0
-
2.0
A
VCC = 3.6 V
-
-
1.0
-
1.0
A
VCC = 6.0 V
-
-
2.0
-
2.0
A
VCC = 3.6 V
-
-
1.0
-
1.0
A
VCC = 6.0 V
-
-
2.0
-
2.0
A
VCC = 3.6 V
-
-
20
-
40
A
VCC = 6.0 V
-
-
40
-
80
A
per input; VI = VCC  0.6 V;
VCC = 2.7 V to 3.6 V
-
-
500
-
850
A
-
3.5
-
-
-
pF
independent pins nYn
-
5
-
-
-
pF
common pins nZ
-
12
-
-
-
pF
VI = VCC or GND
VI = VIH or VIL; see Figure 8
VI = VIH or VIL; see Figure 9
VI = VCC or GND; IO = 0 A
Typical values are measured at Tamb = 25 C.
74LV4052_Q100
Product data sheet
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Rev. 3 — 22 October 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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74LV4052-Q100
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
9.1 Test circuits
9&&
6WR6
9,+RU9,/
Q=
9&&
Q<Q Q<Q Q=
Q<Q (
,6
6WR6
9,+RU9,/
VZLWFK
(
,6
,6
*1' 9((
*1' 9((
9&&
*1'
9,
92
92
9,
DDD
DDD
VI = VCC or VEE and VO = VEE or VCC.
Fig 8.
VZLWFK
Q<Q VI = VCC or VEE and VO = open circuit.
Test circuit for measuring OFF-state leakage
current
Fig 9.
Test circuit for measuring ON-state leakage
current
9.2 ON resistance
Table 7.
ON resistance
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 10 and
Figure 11.
Symbol
Parameter
RON(peak) ON resistance (peak)
40 C to +85 C
Conditions
Min
Max
Min
Max
-
-
-
-
-

-
145
325
-
375

VI = 0 V to VCC  VEE
VCC = 1.2 V; ISW = 100 A
[2]
VCC = 2.0 V; ISW = 1000 A
RON
VCC = 2.7 V; ISW = 1000 A
-
90
200
-
235

VCC = 3.0 V to 3.6 V;
ISW = 1000 A
-
80
180
-
210

VCC = 4.5 V; ISW = 1000 A
-
60
135
-
160

VCC = 6.0 V; ISW = 1000 A
-
55
125
-
145

-
-
-
-
-

-
5
-
-
-

ON resistance mismatch VI = 0 V to VCC  VEE
between channels
VCC = 1.2 V; ISW = 100 A
[2]
VCC = 2.0 V; ISW = 1000 A
74LV4052_Q100
Product data sheet
40 C to +125 C Unit
Typ[1]
VCC = 2.7 V; ISW = 1000 A
-
4
-
-
-

VCC = 3.0 V to 3.6 V;
ISW = 1000 A
-
4
-
-
-

VCC = 4.5 V; ISW = 1000 A
-
3
-
-
-

VCC = 6.0 V; ISW = 1000 A
-
2
-
-
-

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Rev. 3 — 22 October 2015
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74LV4052-Q100
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
Table 7.
ON resistance …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 10 and
Figure 11.
Symbol
RON(rail)
Parameter
ON resistance (rail)
40 C to +85 C
Conditions
Min
Max
Min
Max
-
225
-
-
-

VCC = 2.0 V; ISW = 1000 A
-
110
235
-
270

VCC = 2.7 V; ISW = 1000 A
-
70
145
-
165

VCC = 3.0 V to 3.6 V;
ISW = 1000 A
-
60
130
-
150

VCC = 4.5 V; ISW = 1000 A
-
45
100
-
115

VCC = 6.0 V; ISW = 1000 A
-
40
85
-
100

-
250
-
-
-

VCC = 2.0 V; ISW = 1000 A
-
120
320
-
370

VCC = 2.7 V; ISW = 1000 A
-
75
195
-
225

VCC = 3.0 V to 3.6 V;
ISW = 1000 A
-
70
175
-
205

VCC = 4.5 V; ISW = 1000 A
-
50
130
-
150

VCC = 6.0 V; ISW = 1000 A
-
45
120
-
135

VI = GND
VCC = 1.2 V; ISW = 100 A
RON(rail)
ON resistance (rail)
40 C to +125 C Unit
Typ[1]
[2]
VI = VCC  VEE
VCC = 1.2 V; ISW = 100 A
[2]
[1]
Typical values are measured at Tamb = 25 C.
[2]
When supply voltages (VCC  VEE) near 1.2 V the analog switch ON resistance becomes extremely non-linear. When using a supply of
1.2 V, use these devices only for transmitting digital signals.
74LV4052_Q100
Product data sheet
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Rev. 3 — 22 October 2015
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74LV4052-Q100
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
9.3 On resistance waveform and test circuit
9
96:
9&&
6WR6
9,+RU9,/
Q=
Q<Q VZLWFK
Q<Q (
*1' 9((
9,
*1'
,6:
DDD
RON = VSW / ISW.
Fig 10. Test circuit for measuring RON
001aak412
180
RON
(Ω)
VCC = 2.0 V
120
VCC = 3.0 V
VCC = 4.5 V
60
0
0
1.2
2.4
3.6
4.8
VI (V)
Vi = 0 V to VCC  VEE
Fig 11. Typical RON as a function of input voltage
74LV4052_Q100
Product data sheet
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Rev. 3 — 22 October 2015
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74LV4052-Q100
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
10. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit, see Figure 14.
Symbol Parameter
40 C to +85 C
Conditions
Max
Min
Max
VCC = 1.2 V
-
25
-
-
-
ns
VCC = 2.0 V
-
9
17
-
20
ns
-
6
13
-
15
ns
-
5
10
-
12
ns
-
4
9
-
10
ns
-
3
7
-
8
ns
VCC = 1.2 V
-
190
-
-
-
ns
VCC = 2.0 V
-
65
121
-
146
ns
[2]
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
[3]
VCC = 4.5 V
VCC = 6.0 V
enable time
ten
E, Sn to nYn, nZ; see Figure 13
[2]
VCC = 2.7 V
-
48
89
-
108
ns
VCC = 3.0 V to 3.6 V; CL = 15 pF
[3]
-
30
-
-
-
ns
VCC = 3.0 V to 3.6 V
[3]
-
36
71
-
86
ns
-
32
60
-
73
ns
-
25
46
-
56
ns
VCC = 1.2 V
-
125
-
-
-
ns
VCC = 2.0 V
-
43
80
-
95
ns
VCC = 4.5 V
VCC = 6.0 V
tdis
disable time
E, Sn to nYn, nZ; see Figure 13
[2]
VCC = 2.7 V
-
33
59
-
71
ns
VCC = 3.0 V to 3.6 V; CL = 15 pF
[3]
-
22
-
-
-
ns
VCC = 3.0 V to 3.6 V
[3]
-
26
48
-
57
ns
-
23
41
-
49
ns
-
18
32
-
38
ns
-
57
-
-
-
pF
VCC = 4.5 V
VCC = 6.0 V
power dissipation
capacitance
CPD
[1]
[2]
Unit
Min
propagation delay nYn to nZ, nZ to nYn; see Figure 12
tpd
40 C to +125 C
Typ[1]
CL = 50 pF; fi = 1 MHz;
VI = GND to VCC
[4]
All typical values are measured at Tamb = 25 C.
tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3]
Typical values are measured at nominal supply voltage (VCC = 3.3 V).
[4]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + ((CL  Csw VCC2  fo) where:
fi = input frequency in MHz, fo = output frequency in MHz
CL = output load capacitance in pF
Csw = maximum switch capacitance in pF;
VCC = supply voltage in Volts
N = number of inputs switching
(CL  VCC2  fo) = sum of the outputs.
74LV4052_Q100
Product data sheet
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NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
10.1 Waveforms
VCC
nYn or nZ
input
VM
VEE
tPLH
tPHL
VO
nZ or nYn
output
VM
VEE
001aak351
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 12. nYn, nZ to nZ, nYn propagation delays
VCC
Sn, E input
VM
VSS
tPLZ
nYn or nZ output
LOW-to-OFF
OFF-to-LOW
tPZL
VO
90 %
10 %
VEE
tPHZ
VO
tPZH
90 %
nYn or nZ output
HIGH-to-OFF
OFF-to-HIGH
10 %
VEE
switch ON
switch OFF
switch ON
001aak352
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 13. Enable and disable times
Table 9.
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
< 2.7 V
0.5VCC
0.5VCC
2.7 V to 3.6 V
1.5 V
1.5 V
> 3.6 V
0.5VCC
0.5VCC
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Dual 4-channel analog multiplexer/demultiplexer
VI
tW
90 %
negative
pulse
VM
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
0V
VM
10 %
VM
VM
10 %
tW
VEXT
VCC
VI
RL
VO
G
DUT
RT
VEE
RL
CL
001aak353
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 14. Test circuit for measuring switching times
Table 10.
Test data
Supply voltage
Input
VCC
VI
tr, tf
CL
RL
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
< 2.7 V
VCC
 6 ns
50 pF
1 k
open
VEE
2VCC
2.7 V to 3.6 V
2.7 V
 6 ns
15 pF, 50 pF
1 k
open
VEE
2VCC
> 3.6 V
VCC
 6 ns
50 pF
1 k
open
VEE
2VCC
74LV4052_Q100
Product data sheet
Load
VEXT
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Dual 4-channel analog multiplexer/demultiplexer
10.2 Additional dynamic parameters
Table 11. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); VI = GND or VCC (unless otherwise
specified); tr = tf  6.0 ns; Tamb = 25 C.
Symbol Parameter
Conditions
THD
fi = 1 kHz; CL = 50 pF; RL = 10 k; see Figure 19
total harmonic
distortion
Min
Typ
Max
Unit
VCC = 3.0 V; VI = 2.75 V (p-p)
-
0.8
-
%
VCC = 6.0 V; VI = 5.5 V (p-p)
-
0.4
-
%
VCC = 3.0 V; VI = 2.75 V (p-p)
-
2.4
-
%
VCC = 6.0 V; VI = 5.5 V (p-p)
-
1.2
-
%
-
180
-
MHz
-
200
-
MHz
VCC = 3.0 V
-
50
-
dB
VCC = 6.0 V
-
50
-
dB
-
0.11
-
V
-
0.12
-
V
VCC = 3.0 V
-
60
-
dB
VCC = 6.0 V
-
60
-
dB
fi = 10 kHz; CL = 50 pF; RL = 10 k; see Figure 19
f(3dB)
3 dB frequency
response
CL = 50 pF; RL = 50 ; see Figure 15
isolation (OFF-state)
fi = 1 MHz; CL = 50 pF; RL = 600 ; see Figure 17
[1]
VCC = 3.0 V
VCC = 6.0 V
iso
crosstalk voltage
Vct
[2]
between digital inputs and switch;
fi = 1 MHz; CL = 50 pF; RL = 600 ; see Figure 20
VCC = 3.0 V
VCC = 6.0 V
Xtalk
crosstalk
[2]
between switches; fi = 1 MHz; CL = 50 pF;
RL = 600 ; see Figure 21
[1]
To obtain 0 dBm level at output for 1 MHz, adjust fi voltage (0 dBm = 1 mW into 50 ).
[2]
To obtain 0 dBm level at output for 1 MHz, adjust fi voltage (0 dBm = 1 mW into 600 ).
10.2.1 Test circuits
9&&
6WR6
9,+RU9,/
Q=
—)
9&&
5/
Q<Q
Q<Q
VZLWFK
(
*1' 9((
5/
&/
G%
*1'
IL
DDD
Fig 15. Test circuit for measuring frequency response
74LV4052_Q100
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Dual 4-channel analog multiplexer/demultiplexer
001aak361
5
(dB)
0
−5
10
102
103
104
105
106
f (kHz)
VCC = 3.0 V; GND = 0 V; VEE = - 3.0 V; RL = 50 ; RSOURCE = 1 k.
Fig 16. Typical frequency response
9&&
6WR6
9,+RU9,/
Q=
—)
9&&
5 /
Q<Q
Q<Q
VZLWFK
(
*1' 9((
5 /
&/
G%
9&&
IL
DDD
Fig 17. Test circuit for measuring isolation (OFF-state)
74LV4052_Q100
Product data sheet
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Dual 4-channel analog multiplexer/demultiplexer
001aak360
0
(dB)
−50
−100
102
10
103
104
105
106
f (kHz)
VCC = 3.0 V; GND = 0 V; VEE = - 3.0 V; RL = 50 ; RSOURCE = 1 k.
Fig 18. Typical isolation (OFF-state) as function of frequency
9&&
6WR6
9,+RU9,/
Q=
—)
9&&
5/
Q<Q VZLWFK
Q<Q (
*1' 9((
5/
&/
'
*1'
IL
DDD
Fig 19. Test circuit for measuring total harmonic distortion
74LV4052_Q100
Product data sheet
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Dual 4-channel analog multiplexer/demultiplexer
9&&
9&&
5/
6WR6
Q=
9&&
5/
Q<Q VZLWFK
Q<Q (
5/
*
*1' 9((
5/
&/
9
92
9,+RU9,/
DDD
a. Test circuit
ORJLF
LQSXW6Q(
RII
RQ
RII
92
9FW
DDM
b. Input and output pulse definitions
VI may be connected to Sn or E.
Fig 20. Test circuit for measuring crosstalk voltage between digital inputs and switch
74LV4052_Q100
Product data sheet
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Dual 4-channel analog multiplexer/demultiplexer
9&&
6WR6
9,+RU9,/
5/
Q=
9&&
9&&
5/
5/
Q<Q
Q<Q
(
—)
*1' 9((
5/
*1'
&/
92
G%
5/
9,
DDD
a. Switch-on channel.
9&&
9&&
5/
6WR6
9,+RU9,/
Q=
9&&
9&&
5/
5/
Q<Q
Q<Q
(
*1' 9((
*1'
5/
92
&/
5/
9,
5/
G%
DDD
b. Switch-off channel.
Fig 21. Test circuit for measuring crosstalk between switches
74LV4052_Q100
Product data sheet
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11. Package outline
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74LV4052_Q100
Product data sheet
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Dual 4-channel analog multiplexer/demultiplexer
76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP
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Fig 23. Package outline SOT403-1 (TSSOP16)
74LV4052_Q100
Product data sheet
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12. Abbreviations
Table 12.
Abbreviations
Acronym
Description
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
13. Revision history
Table 13.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LV4052_Q100 v.3
20151022
Product data sheet
-
74LV4052_Q100 v.2
-
74LV4052_Q100 v.1
Modifications:
74LV4052_Q100 v.2
Modifications:
74LV4052_Q100 v.1
74LV4052_Q100
Product data sheet
•
Descriptive title corrected (errata)
20140915
•
•
Product data sheet
Section 2: ESD protection: MIL-STD-833 changed to MIL-STD883
Table 1: Typo in type number corrected.
20130722
Product data sheet
-
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Rev. 3 — 22 October 2015
-
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14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
14.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74LV4052_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 22 October 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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16. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
9.1
9.2
9.3
10
10.1
10.2
10.2.1
11
12
13
14
14.1
14.2
14.3
14.4
15
16
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 8
On resistance waveform and test circuit. . . . . 10
Dynamic characteristics . . . . . . . . . . . . . . . . . 11
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Additional dynamic parameters . . . . . . . . . . . 14
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21
Legal information. . . . . . . . . . . . . . . . . . . . . . . 22
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Contact information. . . . . . . . . . . . . . . . . . . . . 23
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 22 October 2015
Document identifier: 74LV4052_Q100