DATA SHORT To request the full datasheet, please visit www.intersil.com/products/isl78365 Automotive High Speed Quad Laser Diode Driver ISL78365 Features The ISL78365 high speed quadruple output Laser Diode Driver (LDD) is designed to support high speed RGB/RGGB laser scanning projection systems. • High speed quadruple output laser diode driver supporting up to 150MHz maximum output pixel clock Each output driver channel consists of independent threshold and color DACs for greater laser control and flexibility. Separate scale DACs allow independent scaling of both threshold and color DAC output values to control the projector brightness or provide simple Automatic Power Calibration (APC) for laser based systems. Pixel data information is transferred through the LDD's high speed 10-bit parallel video interface. There are two parallel interface modes to allow 3 or 4 color pixel data to be entered efficiently. Pixel data employs a double data rate scheme, allowing video data to be transferred using both edges of the clock. • Fast output switching speeds with pulse rise/fall times of 1.5ns for crisp pixels • Up to 750mA of peak current output per channel • Intersil laser voltage sampler function with integrated dynamic power optimization controller to dramatically minimize system power • Flexible data order supports different RGB LD opto-mechanical placement • Blanking time power reduction to reduce LDD current consumption • Programmable multi-pulse Return to Zero (RTZ) function to provide maximum flexibility Applications • Single 3.3V supply and 1.8V video interface compatible for low power • RGB scanning laser projection system • Laser based projectors • 3-wire SPI interface • Generic laser based applications requiring multiple independently controlled lasers or a single high current driver • Operating temperature range: -40°C to +125°C • AEC-Q100 qualified 12V FB 3.3/2.5/1.8V FB4 FB = FERRITE BEAD FB3 DC–DC Reg4 DC–DC Reg3 TEST POINT VSL 3.3V FB VDD_A1 VDD_A2 DPM4 VDD DPM2 ISL78365 SEN SCLK SDIO EXTERNAL EVENT 1 EXTERNAL EVENT 2 VIDEO DATA ASIC or MEMS CONTROLLER RGB(24) DPM1 LD1 FB1 LD2 LD4 LD3 IOUT1 IOUT2 IOUT3 L_EN 10 DC–DC Reg2 DC–DC Reg1 DPM3 VSS MCU FB2 MON VDD_DAC IOUT4 RSET D[9..0] CLK PGND SYNC PGND PGND RTZ PGND LOWP EPAD LD1 to 4 can be in any order LD1 LD2 LD3 LD4 R G1 G2 B B G1 G2 R FIGURE 1. TYPICAL APPLICATION DIAGRAM May 27, 2016 FN8831.1 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2016. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL78365 Functional Block Diagram CLK /10 PLL SYNC DATA INTERFACE AND MULTI PULSES RTZ D[9..0] RTZ LOWP /10 /10 Color Scale Icolor Iset IOUT1 /8 /6 /10 L_EN /10 Ithreshold Thres. Scale Color Scale Icolor Iset SEN SERIAL INTERFACE SPI SCLK /8 IOUT2 /8 /6 Ithreshold Thres. Scale SDIO /10 /10 LASER VOLTAGE SAMPLER R G G B Color Scale Icolor Iset /8 IOUT3 /8 /6 Ithreshold Thres. Scale DPM1 /10 DPM2 POWER OPTIMIZERTM DPM3 /10 Color Scale Icolor Iset DPM4 IOUT4 /8 Ref. RSET Iset /6 Ithreshold Thres. Scale DIE TEMP. FIGURE 2. FUNCTIONAL BLOCK DIAGRAM Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING ISL78365ARZ 78365 ARZ ISL78365EVAL1Z Evaluation Board TEMP RANGE (°C) -40 to +125 PACKAGE (RoHS Compliant) 40 Ld WQFN PKG. DWG. # L40.6x6C NOTES: 1. Add “-T” suffix for 4k unit or “-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see product information page for ISL78365. For more information on MSL please see techbrief TB363. Submit Document Feedback 2 FN8831.1 May 27, 2016 ISL78365 Pin Configuration RSET MON VSS_A SCN_MODE VDD_A1 VDD LOWP VSL RTZ CLK ISL78365 (40 LD WQFN) TOP VIEW 40 39 38 37 36 35 34 33 32 31 D0 1 30 VDD_DAC D1 2 29 IOUT1 EN1/D2 3 28 PGND D3 4 27 IOUT2 EN2/D4 5 26 PGND D5 6 25 IOUT3 EN3/D6 7 24 PGND D7 8 23 IOUT4 EN4/D8 9 22 PGND 21 L_EN D9 10 VDD_A2 DPM4 DPM3 DPM2 DPM1 SEN SDIO SCLK VSS SYNC 11 12 13 14 15 16 17 18 19 20 Pin Descriptions PIN NAME PIN NUMBER I/O PIN TYPE D0 1 Input Digital D1 2 EN1/D2 3 D3 4 EN2/D4 5 D5 6 EN3/D6 7 D7 8 EN4/D8 9 D9 10 SYNC 11 Input Digital This pulse aligned with the CLK edge indicates the data on that edge is the final word of the sequence. The SYNC signal can be operated at 1.8V, 2.5V or 3.3V CMOS logic levels. The VSL pin configures this setting (see VSL pin for description.) By default, it is 1.8V. SCLK 13 Input Digital The SCLK is the serial interface clock signal. It can be operated at 1.8V, 2.5V or 3.3V CMOS logic level. The VSL pin configures this setting (see VSL pin for description.) By default, it is 1.8V. SDIO 14 Bi-Dir Digital The SDIO is the serial interface data signal. It can be operated at 1.8V, 2.5V or 3.3V CMOS logic level. The VSL pin configures this setting (see VSL pin for description.) By default, it is 1.8V. SEN 15 Input Digital The SEN is the serial interface select enable signal. It can be operated at 1.8V, 2.5V or 3.3V CMOS logic level. The VSL pin configures this setting (see VSL pin for description.) By default, it is 1.8V. Submit Document Feedback PIN DESCRIPTION D0 to D9 form the parallel interface data bus. These 10 pins (bits) form each IOUT DAC’s data. There are two modes on latching the data into the device. These 10 signals can be operated at 1.8V, 2.5V or 3.3V CMOS logic levels. The VSL pin configures this setting (see VSL pin for description.) By default, it is 1.8V. 3 FN8831.1 May 27, 2016 ISL78365 Pin Descriptions (Continued) PIN NAME PIN NUMBER I/O PIN TYPE DPM1 16 Output Analog Dynamic power management to control the voltage headroom at IOUT1. This is current output and the current is sunk from this pin to ground. If DPM function is not implemented, this pin should be left open. DPM2 17 Output Analog Dynamic power management to control the voltage headroom at IOUT2. This is current output and the current is sunk from this pin to ground. If DPM function is not implemented, this pin should be left open. DPM3 18 Output Analog Dynamic power management to control the voltage headroom at IOUT3. This is current output and the current is sunk from this pin to ground. If DPM function is not implemented, this pin should be left open. DPM4 19 Output Analog Dynamic power management to control the voltage headroom at IOUT4. This is current output and the current is sunk from this pin to ground. If DPM function is not implemented, this pin should be left open. L_EN 21 Input Digital The L_EN signal is an active high input with 1.8V logic threshold and it is 3.3V tolerance. It has a programmable current pull-up to VDD_A (3.3V) supply. IOUT4 23 Output Analog Current output for the IOUT4 laser. Current is sunk from the laser cathode to ground. IOUT1, IOUT2, IOUT3, IOUT4 have similar performance capability. IOUT3 25 Output Analog Current output for the IOUT3 laser. Current is sunk from the laser cathode to ground. IOUT1, IOUT2, IOUT3, IOUT4 have similar performance capability. IOUT2 27 Output Analog Current output for the IOUT2 laser. Current is sunk from the laser cathode to ground. IOUT1, IOUT2, IOUT3, IOUT4 have similar performance capability. IOUT1 29 Output Analog Current output for the IOUT1 laser. Current is sunk from the laser cathode to ground. IOUT1, IOUT2, IOUT3, IOUT4 have similar performance capability. RSET 31 Output Analog The RSET pin connects to a resistor to ground the device to set the bias current for the device. A 13kΩ, 1% tolerance resistor is recommended value. The placement of the RSET resistor must be as close as possible to the pin. MON 32 Output Test This pin is reserved for factory testing. It must be left floating. Do not tie to ground. SCN_ MODE 34 Input Test This pin is reserved for factory testing. This pin must tie to ground for normal operation. LOWP 37 Input Digital LOWP is an active high input signal. When asserted, the device goes into the low power mode. The operating voltage is based on the VSL input voltage (see VSL pin description.) An high resistance to ground resistor can be used to bias the pin to ground. RTZ 39 Input Digital RTZ is an active high input signal. The operating voltage depends on the VSL input voltage and register 0x08[7:6] setting (see VSL pin description). When asserted, it causes the RTZ function to be driven on to the IOUTx. If the RTZ function is not implemented, this pin should be tied to ground. CLK 40 Input Digital CLK is the input data clock that latches the data D[0:9] into the parallel data interface. Data is latched on each edge of the CLK; thus its signal integrity is critical to correctly latching data into the device. If interface method chosen to use PLL only, the CLK pin should be tied to ground. The CLK can be operated with different voltage level and it is configured by the VSL pin (see VSL pin for description). VDD_DAC 30 - Power VDD_DAC is the 3.3V supply pin for the output DAC’s. Due to large current changes during switching of these DACs, a good size decoupling capacitor pairs should be tied to this pin. We recommend the use of 10µF and 0.1µF capacitor pair with the smallest value capacitor placed closest to the pin. VDD_A1 35 - Power VDD_A1 is the 3.3V supply pin for the DPM and other DACs. A decoupling capacitor pair of 0.1µF and 4.7µF should be tied to this pin with the smallest value placed closest to the pin. VDD_A2 20 - Power VDD_A2 is the 3.3V supply pin for the DPM circuits. A decoupling capacitor pair of 0.1µF and 1.0µF should be tied to this pin with the smallest value placed closest to the pin. VDD 36 - Power VDD is the 3.3V supply pin for the analog and Digital block. A decoupling capacitor pair of 0.1µF and 1.0µF should be tied to this pin with the smallest value placed closest to the pin. Submit Document Feedback 4 PIN DESCRIPTION FN8831.1 May 27, 2016 ISL78365 Pin Descriptions (Continued) PIN NAME PIN NUMBER I/O PIN TYPE VSL 38 - Power PIN DESCRIPTION VSL is the digital I/O pin supply rail. An 1.8V, 2.5V and 3.3V can be applied to this pin. The register 0x08 Bits[7:6] must be set to the applied voltage to correctly configure the I/O pin voltage threshold. This pin should be decoupled using an 0.01µF and 1.0µF capacitor pair to ground. The smallest value capacitor should be placed closest to the VSL pin. This pin sets the I/O voltage threshold for the following signals: CLK, D[0:9], SYNC, LOWP, RTZ, SCLK, SDIO and SEN. VSS_A 33 - Power VSS_A is ground return for VDD_A1 and VDD_A2. GND connections should be made on the PCB to all GND pins. Decoupling capacitors for VDD_A1 and VDD_A2 returns should be placed as close as possible to this pin. PGND 22, 24, 26, 28 - Power These four pins are the ground returns for the IOUT DAC. VSS 12 - Power GND connections should be made on the PCB to all GND pins. EPAD PAD - This is the thermal pad of the device and can be connected to ground. It is important to remove as much of the thermal heat away from the device as possible. We recommend to place a thermal pad under the EPAD using our guideline given in the “General PowerPAD Design Considerations”. NOTE: Pins with the same name are internally connected together; however, LDD pins must not be used for connecting together external components or features. For additional products, see www.intersil.com/en/products.html Intersil Automotive Qualified products are manufactured, assembled and tested utilizing TS16949 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 5 FN8831.1 May 27, 2016